EP0921638B1

EP0921638B1 - Bus driver circuit

Info

Publication number: EP0921638B1
Application number: EP98309960A
Authority: EP
Inventors: Gerd Rombach
Original assignee: Texas Instruments Deutschland GmbH
Current assignee: Texas Instruments Deutschland GmbH
Priority date: 1997-12-05
Filing date: 1998-12-04
Publication date: 2003-05-21
Anticipated expiration: 2018-12-04
Also published as: DE69814804D1; DE69814804T2; JPH11261403A; EP0921638A2; EP0921638A3

Description

Field Of The Invention

The present invention relates to integrated bus drivers.

Background: Bus Interface Device

Integrated bus interface devices must be capable of sinking or sourcing high output current when the output switches. A current in the range from 50 - 100mA is typical. The high current is necessary to achieve fast propagation delay times (typically driving a 75-ohm transmission line). After the output has reached the stable steady state, only a small part of the switching current, or even no current is needed.
In BiCMOS chips, bipolar NPN transistors were traditionally used to deliver the high sink current that was needed for bus driver devices. However, while bipolar output drivers provide fast high-current output switching, they have the disadvantage of a large static power consumption.
In present day computer systems, the buses spend 80% or more of their time in the stable, inactive (low or high) state. Modern bus interface ICs take this into account. The circuits are designed for self-control of internal power consumption based upon what is needed to drive the output load. Power-On-Demand ("POD") circuits reduce power drain. The first circuits employing this feature appeared in 1992. However, a major limitation of these earlier designs is that the output clamping voltage is dependent on the output current. If current through the output transistor increases, the base-emitter voltage Vbe also increases, due in part to the emitter resistance of the output transistor. See Applicant's prior German application (#De 195 47 754 C1, Control Circuit for a BiCMOS Bus Driver).
Another document, JP-A- 4 040 115 discloses a bus drive circuit with a bipolar output transistor and with a field-effect transistor for detecting variations in the output voltage. A reference voltage generator is formed by a series-connection of a schottky diode and a pm diode. The base current of the output transistor is varied to oppose variations of the output voltage.

Summary Of The Present Invention

The present application discloses an innovative technique for controlling power consumption in a BiCMOS bus driver circuit. A bipolar output driver is used with a MOS base drive circuit which includes a feedback relationship; as output current rises, the base current also rises. The base drive circuit reacts quickly to changes in the load impedance. The bipolar output driver still provides fast switching, and high peak current when needed, but the base drive circuit limits the static base current to a small value except when more is needed. The preferred feedback circuit configuration is nearly temperature and process compensated, and therefore easy to implement in different processes.
Thus the disclosed innovations reduce wasted power consumption. Moreover, the disclosed innovations can be used advantageously for all bus driver devices that are processed in BiCMOS technology. Another advantage is that the base current of the lower output transistor is controlled such that the output voltage stays constant regardless of how large or small the output sink current is. Another advantage is that the power consumption of the circuit is strongly related to the output sink current. Another advantage is that the technique works in the various power supply regimes of 2.5V, 3.3V, or 5.0V.

Brief Description of the Drawings

The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
Figure 1 shows a preferred embodiment of the circuit.
Figure 2 shows a prior art circuit for the lower output transistor of a bus driver.
Figure 3 shows a prior art driver circuit where base current is switch controlled to a fixed resistor value.
Figure 4 shows a typical integrated circuit chip with the driver circuit.

Detailed Description of the Preferred Embodiments

The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. Moreover, some statements may apply to some inventive features but not to others.
Figure 2 shows the principle circuit for the lower output transistor of a bus driver. The clamping diode D10 is used to prevent the output cransistor Q10 from saturating. The base current of Q10 is defined by the resistor value of R10. The resistor has to be designed small enough to guarantee a maximum value drive sink current at output OUT10. If the actual drive sink current is less than the maximum value, a part of the base current will flow through the clamping diode D10. Thus the current will not be available at the output, but be conducted through the diode and wasted.
Figure 3 shows a prior art driver circuit where base current is switch controlled to a fixed resistor value. When the input IN is low, transistor Q31 is biased "Off" since no base current exists. Transistor Q30 conducts based upon the base current developed from resistor R30. When the input IN is high, transistor Q31 is biased to conduct based upon the R30/R31 divider. In this case, most of the base current of the lower output transistor Q31 will sink through the clamping diode to ground. (The lower output transistor Q31 of a bus driver is usually clamped by a Schottky diode D31 to prevent the transistor from going into saturation.) This part of the current will be wasted at that time.
Figure 1 shows a preferred embodiment of the circuit. NPN bipolar transistor Q1 is the output driver. The base current of Q1 is not set by a fixed resistor value, as is done in conventional circuits. Instead, the base current is controlled by the On-resistance of the NMOS transistors N1 and N0, and the resistance R3.
An output signal (from the internal circuits of the chip) is applied at terminal IN to the gate of transistor N0. When the signal at IN is high, the transistor Q1 is turned "On" to pull the OUT terminal low. This state is the one where the static power dissipation issues discussed above are most critical, and thus most of the following discussion will focus on this output state.
Transistor N1 is turned "On" or "Off" by transistor N2. The state of transistor N2 depends upon the output voltage Vout, and is set by the network of transistors N2, N3, and Q2, and Schottky diode D1. When the output current Iout rises, the voltage across the collector-emitter of Q1 (Vout) will also rise, until the base current of transistor Q1 is regulated to a higher value.
Resistor R2, NMOS transistor N3, and bipolar transistor Q2, comprise a reference voltage circuit 100 which generates a reference voltage Vref at node s3. This reference voltage Vref is set by a NMOS transistor N3 threshold voltage Vt_N3, and a base-emitter voltage Vbe_Q2 of a bipolar N?N transistor Q2. Typical approximate voltage values for each are Vt_N3 = 0.6V and Vbe_Q3 = 0.75V. The gate of NMOS transistor N2 is connected to the reference voltage circuit 100 at node s3. Transistor N2 becomes conducting if the voltage across transistor N2, diode D1, and the output voltage Vout, is less than the reference voltage Vref at node s3. Correspondingly, transistor N2 becomes less conducting as the output voltage rises, and turns "Off" when its source voltage, plus its threshold voltage, becomes greater than the reference voltage.
When the voltage at the output OUT rises, transistor N2 turns "Off", voltage at node s2 rises, and transistor N1 conducts. When transistor N1 conducts, the base drive of transistor Q1 increases. (Both transistors N1 and N2 are biased weakly, such that transistor N1 is weakly on with low current demands at the output, and heavily on for high current demands at the output.) Transistor Q1 will turn "On" more, and the output voltage Vout will fall back to the initial value.
Since the threshold voltages (Vt, Vbe, and Vd) are fixed, and set by process parameters, the switching of transistor N2 depends only upon the output voltage Vout. The forward voltage Vd of the Schottky diode D1 is approximately 0.5V. The value of the output voltage Vout is approximately 0.25V, or essentially the difference between the voltage drop across the base-emitter of transistor Q2, and the forward voltage of the Schottky diode D1. That is, Vout = (Vbe_Q2 + Vt_N3) - (Vd + Vt_N2)
= (0.75 + 0.6) - (0.5 + 0.6) = 0.25V.
Typical devices sizes for a 0.6 micron process, and resistor values of 50K ohms for both R1 and R2, may be for example 50x60 square micrometers in a 500 ohm/square sheet resistance, for devices R1, and R2. Approximate transistor sizes are the following;
N1=40/0.6, N2=8/0.6, N3=8/0.6, Q1 emitter area = 250x0.6 for 60 milliamps, Q2 emitter area = 3x0.6, D1 Schottky area = 30.
Key features of the innovative circuit are that the output voltage Vout is clamped, preventing the transistor Q1 from going into saturation. Arocher feature is that the base current of transistor Q1 is controlled so that the output voltage stays constant regardless of transistor Q1 collector current. Another feature is that the output voltage is nearly temperature compensated, since the temperature shift of the components in the control circuit cancel each other. The gate voltages of NMOS transistors N2 and N3 have the same temperature drift.
Furthermore, the diode D1 forward voltage (Vd) temperature drift is compensated for by the base-emitter voltage drift of transistor Q2. Another feature is that the output voltage is partly process compensated - the influence of CMOS transistors N2 and N3 threshold voltages are cancelled out. Finally, the output clamping voltage is independent of the output current.
Note also that, in the presently preferred embodiment, the delay-limiting path of the feedback circuit includes only MOS transistors N1 and N2. Thus this feedback circuit can react quickly to load variations.
Figure 4 shows a typical integrated circuit chip with the driver circuit. IC 400 comprises a core circuitry 404 surrounded by I/O circuitry on the periphery 402 of the chip. The I/O circuitry comprises static discharge protection circuitry 406 and driver circuitry 408. Driver circuits like those of Figure 1 would preferably be used for some (but not necessarily all) of the output drivers in driver circuitry 408.
The illustrated embodiment is a simple low-side driver configuration. However, of course a variety of port interface circuits can be combined with the circuitry shown. For example, an active pull-up circuit can also be used in combination with the driver circuit portion shown.
A complementary circuit configuration can also be used to limit static base current to a PNP high-side driver.
For another example, within the constraints well-known to those of ordinary skill, a variety of well-known reference circuit configurations can be substituted for those shown.
For another example, within the constraints well-known to those of ordinary skill, components may be added to speed up the feedback circuit.
For another example, within the constraints well-known to those of ordinary skill, components may be added to switch off the whole circuit from its supply voltage, during a power-down event.

Claims

An integrated bus interface driver circuit, comprising

a bipolar transistor (Q1) connected for controllably driving an output terminal (OUT) to a defined level in response to a bus drive signal (IN); and including

a feedback circuit, comprising one or more field-effect transistors connected for detecting variations in the voltage (Vout) of said output terminal (OUT), and accordingly, when a variation in said output voltage (Vout) is detected, vary the base current of said bipolar transistor (Q1) thereby to vary the current applied by said bipolar transistor (Q1) at said output terminal (OUT) to oppose said variation in the voltage (Vout) of said output terminal (OUT) and maintain said defined level,
wherein the control terminal of one (N2) of said field-effect transistors, which is connected to follow the voltage (Vout) of said output terminal (OUT), is connected to a. reference voltage (Vref), said reference voltage being set with respect to said defined output level; and
wherein said feedback circuit comprises a first field-effect transistor (N1) for providing base current to said bipolar transistor (Q1), and a second field-effect transistor (N2) which is the one connected to follow the voltage (Vout) of said output terminal, the second field-effect transistor (N2) controlling a gate voltage of said first field-effect transistor (N1), and the first field-effect transistor (N1) being series-connected with an input field effect-transistor (N0).
The integrated circuit of Claim 1, wherein the feedback circuit further comprises a circuit for generating the reference voltage (Vref).
The integrated circuit of Claim 2, wherein the circuit for generating the reference voltage (Vref) comprises a series connection of a gate-drain-connected field effect transistor (N3) and a base-collector-connected bipolar transistor (Q2).
The integrated circuit of any of Claims 1 to 3, wherein said feedback circuit is temperature compensated.
the bus drive signal being applied to the control terminal of said input transistor.
The integrated circuit of Claim, further comprising a Schottky diode (D1) disposed between a source of said second field-effect transistor (N2) and said output terminal (OUT).
A method for controlling a bus interface circuit, comprising the steps of:

controllably driving an output terminal (OUT) to a defined level with a bipolar transistor (Q1) in response to a bus drive signal (IN),

connecting a feedback circuit comprising one or more field-effect transistors to vary the base current of said bipolar transistor (Q1) when said output voltage (Vout) varies, to thereby vary the current applied by said bipolar transistor (Q1) at said output terminal (OUT) to oppose any variation in the voltage of said output terminal (OUT) and maintain said defined level, connecting one (N2) of said field-effect transistors to follow the voltage (Vout) of said output terminal (OUT) and connecting the control terminal of said field-effect transistor (N2) to a reference voltage (Vref) and setting said reference voltage with respect to said defined output level;

providing said base current by a further field - effect transistor (N1) connected in series with an input field-effect transistor (N0),

applying the bus drive signal (IN) to the control terminal of the input field-effect transistor (N0),

and the further field-effect transistor (N1) having its control terminal connected to the field - effect transistor (N2) that follows the voltage of the output terminal.
The method of Claim 6, wherein the step of connecting the control terminal with a reference voltage includes the step of connecting the control terminal with a circuit for generating the reference voltage comprising a series connection of a gate-drain-connected field effect transistor (N3) and a base-collector-connected bipolar transistor (Q2).