EP0913782A3 - Verifying hardware in its software context and vice-versa - Google Patents

Verifying hardware in its software context and vice-versa Download PDF

Info

Publication number
EP0913782A3
EP0913782A3 EP98308795A EP98308795A EP0913782A3 EP 0913782 A3 EP0913782 A3 EP 0913782A3 EP 98308795 A EP98308795 A EP 98308795A EP 98308795 A EP98308795 A EP 98308795A EP 0913782 A3 EP0913782 A3 EP 0913782A3
Authority
EP
European Patent Office
Prior art keywords
centric
software
hardware
partial order
order reduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98308795A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0913782A2 (en
Inventor
Robert Paul Kurshan
Vladimir Levin
Marius Minea
Doron A. Peled
Husnu Yenigun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of EP0913782A2 publication Critical patent/EP0913782A2/en
Publication of EP0913782A3 publication Critical patent/EP0913782A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3604—Software analysis for verifying properties of programs
    • G06F11/3608—Software analysis for verifying properties of programs using formal methods, e.g. model checking, abstract interpretation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3604—Software analysis for verifying properties of programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Debugging And Monitoring (AREA)
  • Stored Programmes (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Devices For Executing Special Programs (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP98308795A 1997-11-03 1998-10-27 Verifying hardware in its software context and vice-versa Withdrawn EP0913782A3 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US6408097P 1997-11-03 1997-11-03
US64080 1997-11-03
US09/172,484 US6209120B1 (en) 1997-11-03 1998-10-14 Verifying hardware in its software context and vice-versa
US172484 1998-10-14

Publications (2)

Publication Number Publication Date
EP0913782A2 EP0913782A2 (en) 1999-05-06
EP0913782A3 true EP0913782A3 (en) 2001-02-21

Family

ID=26744122

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98308795A Withdrawn EP0913782A3 (en) 1997-11-03 1998-10-27 Verifying hardware in its software context and vice-versa

Country Status (6)

Country Link
US (1) US6209120B1 (ko)
EP (1) EP0913782A3 (ko)
JP (1) JPH11213031A (ko)
KR (1) KR100329305B1 (ko)
CA (1) CA2251244A1 (ko)
IL (1) IL126736A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117093434B (zh) * 2023-10-20 2024-01-30 深圳品网科技有限公司 一种用于笔记本电脑的开关机自检测方法

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060117274A1 (en) * 1998-08-31 2006-06-01 Tseng Ping-Sheng Behavior processor system and method
US9195784B2 (en) * 1998-08-31 2015-11-24 Cadence Design Systems, Inc. Common shared memory in a verification system
US6681374B1 (en) * 1999-06-09 2004-01-20 Lucent Technologies Inc. Hit-or-jump method and system for embedded testing
US6385757B1 (en) * 1999-08-20 2002-05-07 Hewlett-Packard Company Auto design of VLIW processors
US6751582B1 (en) * 1999-09-09 2004-06-15 International Business Machines Corporation Method and system for enhanced design validation through trace tailoring
KR100368546B1 (ko) * 2000-01-18 2003-01-24 한국 Mds (주) 실제 프로세서를 이용한 낙관적 실행에 의한하드웨어-소프트웨어 통합 검증방법
US20050192789A1 (en) * 2000-06-30 2005-09-01 Jin Yang Methods for formal verification on a symbolic lattice domain
US7031896B1 (en) 2000-06-30 2006-04-18 Intel Corporation Methods for performing generalized trajectory evaluation
US6725431B1 (en) 2000-06-30 2004-04-20 Intel Corporation Lazy symbolic model checking
US6591400B1 (en) 2000-09-29 2003-07-08 Intel Corporation Symbolic variable reduction
US6643827B1 (en) 2000-09-30 2003-11-04 Intel Corporation Symbolic model checking with dynamic model pruning
US7165231B2 (en) * 2000-12-18 2007-01-16 Yardstick Research, Llc Method and system for incremental behavioral validation of digital design expressed in hardware description language
US7146605B2 (en) * 2001-01-15 2006-12-05 International Business Machines Corporation Automatic abstraction of software source
US6792580B2 (en) * 2001-01-31 2004-09-14 Kabushiki Kaisha Toshiba Method and computer program product for software/hardware language model conversion
US7366650B2 (en) * 2001-04-12 2008-04-29 Arm Limited Software and hardware simulation
US20030172177A1 (en) * 2001-12-06 2003-09-11 Kersley Ian P. System and method for verifying a device
JP2005063136A (ja) * 2003-08-12 2005-03-10 Toshiba Corp 半導体集積回路の設計装置、設計方法、及び設計プログラム
US7231571B2 (en) * 2005-04-28 2007-06-12 Yardstick Research, L.L.C. Single-pass methods for generating test patterns for sequential circuits
US7783467B2 (en) 2005-12-10 2010-08-24 Electronics And Telecommunications Research Institute Method for digital system modeling by using higher software simulator
KR100857903B1 (ko) * 2005-12-10 2008-09-10 한국전자통신연구원 상위 프로그래밍 언어를 이용한 디지털 시스템 설계 방법
US7958421B2 (en) 2007-08-16 2011-06-07 Yardstick Research, Llc Single-pass, concurrent-validation methods for generating test patterns for sequential circuits
US8326592B2 (en) * 2007-12-21 2012-12-04 Cadence Design Systems, Inc. Method and system for verifying electronic designs having software components
US8244516B2 (en) * 2008-06-30 2012-08-14 International Business Machines Corporation Formal verification of models using concurrent model-reduction and model-checking
US8156395B2 (en) * 2008-07-28 2012-04-10 Yardstick Research, Llc Methods for generating test patterns for sequential circuits
KR20100084036A (ko) * 2009-01-15 2010-07-23 삼성전자주식회사 소프트웨어의 에러 검출 장치 및 방법
US8797330B1 (en) * 2013-10-18 2014-08-05 Google Inc. Systems and methods for detecting and animating changes in application state
US10333696B2 (en) 2015-01-12 2019-06-25 X-Prime, Inc. Systems and methods for implementing an efficient, scalable homomorphic transformation of encrypted data with minimal data expansion and improved processing efficiency
CN104503837B (zh) * 2015-01-15 2017-10-10 南京大学 基于偏序规约的中断驱动系统有界模型检验方法
US9996637B2 (en) 2015-07-30 2018-06-12 International Business Machines Corporation Method for verifying hardware/software co-designs
US10839124B1 (en) 2019-06-26 2020-11-17 Amazon Technologies, Inc. Interactive compilation of software to a hardware language to satisfy formal verification constraints

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2815281B2 (ja) * 1993-04-19 1998-10-27 株式会社ピーエフユー デジタル回路設計支援システムおよびその方法
US6044211A (en) * 1994-03-14 2000-03-28 C.A.E. Plus, Inc. Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description
US5537580A (en) * 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5870588A (en) * 1995-10-23 1999-02-09 Interuniversitair Micro-Elektronica Centrum(Imec Vzw) Design environment and a design method for hardware/software co-design
JPH09153077A (ja) * 1995-12-01 1997-06-10 Pfu Ltd デジタル回路設計支援システムおよびデジタル回路のハードウェアおよびソフトウェアの設計方法

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
ALUR R ET AL: "Partial-order reduction in symbolic state space exploration", COMPUTER AIDED VERIFICATION. 9TH INTERNATIONAL CONFERENCE, CAV'97. PROCEEDINGS, COMPUTER AIDED VERIFICATION. 9TH INTERNATIONAL CONFERENCE, CAV'97. PROCEEDINGS, HAIFA, ISRAEL, 22-25 JUNE 1997, 1997, Berlin, Germany, Springer-Verlag, Germany, pages 340 - 351, XP000965351, ISBN: 3-540-63166-6 *
FISLER K ET AL: "Verifying VHDL designs with COSPAN", FORMAL HARDWARE VERIFICATION. METHODS AND SYSTEMS IN COMPARISON, 1997, BERLIN, GERMANY, SPRINGER-VERLAG, GERMANY, pages 206 - 247, XP000965350, ISBN: 3-540-63475-4 *
KURSHAN R P: "Formal verification in a commercial setting", PROCEEDINGS 1997. DESIGN AUTOMATION CONFERENCE, 34TH DAC, PROCEEDINGS OF 34TH DESIGN AUTOMATION CONFERENCE, ANAHEIM, CA, USA, 9-13 JUNE 1997, 1997, New York, NY, USA, ACM, USA, pages 258 - 262, XP000960828, ISBN: 0-89791-920-3 *
LEVIN V ET AL: "A bilingual specification environment for software/hardware co-design", PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTER AND INFORMATION SCIENCES. ISCIS, PROCEEDINGS OF 11TH INTERNATIONAL SYMPOSIUM ON COMPUTER AND INFORMATION SCIENCES, ANTALYA, TURKEY, 6-8 NOV. 1996, 1996, Ankara, Turkey, Middle East Tech. Univ, Turkey, pages 153 - 162 vol.1, XP000965370, ISBN: 975-429-103-9 *
PELED D: "Combining partial order reductions with on-the-fly model-checking", FORMAL METHODS IN SYSTEM DESIGN, JAN. 1996, KLUWER ACADEMIC PUBLISHERS, NETHERLANDS, vol. 8, no. 1, pages 39 - 64, XP000965348, ISSN: 0925-9856 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117093434B (zh) * 2023-10-20 2024-01-30 深圳品网科技有限公司 一种用于笔记本电脑的开关机自检测方法

Also Published As

Publication number Publication date
EP0913782A2 (en) 1999-05-06
JPH11213031A (ja) 1999-08-06
IL126736A (en) 2002-11-10
IL126736A0 (en) 1999-08-17
KR19990066809A (ko) 1999-08-16
KR100329305B1 (ko) 2002-09-27
US6209120B1 (en) 2001-03-27
CA2251244A1 (en) 1999-05-03

Similar Documents

Publication Publication Date Title
EP0913782A3 (en) Verifying hardware in its software context and vice-versa
EP1983754A3 (en) Information system
EP0838772A3 (en) Method and apparatus for design verification using emulation and simulation
GB9926107D0 (en) System and method fo9r automatically generating computer language grammers in browable form
EP0837383A3 (en) Method and apparatus for data verification
EP0816981A3 (en) Method and apparatus for eyetrack-driven captioning
EP0933712A3 (en) Method and system for generating document summaries with navigation information
EP0834853A3 (en) Method and apparatus for presenting client side image maps
ZA97860B (en) Skin smoothing compositions containing hydroxyacids and methods for using same.
EP1085417A3 (en) Method and system for forming skeletons for generating verification systems
EP1016963A3 (en) Run-time addition of interfaces
EP1126436A3 (en) Speech recognition from multimodal inputs
EP1037131A3 (en) Data processing system and method for mutual identification between apparatuses
GB9615624D0 (en) Personal computer having security function,security method therefor,security d evice installation and detachment methods
AU4432399A (en) Database for use in method and apparatus for displaying television programs and related text
EP0913781A3 (en) Static partial order reduction
EP0862273A3 (en) Data padding method and apparatus
TW346607B (en) Method of levying accounting data for the use of services that are programmed or available via a program
DE59802270D1 (de) Verfahren zur herstellung von wässrigen, schutzkolloid-stabilisierten vinylester-homo- und -co-polymerdispersionen
EP1014309A3 (en) Multi-level simulation
EP0817016A3 (en) Software ICS for high level application frameworks
EP0756250A3 (en) Method for signature verification
HK1009861A1 (en) Program execution method and device using the same.
WO2001033388A3 (en) Method and system for multi-user access of a database over a network
EP0825558A3 (en) Method and apparatus for displaying free-form graphic objects

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20010810

AKX Designation fees paid

Free format text: DE FR GB IT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20030506