EP0894301A1

EP0894301A1 - Method and apparatus for power management using power control

Info

Publication number: EP0894301A1
Application number: EP97915057A
Authority: EP
Inventors: David J. Allard; Neal A. Osborn
Original assignee: Rockwell Semiconductor Systems Inc
Current assignee: Lakestar Semi Inc
Priority date: 1996-03-14
Filing date: 1997-03-13
Publication date: 1999-02-03
Also published as: AU2210097A; WO1997034218A1; JP2000506649A

Abstract

A method and apparatus which conserves power in computing and communications devices by providing a real-time alarm clock (18) that allows the processor (12) in the device to turn off during specific fixed periods of time. These periods of times may be measured by absolute or relative time by the real-time alarm clock (18) of the present invention. As a result, the processor (12) is relieved of the task of timing events, whether external event, internal events or set by user input. This saves a significant amount of power because the real-time alarm clock (18) consumes much less power than the processor (12) and its associated circuitry. This results in extending the battery life of the device and/or in reducing its overall energy requirements.

Description

METHOD AND APPARATUS FOR POWER MANAGEMENT USING POWER CONTROL

TECHNICAL FIELD

This invention relates to digital processing systems, and more particularly, to a method and apparatus for conserving power in a digital processing system during selected periods of time.

BACKGROUND ART

Advances in digital electronics have resulted in computing systems which are both powerful and compact. This trend has reached the point where devices such as personal computers and telephones can be made completely portable. Portability, however, requires an adequate portable supply of electrical power. That is, the power supply must not be unduly heavy and bulky, and must provide the portable system with adequate power for a sufficiently long period of time before needing recharging or replacement.

Because of these requirements, battery life is of paramount importance in portable electronic systems. To extend battery life in portable computing and communication devices, much attention is given, by designers of these systems, to the ability to control power to as many subsections of the system as possible in a manner which expends a minimal amount of energy.

For example, one common power management technique is to halt a processor when it has nothing to do. Since a microprocessor's time scale is so vastly different from the human time scale, this can often be accomplished in a manner which is entirely transparent to the user. Typically, such "rest" or "sleep" schemes are based on external events, or on events beyond the control of the system. For example, it is common to stop a processor in charge of scanning a keyboard between individual keystrokes. In such systems, the processor starts, or wakes up in response to a keystroke, spends some time determining which key has been pressed, and then goes back into a sleep mode until the next keystroke. In other devices, such as battery operated calculators, a similar technique is employed to turn off the processor and display when a given period of time has elapsed without any external input (such as a keystroke).

Nevertheless, despite these techniques, there remains a relatively limited number of opportunities to conserve battery power by turning off a processor while waiting for external events. As a result, battery life in portable computing and communication devices is still generally too short in many circumstances.

Also, in some devices such as portable electronic messaging and communications equipment, generally the device must remain on in order to ensure that messages are received. However, the user's individual schedule may only necessitate the receipt of messages at specific times of the day. As a result, power is unnecessarily wasted by having the receiving processor on for longer periods of time than is absolutely necessary.

Accordingly, it would be desirable to provide new ways to conserve power in systems where electrical power is in limited supply. To this end, it would be desirable to provide a system which enables a digital processing system to turn power off to its microprocessor at various times when the processing power is not needed. It would also be desirable to provide a system which enables a user to preset the times when the system is on and off, based on the desires and routine of the individual user.

DISCLOSURE OF INVENTION

The present invention is a method and apparatus which conserves power in computing and communication devices by providing a real-time alarm clock which allows the processor in the device to turn itself off during specific fixed periods of time. The timed event can be measured by either absolute or relative time by the real-time alarm clock. Prior power convention techniques generally relied on external events to determine when to turn a processor on or off. The present invention recognizes that during many internal events, computing and communication devices utilize the processor for nothing more than the timing of the internal event. For example, conventionally, a processor may be used to time an event via software timing loops or by incrementing counters based on a timer chip. In the present invention, the processor is relieved of these duties, and a separate real-time alarm clock is utilized instead. This saves power because the real-time alarm clock consumes much less power than the processor together with its associated circuitry (such as its oscillator). For example, the real-time alarm clock of the present invention may consume 1/10,000 (one ten-thousandth) the power of the processor and its associated circuitry.

In accordance with one embodiment of the present invention, a method of conserving power in a system having a digital processor is provided. The method includes the steps of determining a period of time during which the operation of the processor is unnecessary. Next, the system turns off the processor at the beginning of this period of time. Then the system determines when this period of times has elapsed, and the processor is turned on in response to this determination. In another embodiment of the present invention, an apparatus is provided for implementing the method of the present invention described above. In a preferred embodiment of the present invention, the techniques of the present invention are adapted to a system and method for conserving power in a battery powered system having a processor and software controlling internal events. The system of the present invention enables the processor to be turned off during internal processor idle periods, and then turned back on by a real-time alarm clock.

Thus, in accordance with the present invention, portable computing and communication devices are provided with a technique for conserving power by turning off the processor during intervals timed by a real-time clock. This results in extending the battery life of the device and/or reducing the overall energy requirements of the device.

The details of the preferred embodiment of the present invention are set forth in the accompanying drawings and the description below. Once the details of the invention are known, numerous additional innovations and changes will become obvious to one skilled in the art.

BRIEF DESCRIPTION OF DRAWING

The objects, advantages and features of this invention will be more readily appreciated from the following detailed description, when read in conjunction with the accompanying drawing, in which: Figure 1 is a block diagram of an electronic system utilizing the real-time alarm clock in accordance with the present invention.

Figure 2 is a block diagram of the real-time clock shown in Figure 1 in accordance with the present invention. Figure 3 is a flow chart illustrating basic steps for the power manager software in executing the control processor idle task.

Figure 4 is a flow chart illustrating steps performed by the timer manager software adding timed events.

JFigure 5 is a flow chart illustrating steps performed by the timer manager software in servicing timed interrupts.

Like reference numbers and designations in the various drawings refer to like elements.

BEST MODE FOR CARRYING OUT THE INVENTION

Throughout this description, the preferred embodiment and examples shown should be considered as exemplars rather than limitations on the present invention.

The present invention is a method and apparatus for conserving power in computing and communication devices. This is particularly important in portable electronic devices which rely on battery power. The present invention provides a real¬ time alarm clock which allows a microprocessor to turn off during programmable periods of time. For example, the present invention enables a microprocessor to turn off during internal events of variable duration. Conventionally, the microprocessor may be used to time such internal events via software timing loops, or by incrementing counters based on a timer tick. In the present invention, a separate real-time alarm clock is used to relieve the microprocessor of these duties to allow the processor to be turned off during the timed interval. This will save considerable power because the real-time alarm clock is less power hungry than the CPU and associated circuitry. One embodiment of the invention is illustrated in the block diagrams of Figures 1 and 2. The electronic device 10 in Figure 1 incorporating the alarm clock of the present invention may comprise a portable computing or telecommunications device. Such devices will conventionally include a CPU core unit 12 driven by a high speed clock 14, and will also include an interrupt controller 16, all of which are conventional and known in the art. Also included in the memory of CPU 12 is power manager 29 and timer manager 31 software functions which are described in more detail below. Other components of the device 10 are not shown to simplify the drawing. In accordance with the present invention, the system 10 includes a real-time clock unit 18 which is coupled to both the CPU core 12, and the interrupt controller 16 through a read-write data bus 20. The real-time clock 18 is driven by an oscillator 22, which may include a 32.768 kHz oscillator. The CPU 12 is turned on and off by means of an on-off control line 26. The on-off control line 26 is used to turn off the CPU 12 by disconnecting the high speed clock 14 under control of both CPU 12 and interrupt controller 16. The off state is signaled by CPU 12 in response to a CP idle task within the Power Manager 29 program within the CPU core. The on state is signaled by interrupt controller 16. The interrupt controller 16 in general serves the function of latching asynchronous events and signaling the CPU core to process an exception to normal program flow. The interrupt controller receives external inputs along line 28, which may originate from a number of sources such as button switches, communication UARTs and power supplies.

Figure 2, illustrates in more detail the real-time clock 18 in accordance with the present invention. The real-time clock 18 includes an alarm register 30 which contains the data indicating the time that the next alarm is to occur. If the processor 12 is turned off, this alarm time determines when the processor 12 is turned back on. The alarm register 30 receives this information from data stored in the CPU memory (not shown) through the read- write bus 20. For example, user interface means (not shown) may be used to permit a user to set particular times of the day for the system 10 to be on or off. This information would then be communicated to the real-time clock 18 via read- write bus 20. For example, the user input is gathered by the CPU 12, scheduled by the timer manager 31 (see "Adding Timed Events" in Figure 4), and then communicated to the real-time clock 18 via the read/write data bus 20. A counter register 34 coupled to the oscillator 22 continuously counts and maintains the current time, whether that be real- time or a particular duration of time. A comparison register 36 receives the current value from the alarm register, and the counter register and compares the two. When those two values are equal, the comparison register 36 generates an output signal on line 38 which is fed to the interrupt controller 16. This signal will instruct the interrupt controller 16 to turn the CPU on by means of the on-off control line 26. It should be noted that the operation of on-off control 26 in the preferred embodiment will also turn off the high speed clock 14, rather than simply disconnecting this clock from the microprocessor. This results in additional power savings since the high speed clock 14 will not be running. Once the processor is operational, its execution is directed to the alarm clock (Interrupt Service Routine) ISR . This routing may service a single event or a list of timed events as depicted in

Figure 5 and described below.

In general, the present invention may be used in any electronic device where it is desired to conserve power. This is particularly important in battery operated electronic devices. By utilizing the real-time clock to keep track of real-time or timed intervals during which the microprocessor is not used, significant power savings are achieved. This is because the power consumed by the CPU 12 and the high speed clock 14 is significantly less than that of the real-time clock 18 and associated oscillator 22. For example, in many systems there are periods of time during which the CPU is not used for any other purpose than as a timer while waiting for some event or timed period to occur. That is, in such systems, the processor is used to time an event via software timing loops or by incrementing counters based on a timer tick. By transferring these timing tasks to the real-time clock 18 from the CPU 12, significant savings and power consumption are achieved. Thus, the real-time clock 18 shown in Figures 1 and 2, is easily adapted to many kinds of electronic devices to conserve power consumption, and is particularly useful in portable battery operated devices. In general, the system can be adapted by integrating the real-time clock 18 with the power management layer of the controlling software.

Figures 3, 4, and 5 illustrate some of the steps which may be performed by the CPU 12 in implementing the present invention. Each of these figures describe a different task which is driven by particular events. For example, there may be several paths in the software which are all waiting for something external to happen such as an interrupt coming in from the outside (via a radio event, for example, in a communications device) or from the internal alarm timer. A particular part of the operating system will then notify and run the tasks waiting on a particular event when the event occurs. If none of these are ready to run, the operating system executes another section of code, the CP idle task, which turns off the clock, and disables the

CPU 12.

For example, Figure 3 is a flow chart of an exemplary central processor idle task. The process illustrated in Figure 3 is particularly useful in cases where time critical real time events are pending. The CP clock (high speed clock) circuitry uses an appreciable amount of power while running. It is therefore advantageous to power down the clock when the processor is idle. However, when the CP clock is again turned on, a period of time is required to assure a stable signal. Since the CP cannot execute instructions while the clock is unstable, a latency is incurred with this process. Step 42 of Figure 3 is used to bypass the steps where the clock is powered down if the events that are pending require very short processor latency. Step 46 is similar to step 42 in that it compares the next alarm clock to the clock startuj latency. If the next alarm time occurs within the clock latency, the steps where the clock is powered down are bypassed.

Step 48 adjusts the alarm time to compensate for the latency of the clock startup prior to powering down the clock. Step 50 executes the necessary instructions to initiate the hardware sequence that powers down the clock.

All paths in the idle task eventually reach step 44 which disables the CP by removing its clocking signal.

In Figure 4, a software routine is described whereby the timer manager 31 adds timed events to an existing list of timed events. This routine is used when a software path needs to be stopped and restarted after a delay in order to carry out at a procedure at a certain time. Initially, a delay-time is introduced into the software routine (Step 52). The system then calculates the time at which the event is to occur by converting the received delay time into a real-time value. The system compares the newly received time to the other times it has on a linked event list and sorts them chronologically putting the events that are to happen first on top of the list (Step 56). Next, the system checks to see if the newly received time is at the top of the list (Step 58). If so, this event is entered into the alarm register 30 (Step 60), which is compared to the real-time clock counter register. If not, the event that was at the top of the list remains the next event, and the routine is exited (Step 62). Figure 5 illustrates a flow chart of the process performed by the timer manager software 31 when servicing timer interrupts. This process is referred to as the Interrupt Service Routine (ISR). An alarm clock interrupt occurs when, the comparison register 36 determines that the value in the real time counter register 34 is equal to the value in the alarm register 30. When this happens, an interrupt signal is sent from the real-time clock 18 along line 38 to the interrupt controller 16 (Step 64). As a result, the CPU 12 is turned on, if it was off (Step 66), by reenabling the high speed clock 14. Next, the re-enabled CP jumps to the timer interrupt vector. If the real-time value in counter register 34 is greater than or equal to the top of the list, then the interrupt controller 16 will wake up the task that set that alarm (Step 68) and delete that event from the top of the link list (Step 70). The process then loops back through path 72 and proceeds again to Step 68. If instead, the real-time value is less than the value at the top of the list, then the current item in the top of the link list is placed into the alarm register 30 in the real-time clock 18, and the Interrupt Service Routine is exited (STEP 74).

One reason why the steps in Figure 5 are necessary is that in some situations the alarm register 30 in the real-time clock 18 may only support a subset of the bits in the real time counter register 34. This subset of bits would represent a limited time period (e.g. 10 minutes), which is less than the total amount of time which is desired to be measured. The situation is handled by putting in the subset of bits for the alarm time, which is less than its total time needed and then repeatedly entering these bits for the same time period until the longer desired time period has been reached. In a sense, the alarm clock will go off several times, and the processor will wake up briefly to reset the alarm clock, turning off immediately thereafter. The task which originally set the alarm will not be started until the ultimate real-time is reached.

Most internal timed events occur within periods of time that are shorter than the typical maximum timing capabilities of the real-time clock. However, one situation in which the real-time clock will be exceeded occurs when it is desired to set an electronic device to turn on at a particular time several days in the future. The alarm time is loaded into the system by means of the read- write bus 20, from CPU 12, via the user interface (not shown). In accordance with the preferred embodiment of the present invention, this time period would be placed into the timer event list in chronological order. When this event is next to occur, it is then loaded into the real-time clock 18.

One example of this might be a calendar/reminder function in a portable electronic organizer.

It should be noted that there are at least three general categories of use for the present invention. The first category is where it is desired to have the real-time clock 18 turn off the CPU 12 for a period which is determined by events external to the system. In contrast to prior art systems which simply respond immediately to external events, in accordance with the present invention, there may be a timing function which turns the CPU 12 on or off at a given period of time after an external event. In the second category, the real-time clock 18 turns the CPU 12 on or off in response to specific times or intervals which are set by the user through the user interface (not shown). In the third category, the real-time clock 18 turns the CPU 12 on or off in response to events which are entirely internal to the system 10. As will be discussed in more detail below, such external interrupts in a communications system may comprise radio events. For example, in communications systems such as Cellular Digital Packet Data (CDPD), and personal Air Communications Technology (pACT) there may be hundreds of protocol timers running at any given time. These timers identify time periods during which particular events happen or do not happen. In conventional systems, such timers were implemented via software timing loops by incrementing counters based on a timer ticks. This process required the operation of the CPU, and the expenditure of significantly higher levels of power than the real-time clock 18 of the present invention.

In one example of these types of systems, a base station broadcasts a list of stations for which the base station has messages. The station must wake up and be ready to receive the message that is transmitted. Otherwise, the system will not know that there is a message for it. Of course, the station must be configured to wake up at a predetermined time and have enough lead time to be able to accomplish this event. This is a time dependent event that can utilize the real-time clock 18 of the present invention instead of the CPU 12.

Another example in communications is the situation where a transmitter attempts to send a message. If the m jssage collides with another message, an expected response will not be received. Thus, if no response is received within a predetermine amount of time, then the system can assume that the message did not get through and can attempt to resend the message. The timing of this event can be easily implemented using the real-time clock 18 of the present invention.

Another application would be a battery recharger where the CP measures the battery and adjusts the charging process at predetermined intervals while the energy is being put into the battery. In accordance with the present invention, the real-time alarm clock can time these intervals instead of using a less efficient processor based method to do so.

One specific example of an internal timer in a communications device which can be implemented using the real-time clock 18 of the present invention is found in the

U.S. patent application Serial Number 08/288,284 filed by K. Balachandran, and assigned to Pacific Communication Sciences, Inc. The present invention may be employed to implement the handoff timers described in this patent application, which is hereby incorporated by reference. In general, in addition to the above example, the present invention is usable in any system having a microprocessor which is used as a timer and not for other processing tasks during a specific period of time. A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the present invention may be used in any electronic device, but is particularly well suited to battery operated computing and communication devices where conserving battery life is important. Furthermore, the logical and physical organization of the components of present invention may differ from those that are disclosed, without departing from the scope of the present invention as will be clear to one of ordinary skill. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiment, but only by the scope of the appended claims.

Claims

1. A method of reducing power consumption in a system having a digital processor, the method comprising the steps of: determining a fixed period of time during which the operation of the processor is not expected to be required; turning off the processor at the beginning of the fixed period of time; determining when the period of time has elapsed; and turning the processor back on after the period of time has elapsed.

2. The method of claim 1 , wherein the step of determining when the period of time has elapsed includes the step of turning on an alarm clock at the beginning of the period of time.

3. The method of claim 1, wherein the system is powered by a battery, and the step of turning off the processor includes the step of disconnecting a clock which drives the processor.

4. The method of claim 1, wherein said step of determining a period time comprises the step of determining the absolute time during which the operation of the processor is again required.

5. The method of claim 1, wherein said step of determining a period of time comprises the step of determining the time duration during which the operation of the processor is not required.

6. The method of claim 1, wherein said step of determining a fixed period of time is based on internal events within said system.

7. The method of claim 1, wherein said step of determining a fixed period of time includes the step of determining a protocol time in a communications system.

8. The method of claim 7 wherein the protocol time is a period of time between retry actions in a message sending process of the communications system.

9. The method of claim 1 , wherein said step of determining a fixed period of time further includes the step of subtracting from said period of time, a start-up time which is the start-up time of an electrical component of the system.

10. The method of claim 1 , wherein the step of determining a period of time comprises the step of receiving a user input specifying the period of time.

1 1. The method of claim 1 , wherein the step of determining a period of time comprises the step of receiving a user input specifying an absolute time.

12. The method of claim 1 further comprises the step of turning the processor back on prior to the completion of the fixed interval in response to an asynchronous event.

13. An apparatus for reducing power consumption in a system having a digital processor, the apparatus comprising; means for determining a period of time during which the operation of the processor is not expected to be needed; means for disabling the processor at the beginning of the period of time; means for determining when the period of time has elapsed; and means for turning the processor back on after the period of time has elapsed.

14. The apparatus of claim 13, wherein the means for determining when the period of time has elapsed includes means for turning on an alarm clock at the beginning of the period of time.

15. The apparatus of claim 13, wherein the system is powered by a battery, and the means for disabling the processor includes means for disconnecting the clock which drives the processor.

16. The apparatus of claim 13, wherein the means for determining a period of time comprises a means for determining the absolute time at which the operation of the processor is again required.

17. The apparatus of claim 13, wherein the means for determining a period of time comprises the step of determining the time duration during which the operation of the processor is not required.

18. The apparatus of claim 13, wherein the means for determining a fixed period of time determines a fixed period of time based on internal events within said system.

19. The apparatus of claim 13, wherein the means for determining a fixed period of time includes a means for determining a protocol time in a communications system.

20. The apparatus of claim 19, wherein the protocol time is a period of time between retry actions in a message sending process of the communications system.

21. The apparatus of claim 13, wherein said means for determining a fixed period of time further includes means for subtracting from said period of time, a start-up time which is the start-up time of an electrical component of the system.

22. The apparatus of claim 13. wherein said means for determining a period of time comprises means for receiving a user input specifying the period of time.

23. The apparatus of claim 13, wherein the step of determining a period of time comprises the step of receiving a user input specifying an absolute time.

24. The apparatus of claim 13 further comprises means for turning the processor back on prior to the completion of the fixed interval in response to an asynchronous event.

25. The apparatus of claim 13 wherein the means in determining a period of time comprises an alarm register, the means for disabling comprises an interrupt register, and the means for determining when the period of time has elapsed comprises a comparison register.

26. In a battery powered system having a digital processor and software controlling internal events which occur at predetermined intervals within the system, a method for conserving battery power comprising the steps of; scheduling a plurality of events to occur at predetermined times, there being a known period of time between the events; turning off the digital processor after an earlier one of the events is complete; determining when one of the predetermined times has been reached; and turning the digital processor back on upon the occurrence of the predetermined time when a later event is scheduled.

27. The method of claim 26 further comprising the step of turning the processor back on prior to reading the predetermined time in response to an asynchronous event.