Classifications

• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
  • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
  • G06Q20/00—Payment architectures, schemes or protocols
  • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
  • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
  • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
  • G06Q20/00—Payment architectures, schemes or protocols
  • G06Q20/38—Payment protocols; Details thereof
  • G06Q20/40—Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check credit lines or negative lists
  • G06Q20/409—Device specific authentication in transaction processing
  • G06Q20/4097—Device specific authentication in transaction processing using mutual authentication between devices and transaction partners
  • G06Q20/40975—Device specific authentication in transaction processing using mutual authentication between devices and transaction partners using encryption therefor
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Definitions

• cryptographic algorithms are used to encrypt the actual communication data.
• Various algorithms are used, for example, to ensure the integrity, confidentiality or authenticity of the transmitted data or the communication partner.
• Special security modules designed for individual applications are known, for example a security module for secure fax transmissions (Siemens, data security module DSM-Fax, secure fax transmissions, Siemens area security technology) or also for encryption of telephone conversations (Siemens, DSM -Voice-Telephoning in Confidence, Sie ⁇ mens area security technology; Luis Cypher, LC-1 The digital voice encryptor for tap-proof telephone calls).
• a security module for secure fax transmissions Siemens, data security module DSM-Fax, secure fax transmissions, Siemens area security technology
• DSM-Voice-Telephoning in Confidence, Sie ⁇ mens area security technology Siemens area security technology
• Luis Cypher Luis Cypher
• LC-1 The digital voice encryptor for tap-proof telephone calls).
• the invention is therefore based on the problem of specifying a security chip which avoids the disadvantages mentioned above.
• the security chip is completely decoupled from the application hardware and can only be “addressed” via a data interface and a command interface. Because the security chip also has its own processor, an on-chip bus to which the application hardware cannot access, and different algorithm modules which the most diverse security services based on asymmetrical and symmetrical algorithms perform, is the security universally applicable and does not provide any security-relevant information to the application hardware.
• the application hardware and the application software could be loaded, configured and adapted as desired without endangering the security of the various crypto functions that are carried out with the algorithm modules.
• the development of the security chip according to claim 6 implements an extension of the algorithm modules by additional security services and thus extends the applicability of the security chip.
• Figure 1 is a sketch describing a possible arrangement of the security chip
• FIG. 2 shows a block diagram describing possible algorithm modules
• FIG. 3 shows an arrangement which represents the construction of a safe timer module. The invention is explained further with reference to FIGS. 1 to 3.
• FIG. 1 An arrangement of a security chip SC is shown in FIG.
• the security chip SC has at least the following components:
• a secure command interface BS which is either led into a chip-internal data bus DB or directly into the processor P,
• the chip-internal data bus DB via which the plurality VZ of independent algorithm modules AMi is coupled to the data interface DS, and
• the encryption performance is no longer dependent on the processor P.
• the chip internal data from the chip internal bus IB cannot be intercepted by an unauthorized third party, in particular at the data interface DS or manipulated.
• the security chip SC can have the following components:
• a wide variety of communication protocols can be used for communication between the individual components, that is to say for sequence control, of course independently of the communication protocol used by an application hardware AHW.
• the data interface DS and the command interface BS are the only access points for the application hardware AHW on the security chip SC.
• the application hardware AHW has no possibility of accessing the security chip SC and thus also the security-relevant data that are used and / or stored in the security chip SC.
• the processor P can be any processor with a suitable speed which results directly from the requirements of the planned application.
• the algorithm modules AMi are independent modules, each of which is “responsible” for a cryptographic protocol or method. These include, for example, methods or protocols for the encryption and decryption of user data, for integrity protection, or for digital signature (signature) or hash value formation.
• the index i uniquely identifies each algorithm module AMi. It is any natural number in the range from 1 to n. Here n is the number of different Algorithm modules AMi implemented on the security chip SC.
• An algorithm module AMi is, for example, a module that is specifically designed to carry out a cryptographic symmetrical method SV, for example the data description standard method (DES method).
• the module can also be designed such that it can carry out the DES process with different key lengths, for example also the triple DES process.
• DES method data description standard method
• asymmetrical cryptographic algorithms AV are also carried out in the algorithm modules AMi.
• Examples of asymmetric cryptographic algorithms AV are well known to any person skilled in the art, for example the RSA method.
• algorithm modules AMi of the same type can also be provided on the security chip SC to carry out the same method, for example to increase the performance of the security chip SC.
• This can e.g., it can also be provided in a way that an algorithm module AMi for processing an incoming data stream and another algorithm module AMi of the same design for processing an outgoing data stream is provided.
• the algorithm modules AMi are used, among other things, for the encryption of user data, which are placed in plain text by the application hardware AHW on a chip-internal data bus DB via the data interface DS and with any encryption method defined by the application hardware AHW via the command interface BS that the algorithm module AMi used is selected from the plurality VZ of the independent algorithm modules AMi are encrypted.
• the user data encrypted in the respective algorithm module AMi are again transmitted to the application hardware AHW via the chip-internal data bus DB and the data interface DS, now in encrypted form.
• the parameters of the respective encryption request for the user data are made known to the security chip SC by the application hardware AHW via the command interface BS.
• This can be, for example, the encryption algorithm to be used, the key length, or similar parameters that are necessary for the encryption of user data.
• the method ie for example encryption of user data, is started by the application hardware AHW via the command interface BS.
• the processor P controls the administrative processes for encrypting data in the security chip SC and also cryptographic protocols described below.
• the processor P does not necessarily transport the encrypted, decrypted or processed with cryptographic methods user data. If not transported by the processor P, these are usually transported via the on-chip data bus DB and, which leads to a further advantage of the security chip SC, that the encryption performance SC is not dependent on the processor P.
• the decoupling of the chip-internal data bus DS from the chip-internal bus IB ensures that the internal data which are transported via the chip-internal bus IB are not listened to or manipulated at the data interface DS.
• Both unencrypted data and data that have to be buffered in order to carry out cryptographic algorithms are stored in the memory SP, for example intermediate keys in methods that work on the principle of exponential key exchange or intermediate keys that are used in the DES method be used, .
• Additional algorithm modules AMi can be provided to carry out different security services, for example from known authentication protocols, or also to carry out methods for key exchange or for key generation of cryptographic keys.
• the sensor module SM detects physical attacks on the security chip SC, possibly evaluates them and reports them to the processor P via the chip-internal bus IB.
• the ZM timer module has at least the following components:
• a timer interface SIO a timer controller ZC
• the counting circuit ZS having at least:
• the ZM timer module carries out autonomous tasks, for example to provide time stamps.
• the time stamps are made available to other applications of the SC security chip via the ZIO timer interface.
• the timer controller ZC controls the processes of the timer module ZM.
• the timer interface ZIO represents the bus interface of the timer module ZM to the on-chip bus IB.
• the timer interface ZIO is primarily required to handle communication with external controllers, in the case of the security chip SC with the processor P.
• Connections are therefore provided to control the sequence of the cryptographic communication protocol, that is to say to control communication with other controllers, that is to say with the processor P. Furthermore, a connection is provided via which the timer module ZM attempts to tamper with the sensor module SM, be reported, e.g. B. manipulations on the clock. Additional connections are provided for exchanging the data of the timer module ZM, that is to say an absolute or relative time which is determined by the timer module ZM. No crypto-algorithms are carried out in the timer module ZM itself.
• the other modules of the security chip SC are responsible for handling authentication protocols and other security functions.
• the processor P must decide and monitor who is allowed to access the timer module ZM in what way via the timer interface ZIO.
• the timer controller ZC controls the timer interface ZIO and the counter circuit ZS. In addition, the timer controller ZC receives logic commands from the processor P via the timer interface ZIO.
• the logic commands of the processor P are interpreted by the timer controller ZC and implemented in the internal control of the timer module ZM.
• the timer controller ZC thus monitors the functional sequence of the entire module. It thus represents the control unit of the timer module.
• Commands with which the timer controller ZC influences the sequence of the timer module ZM can include the following functions, for example:
• a data access control and a function access control are carried out by the timer controller ZC.
• this includes, for example:
• - Access to the timer module ZM is only permitted after a secret number has been successfully checked; - Access is only allowed after successful authentication;
• the counter circuit ZS of the timer module ZM has, as described in the previous, among other things the real time counter RZ.
• the real-time counter RZ is a counting circuit that is made up of cascaded modulo counters.
• the cascading and synchronization of the real-time counter RZ can take into account the peculiarities of time jumps, for example caused by summer time or leap years, etc.
• a counting of the “relative” time ie a monotone counting binary counter of sufficient length corresponding to the required time, is also provided.
• the clock adaptation TA is used to generate a suitable time base for the time measurement in the timer module ZM with an external clock supply, as is the case, for example, with chip cards customary today.
• the data buffer DB is used to store data that is required in the timer module ZM.
• the algorithm modules AMi are designed in such a way that the key management is supported directly in hardware. This offers considerable performance advantages, especially in the case of rapid key changes between differently encrypted data streams. This is of particular importance in the area of packet-oriented telecommunications or data connections or in application sharing systems or multimedia applications, for example in a local area network (LAN) in which many packets are transmitted to different communication partners and processed differently by cryptography Need to become.
• LAN local area network

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• Engineering & Computer Science (AREA)
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• Physics & Mathematics (AREA)
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• General Physics & Mathematics (AREA)
• Strategic Management (AREA)
• Computer Security & Cryptography (AREA)
• General Business, Economics & Management (AREA)
• Theoretical Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Finance (AREA)
• Signal Processing (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Storage Device Security (AREA)

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• 1995
  • 1995-10-25 DE DE19539700A patent/DE19539700C1/de not_active Expired - Fee Related
• 1996
  • 1996-09-25 EP EP96932453A patent/EP0857382A1/de not_active Ceased
  • 1996-09-25 RU RU98109590/09A patent/RU2180987C2/ru not_active IP Right Cessation
  • 1996-09-25 UA UA98042063A patent/UA46064C2/uk unknown
  • 1996-09-25 WO PCT/DE1996/001813 patent/WO1997016003A1/de not_active Application Discontinuation
  • 1996-09-25 JP JP9516179A patent/JPH11513864A/ja active Pending

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