EP0853818A1 - Transistor mos a double diffusion en tranchees a canal court basse tension - Google Patents

Transistor mos a double diffusion en tranchees a canal court basse tension

Info

Publication number
EP0853818A1
EP0853818A1 EP96927387A EP96927387A EP0853818A1 EP 0853818 A1 EP0853818 A1 EP 0853818A1 EP 96927387 A EP96927387 A EP 96927387A EP 96927387 A EP96927387 A EP 96927387A EP 0853818 A1 EP0853818 A1 EP 0853818A1
Authority
EP
European Patent Office
Prior art keywords
region
trench
drift
semiconductor device
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96927387A
Other languages
German (de)
English (en)
Other versions
EP0853818A4 (fr
Inventor
Dorman C. Pitzer
Fwu-Iuan Hshieh
Mike F. Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of EP0853818A1 publication Critical patent/EP0853818A1/fr
Publication of EP0853818A4 publication Critical patent/EP0853818A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • This invention pertains to semiconductor devices and more specifically to a trenched DMOS transistor suitable for use as a power transistor and having punch-through elimination, improved safe operating area and threshold control.
  • DMOS transistors are well known and are especially suitable for use as power transistors. Such transistors are typically fabricated by well known semiconductor fabrication techniques. A typical power transistor includes hundreds or thousands of cells formed in a single semiconductor substrate and connected together electrically. Prior art DMOS transistors have several well known deficiencies, including having punch-through i.e. current conduction from the source region to drain region, when such is not desired. Also there is the deficiency of control of the threshold voltage. Additionally, such devices often suffer from excessive resistance of the pinched body region, which tends to cause latchback (i.e. snap back) .
  • a vertical DMOS field effect transistor includes (for an N-channel device) a N+ drain region overlain by a P- drift region which in turn is overlain by a P body region which is overlain by a N+ source region.
  • a trench penetrates through the source region, body region and drift region into the drain region and is filled with a conductive polycrystalline silicon gate electrode. The trench penetrating down into the drain region is useful in accordance with the present invention due to the need to invert the entire trench sidewall surface.
  • a source-body contact overlies the principal surface of the silicon and is in electrical contact with the source region and is also in electrical contact with the body region via a P+ body contact formed in an upper portion of the P body region.
  • this structure provides a power transistor device with a simplified punch-through elimination structure, improved safe operating area, and threshold control.
  • the device has a short channel and a low threshold voltage for e.g. low voltage battery applications.
  • the depletion region spreads from the N+ drain region into the P- drift region.
  • the thickness of this P- drift region in conjunction with the thickness and concentration of the P body region determines the drain-source breakdown voltage. Diffusing the P body region into the P- drift region allows control of both the surface concentration in the channel region and the channel length, resulting in improved threshold control.
  • the effective body junction depth is the combination of the body and drift regions, resulting in lower Rb' .
  • the gate voltage When the device is forward biased, the gate voltage easily inverts the surface of the drift region. Since critical electric field has been achieved in the body (channel) region, carriers are injected into the drift region with maximum velocity which results in low resistance for this region.
  • a complementary P-channel device which is otherwise similar structurally has also been found to be advantageous.
  • a P+ doped "body plus" region is provided which extends from the principal surface of the semiconductor material adjacent the source region into the drift region.
  • Fig. 1 shows a cross-section of a semiconductor device in accordance with the present invention.
  • Fig. 2 shows a cross-section of a second embodiment of a semiconductor device in accordance with the present invention.
  • Figs. 3A-3C show process steps for forming a semiconductor device in accordance with the present invention.
  • Fig. 1 shows a trenched DMOS transistor in accordance with the present invention. It i ⁇ to be understood that this shows one cell of what is typically many cells (as described above) of a transistor. Also conventionally this cross sectional depiction shows various semiconductor regions delineated by lines. It is to be understood that in an actual device there are concentration gradients between these regions. Moreover, Fig. 1, as is true of the other figures in this disclosure, is not to scale and shows only an active portion of the transistor. The surrounding termination region is discussed below. Moreover, the description of various materials, dimensions, doping levels, etc. herein is intended to be illustrative and not limiting; other materials, dimension, and doping levels may also be used in accordance with the present invention as is well known in the field.
  • the transistor of Fig. 1 in its lower portion includes an N+ doped drain region 20 having typically a dopant concentration of 2 x l ⁇ 19 /cm 3 .
  • Fig. 1 depicts an N-channel device and the complementary P-channel device may also be fabricated with all the conductivity types being opposite to that shown in Fig. 1. Such a complementary P-channel device would have comparable performance to that of the depicted N-channel device.
  • a P- drift region 22 Overlying the N+ drain region 20 is a P- drift region 22, the thickness of which partially determines the drain/source breakdown voltage of the device. For instance, for a 30 volt device the P- drift region 22 has e.g.
  • P- drift region 22 is typically an epitaxial layer grown on an N+ doped substrate 20.
  • the drift region 22 is lightly doped, typically having a resistivity of 20 ohm cm and a doping concentration of 7xl0 I4 /cm 3 .
  • a diffused P body (channel) region 26 typically 0.6 to 1.1 ⁇ m thick and having a typical compensated surface doping concentration in the range of l to 3 x l ⁇ 16 /cm 3 .
  • the thickness and doping level of this body region 26 is important because its properties determine the length of the channel.
  • the N+ source region 30 having a typical thickness of 0.2 to 0.5 micrometer and a surface doping concentration of 5xl0 19 /cm 3 .
  • a P+ body contact region 34 Formed also in the upper portion of the epitaxial layer and adjacent the source region 30 is a P+ body contact region 34 allowing ohmic contact to be made to the body region 26.
  • the P+ body contact region 34 has a thickness similar to that of the source region 30 and a typical surface doping concentration of 5xl ⁇ I8 /cm 3 .
  • a trench 38 typically 2 to 3 ⁇ m deep and 1 ⁇ m wide, penetrates into the drain region 20.
  • Trench 38 is conventionally lined with a gate oxide layer 42 and filled with a doped polysilicon gate electrode 46.
  • a layer 48 of boro-phosphosilicate glass (BPSG) overlies and insulates the upper portion of the conductive gate electrode 46.
  • a conventional aluminum silicon metallization layer 52 overlies the BPSG layer and electrically contacts both the source region 30 and the body contact region 34.
  • a passivation layer (not shown) overlying the metallization layer and a drain metallization layer 56 formed on the lower portion of the substrate to electrically contact the drain region 20.
  • the structure shown in Fig. 1 therefore includes, arranged vertically, semiconductor regions including a source region 30, a body region 26, a drift region 22 and a drain region 20.
  • semiconductor regions including a source region 30, a body region 26, a drift region 22 and a drain region 20.
  • a lateral DMOS with similar semiconductor regions but of course arranged laterally rather than vertically.
  • the vertical device of Figure 1 saves considerable chip "real estate" (surface area) over a comparable lateral device.
  • the present device allows spreading of the breakdown between the drain and the drift region and not across the channel.
  • a shorter channel is formed than in other types of semiconductor devices.
  • the channel is in the body region 26 between the source region 30 and the drift region 22.
  • This device therefore allows use of a short channel without the problem of punch-through.
  • trenched DMOS devices when one grows gate oxide over an N- doped drift region, surface accumulation occurs, i.e. the N- region becomes more N-type and this undesirably compensates the P-body region and shortens the channel even more, leading to punch through.
  • the present device avoids this by providing an enhancement in the opposite direction because the P- drift region 22 depletes at the conduction surface next to the gate oxide, so that the channel experiences less effect from the redistribution of charge at the conduction surface.
  • the present device also avoids the problem of latchback (snap back) which is typically caused by the resistance Rb' of the body region 26.
  • latchback typically caused by the resistance Rb' of the body region 26.
  • Rb' the leakage current through Rb' causes a voltage gradient along the source/P body junction.
  • the NPN parasitic transistor latches.
  • the parasitic transistor is the NPN (bipolar) transistor formed by source 30, body and drift regions 26 and 22, and drain region 20. Since the present device has a vertically wider effective body (regions 22, 26) , Rb' advantageously is decreased.
  • the depletion region spreads from the drain region 20 into the drift region 22.
  • the thickness of the drift region 22 determines the drain to source breakdown voltage. Formation by diffusion of the body region 26 into the drift region 22 improves control of both the surface concentration and the body region concentration and the resulting channel length, and improves the threshold control.
  • the effective body junction depth is that of the combined drift 22 and body regions 26, resulting in lower Rb' .
  • the gate voltage When the device of Fig. 1 is forward biased, the gate voltage easily inverts the conduction surface next to the gate oxide of the drift region 22. Since critical electric field has been achieved in the channel (body) region 26, carriers are injected into the drift region 22 with maximum velocity, resulting in lower resistance for the drift region.
  • a top side geometry (not shown) suitable for the device of Fig. 1 is any of the well known types of cells, i.e. circular, rectangular, hexagonal, linear, etc.
  • a second embodiment in accordance with the present invention is shown in Fig. 2, the structure of which is generally identical to those of Fig. 1 (although two trenches are shown rather than one for greater understanding) .
  • trench 38B, gate electrode 46, and BPSG layer 48A in Fig. 2 correspond to structures 38, 46, 48 in Fig. 1 and trench 38B, gate electrode 46B, and BPSG layer 48B are the second trench and associated structures.
  • FIG. 2 shows the additional P+ "body plus" region 62A, 62B formed between two portions of the source region 30 and extending at portion 62A not only into the upper portion of the body region 26 to serve as a body contact, but also extending down at portion 62B into the drift region 22.
  • the doping level of body plus region 62A, 62B is the same or even heavier than that of the body contact region 34 in Fig. 1.
  • Fabrication of the embodiment of Fig. 2 is compatible with processes already used in the semiconductor industry and provides better control (prevents latchback) of the NPN parasitic transistor present.
  • the embodiment of Fig. 2 has a potential detriment in that the breakdown voltage may be compromised by the distance from the body plus region 62B to the drain region 20 i.e., these two regions approach relatively close together, hence providing a potential breakdown path.
  • a termination structure which in this case is a polysilicon field plate 66 in the righthand portion of the drawing.
  • the field plate 66 is located on the principal surface of the semiconductor substrate and is in contact with the P+ region 34 to the right of trench 38A.
  • P+ region 34 is a channel stop to prevent conduction.
  • a metallization layer 52B overlies field plate 60, but is isolated from metallization layer 52.
  • This termination structure is also suitable for use with the transistor of Fig. 1.
  • Another termination structure (not shown) suitable for use with the transistors of Fig. 1 and Fig.
  • FIG. 2 is a trench which penetrates (like the trenches in the active region) through the epitaxial layer down into the drain region but having a dummy cell (one not having any N+ source region) in the (exterior) termination portion of the transistor.
  • This second termination structure would typically include a conductive polysilicon gate runner (not shown) which connects to the polysilicon in the termination trench and to the active gate electrodes.
  • One advantage therefore in accordance with the present invention is the ability to use such relatively simple termination structures.
  • a process flow to fabricate a transistor as in Fig. 1 (or Fig. 2) is described hereinafter with reference to Fig. 3A and following. It is to be understood that this process flow is illustrative and not limiting and other process flows may also be used to fabricate a transistor in accordance with the present invention.
  • a conventional silicon substrate 20 is provided in Fig. 3A which is N+ doped to a concentration of 2xl0 19 /cm 3 .
  • An epitaxial layer 22 approximately 4 ⁇ m thick is grown on the upper portion of the substrate. This epitaxial layer is lightly P- doped and has a resistivity of 20 ohm.cm.
  • An oxide layer (not shown) is grown 6,000 A thick over the principal surface of the epitaxial layer.
  • the first mask layer (not shown) is formed over the surface of this oxide layer.
  • the mask is patterned and the oxide layer then etched. This mask thereby defines the active portions of the transistor.
  • another mask layer 70 is formed on the principal surface and patterned to define the locations of the gate trenches.
  • the gate trench is 38 anisotropically etched to a depth of 2 to 3 ⁇ m and a width of 1 ⁇ m in Fig. 3B and mask layer 70 is stripped.
  • Gate oxide layer 42 is grown to a thickness of 100 to 70 ⁇ A over the sidewalls and floors of the trench and also over the principal surface of the substrate.
  • Polycrystalline silicon 72 (polysilicon) is deposited in the trench 38 and over the silicon principal surface to a thickness of 15,OO ⁇ A and on the drain 20 surface of the silicon.
  • the polysilicon is then removed from the backside (drain) surface of the substrate, and any oxide on the backside surface is also removed.
  • the polysilicon is then etched back (planarized) to a final thickness of 5,50 ⁇ A.
  • the polysilicon is N-doped using for instance phosphorous.
  • a photoresist mask layer (not shown) is formed thereover and patterned to define the gate electrodes and gate runners.
  • the polysilicon after the mask is patterned, is etched down so that the polysilicon gate electrode 46 does do not protrude above the level of the substrate at the trench 38 (the polysilicon 46 is planarized with the silicon principal surface) .
  • the photoresist is then stripped.
  • the P body region 26 is diffused (driven in) so as to form a 50 ⁇ A thick oxide layer (not shown) during the drive-in proces ⁇ .
  • the doping concentration of the P body region 26 is intended to be in one embodiment 1 to 3 x 10 16 /cm 3 doping level at its surface next to the gate oxide.
  • An unmasked (blanket) etch is performed to etch back this 500 A oxide layer to a thickness of 250 to 300 A. 14.
  • Next is the formation and patterning of the N+ source region mask (not shown) .
  • the source region 30 is implanted using this source region mask using a dose of 8 x 10 15 /cm 2 at 80 KeV of arsenic. 16.
  • the source region 30 is diffused (driven in) so as to grow a l,60 ⁇ A thick oxide layer.
  • the BPSG layer is deposited; the BPSG is doped lightly with phosphorous and boron. (This step and the remaining steps are not depicted, being conventional) .
  • the BPSG layer is flowed.
  • the BPSG is reflowed (smoothed out) . This reflow step also activates the P+ body contact region implant.
  • An unmasked oxide etch is performed to clear out the contact holes in the BPSG layer, to remove the oxide and any material present due to the reflow process.
  • An aluminum silicon metal layer is deposited to a thickness of e.g. 2.8 ⁇ m over the entire structure .
  • a metal mask layer is formed and patterned and the metal layer is etched accordingly to define the metallization.
  • a passivation layer of PSG is formed over the entire structure.
  • a pad mask layer is formed and patterned and the PSG passivation layer patterned thereby to expose the contact pads.
  • the aluminum/silicon is alloyed.
  • Last is the backside metallization deposit to form the drain electrode. While particular structures and processes are disclo ⁇ ed herein, these are not intended to be limiting. Furthermore, a transistor in accordance with the present invention may be used for applications other than the above-described low voltage application; as is well known, the voltage which the device will withstand is typically limited by the trench and semiconductor region configurations. Particular advantages in accordance with the present invention are that one can achieve a lower threshold voltage and short channel without punch through; improved threshold control due to the P drift region; and the ability to use a relatively simple termination ⁇ tructure, rather than the more complex termination ⁇ tructure ⁇ often used with field effect tran ⁇ istors for power applications. This disclosure is illustrative and not limiting; further modifications will be apparent to one skilled in the art in light of this disclosure and are intended to fall within the scope of the appended claims.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Transistor MOS à double diffusion en tranchées à canal court basse tension présentant une élimination de claquage simplifiée, une plage de fonctionnement sûr améliorée et une commande de seuil améliorée. Ce transistor comprend (pour un dispositif à canal de type N-), du haut vers le bas, une région de source N+ (30), une région de corps P- (26), une région de migration P- (22) et une région de drain N+ (20). La tranchée (38) pénètre dans la région de drain (20), l'électrode-porte étant localisée dans la tranchée (38). Lorsque le transistor est sous polarisation inverse, la région de déplétion s'étale de la région de drain jusque dans la région de migration P- (22). L'épaisseur de la zone de migration détermine la tension de claquage drain-source. La diffusion de la région de corps jusque dans la région de migration (22) permet de maîtriser aussi bien la concentration superficielle de la région de canal que la longueur du canal, ce qui entraîne une amélioration de la commande de seuil. Ce dispositif présente ainsi un canal court et une faible tension de seuil. Le dispositif complémentaire à canal P- présente des avantages similaires.
EP96927387A 1995-08-21 1996-08-15 Transistor mos a double diffusion en tranchees a canal court basse tension Withdrawn EP0853818A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53715695A 1995-08-21 1995-08-21
US537156 1995-08-21
PCT/US1996/013039 WO1997007548A1 (fr) 1995-08-21 1996-08-15 Transistor mos a double diffusion en tranchees a canal court basse tension

Publications (2)

Publication Number Publication Date
EP0853818A1 true EP0853818A1 (fr) 1998-07-22
EP0853818A4 EP0853818A4 (fr) 1998-11-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP96927387A Withdrawn EP0853818A4 (fr) 1995-08-21 1996-08-15 Transistor mos a double diffusion en tranchees a canal court basse tension

Country Status (3)

Country Link
EP (1) EP0853818A4 (fr)
AU (1) AU6722396A (fr)
WO (1) WO1997007548A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
DE19935442C1 (de) * 1999-07-28 2000-12-21 Siemens Ag Verfahren zum Herstellen eines Trench-MOS-Leistungstransistors
DE10009345C1 (de) * 2000-02-28 2001-07-19 Infineon Technologies Ag Feldeffekt-Transistoranordnung mit hoher Latch-up-Festigkeit und Verfahren zu deren Herstellung
US6312993B1 (en) * 2000-02-29 2001-11-06 General Semiconductor, Inc. High speed trench DMOS
US6921939B2 (en) * 2000-07-20 2005-07-26 Fairchild Semiconductor Corporation Power MOSFET and method for forming same using a self-aligned body implant
JP4813762B2 (ja) * 2003-12-25 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8698232B2 (en) 2010-01-04 2014-04-15 International Rectifier Corporation Semiconductor device including a voltage controlled termination structure and method for fabricating same

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JPS5674960A (en) * 1979-11-22 1981-06-20 Toshiba Corp Semiconductor integrated circuit
US4369564A (en) * 1979-10-29 1983-01-25 American Microsystems, Inc. VMOS Memory cell and method for making same
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US4814839A (en) * 1977-01-11 1989-03-21 Zaidan Hojin Handotai Kenkyu Shinkokai Insulated gate static induction transistor and integrated circuit including same
US5021845A (en) * 1985-08-30 1991-06-04 Texas Instruments Incorporated Semiconductor device and process fabrication thereof
US5298780A (en) * 1992-02-17 1994-03-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating same
US5385853A (en) * 1992-12-02 1995-01-31 International Business Machines Corporation Method of fabricating a metal oxide semiconductor heterojunction field effect transistor (MOSHFET)
EP0717450A2 (fr) * 1994-12-13 1996-06-19 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur vertical à grille isolée et méthode de fabrication

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NL184551C (nl) * 1978-07-24 1989-08-16 Philips Nv Veldeffekttransistor met geisoleerde stuurelektrode.
US5910669A (en) * 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US5341011A (en) * 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor

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US4814839A (en) * 1977-01-11 1989-03-21 Zaidan Hojin Handotai Kenkyu Shinkokai Insulated gate static induction transistor and integrated circuit including same
US4369564A (en) * 1979-10-29 1983-01-25 American Microsystems, Inc. VMOS Memory cell and method for making same
JPS5674960A (en) * 1979-11-22 1981-06-20 Toshiba Corp Semiconductor integrated circuit
US5021845A (en) * 1985-08-30 1991-06-04 Texas Instruments Incorporated Semiconductor device and process fabrication thereof
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US5298780A (en) * 1992-02-17 1994-03-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating same
US5385853A (en) * 1992-12-02 1995-01-31 International Business Machines Corporation Method of fabricating a metal oxide semiconductor heterojunction field effect transistor (MOSHFET)
EP0717450A2 (fr) * 1994-12-13 1996-06-19 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur vertical à grille isolée et méthode de fabrication

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Title
PATENT ABSTRACTS OF JAPAN vol. 005, no. 141 (E-073), 5 September 1981 & JP 56 074960 A (TOSHIBA CORP), 20 June 1981, *
See also references of WO9707548A1 *

Also Published As

Publication number Publication date
WO1997007548A1 (fr) 1997-02-27
EP0853818A4 (fr) 1998-11-11
AU6722396A (en) 1997-03-12

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EP0853818A1 (fr) Transistor mos a double diffusion en tranchees a canal court basse tension

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