EP0851474A3 - Improvements in or relating to integrated circuits - Google Patents

Improvements in or relating to integrated circuits Download PDF

Info

Publication number
EP0851474A3
EP0851474A3 EP97310064A EP97310064A EP0851474A3 EP 0851474 A3 EP0851474 A3 EP 0851474A3 EP 97310064 A EP97310064 A EP 97310064A EP 97310064 A EP97310064 A EP 97310064A EP 0851474 A3 EP0851474 A3 EP 0851474A3
Authority
EP
European Patent Office
Prior art keywords
relating
integrated circuits
flourine
ashing
contamination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP97310064A
Other languages
German (de)
French (fr)
Other versions
EP0851474A2 (en
Inventor
Robert M. Wallace
S. Charles Baber
Peijun Chen
Steven A. Henck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP0851474A2 publication Critical patent/EP0851474A2/en
Publication of EP0851474A3 publication Critical patent/EP0851474A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

An integrated circuit fabrication process in which residual flourine contamination on metal surfaces after ashing is removed by exposure to an NH3/O2 plasma.
EP97310064A 1996-12-12 1997-12-12 Improvements in or relating to integrated circuits Ceased EP0851474A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3527096P 1996-12-12 1996-12-12
US35270P 1996-12-12

Publications (2)

Publication Number Publication Date
EP0851474A2 EP0851474A2 (en) 1998-07-01
EP0851474A3 true EP0851474A3 (en) 1998-12-23

Family

ID=21881639

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97310064A Ceased EP0851474A3 (en) 1996-12-12 1997-12-12 Improvements in or relating to integrated circuits

Country Status (5)

Country Link
US (1) US6140243A (en)
EP (1) EP0851474A3 (en)
JP (1) JPH10189554A (en)
KR (1) KR19980064028A (en)
TW (1) TW373229B (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
US6313042B1 (en) * 1999-09-03 2001-11-06 Applied Materials, Inc. Cleaning contact with successive fluorine and hydrogen plasmas
US6668445B1 (en) * 2000-01-11 2003-12-30 Lexmark International, Inc. Method of increasing tab bond strength using reactive ion etching
JP3425927B2 (en) * 2000-05-16 2003-07-14 九州日本電気株式会社 Method for manufacturing semiconductor device
US6777344B2 (en) 2001-02-12 2004-08-17 Lam Research Corporation Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications
US6893969B2 (en) * 2001-02-12 2005-05-17 Lam Research Corporation Use of ammonia for etching organic low-k dielectrics
US6620733B2 (en) 2001-02-12 2003-09-16 Lam Research Corporation Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics
EP1320128B1 (en) * 2001-12-17 2006-05-03 AMI Semiconductor Belgium BVBA Method for making interconnect structures
US6953654B2 (en) 2002-03-14 2005-10-11 Tokyo Electron Limited Process and apparatus for removing a contaminant from a substrate
US6869812B1 (en) * 2003-05-13 2005-03-22 Heng Liu High power AllnGaN based multi-chip light emitting diode
US20060255349A1 (en) * 2004-05-11 2006-11-16 Heng Liu High power AllnGaN based multi-chip light emitting diode
EP1614709A1 (en) * 2004-06-21 2006-01-11 Air Products And Chemicals, Inc. Process for reducing the permeability of plastics materials
US7282441B2 (en) * 2004-11-10 2007-10-16 International Business Machines Corporation De-fluorination after via etch to preserve passivation
JP2006165189A (en) * 2004-12-06 2006-06-22 Nec Electronics Corp Method of manufacturing semiconductor device
EP1746124B1 (en) * 2005-07-22 2010-04-14 Air Products And Chemicals, Inc. Treatment of fluorinated plastics material
US8231736B2 (en) * 2007-08-27 2012-07-31 Applied Materials, Inc. Wet clean process for recovery of anodized chamber parts
FR2941560A1 (en) * 2009-01-28 2010-07-30 Commissariat Energie Atomique Preventing formation of metal oxyfluorides residues on a metal e.g. titanium layer before exposing it to a plasma containing fluorine, comprises performing reductive treatment with plasma containing compounds e.g. hydrocarbons
US8877299B2 (en) * 2009-03-31 2014-11-04 Tel Epion Inc. Method for enhancing a substrate using gas cluster ion beam processing
JP2010056574A (en) * 2009-12-07 2010-03-11 Nec Electronics Corp Method of manufacturing semiconductor device
JP6521799B2 (en) 2015-08-31 2019-05-29 東京エレクトロン株式会社 Method of removing halogen and method of manufacturing semiconductor device
US10410883B2 (en) * 2016-06-01 2019-09-10 Corning Incorporated Articles and methods of forming vias in substrates
US10794679B2 (en) 2016-06-29 2020-10-06 Corning Incorporated Method and system for measuring geometric parameters of through holes
US10580725B2 (en) 2017-05-25 2020-03-03 Corning Incorporated Articles having vias with geometry attributes and methods for fabricating the same
US11078112B2 (en) 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US11554984B2 (en) 2018-02-22 2023-01-17 Corning Incorporated Alkali-free borosilicate glasses with low post-HF etch roughness
US11404245B2 (en) * 2018-02-28 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. DC bias in plasma process
CN114496751A (en) * 2020-10-26 2022-05-13 中芯国际集成电路制造(北京)有限公司 Method for forming semiconductor structure
EP4411790A1 (en) * 2023-02-06 2024-08-07 Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO Anisotropic aluminium etching

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430152A (en) * 1981-10-23 1984-02-07 Fujitsu Limited Process for fabricating a semiconductor device
WO1993017453A2 (en) * 1992-02-26 1993-09-02 Materials Research Corporation Ammonia plasma treatment of silicide contact surfaces in semiconductor devices
EP0596364A2 (en) * 1992-10-27 1994-05-11 Nec Corporation Method of producing semiconductor device having buried contact structure
WO1995021458A1 (en) * 1994-02-03 1995-08-10 Applied Materials, Inc. Stripping, passivation and corrosion inhibition of semiconductor substrates
EP0680078A2 (en) * 1994-03-28 1995-11-02 Mitsubishi Gas Chemical Company, Inc. Semiconductor substrate surface treatment
US5700740A (en) * 1996-03-25 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Prevention of corrosion of aluminum interconnects by removing corrosion-inducing species

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430152A (en) * 1981-10-23 1984-02-07 Fujitsu Limited Process for fabricating a semiconductor device
WO1993017453A2 (en) * 1992-02-26 1993-09-02 Materials Research Corporation Ammonia plasma treatment of silicide contact surfaces in semiconductor devices
EP0596364A2 (en) * 1992-10-27 1994-05-11 Nec Corporation Method of producing semiconductor device having buried contact structure
WO1995021458A1 (en) * 1994-02-03 1995-08-10 Applied Materials, Inc. Stripping, passivation and corrosion inhibition of semiconductor substrates
EP0680078A2 (en) * 1994-03-28 1995-11-02 Mitsubishi Gas Chemical Company, Inc. Semiconductor substrate surface treatment
US5700740A (en) * 1996-03-25 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Prevention of corrosion of aluminum interconnects by removing corrosion-inducing species

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PEARTON S J ET AL: "LOW BIAS DRY ETCHING OF TUNGSTEN AND DIELECTRIC LAYERS ON GAAS", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol. 8, no. 10, 1 October 1993 (1993-10-01), pages 1897 - 1903, XP000417423 *

Also Published As

Publication number Publication date
TW373229B (en) 1999-11-01
EP0851474A2 (en) 1998-07-01
JPH10189554A (en) 1998-07-21
KR19980064028A (en) 1998-10-07
US6140243A (en) 2000-10-31

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