EP0845588A2

EP0845588A2 - Data processing device

Info

Publication number: EP0845588A2
Application number: EP97120733A
Authority: EP
Inventors: Kenzo Yano; Shinji Takeuchi; Kengo Sugiura; Takuya Harada; Tetsuyasu Kitamura
Original assignee: Denso Corp
Current assignee: Denso Corp
Priority date: 1996-11-27
Filing date: 1997-11-26
Publication date: 1998-06-03
Anticipated expiration: 2017-11-26
Also published as: DE69728237T2; ES2218630T3; DE69728237D1; EP0845588A3; EP0845588B1; JPH10213002A

Abstract

To use correction data having different lengths and to obtain flexibility in the use of data items, basic control data are stored in a ROM 6, and correction data related to the basic control data are stored in an OTPROM 7. The correction data have different data lengths based on the items to which they relate. The OTPROM 7 has discrimination codes for discriminating items and data lengths of the correction data and respective corresponding correction data in pairs. The correction data is transmitted from the OTPROM 7 to a back-up memory 8. A CPU 9 carries out an operation based on the data stored in the ROM 6 and the back-up memory 8.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to Japanese Patent Application Nos. Hei 8-316619 and 9-215200, incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a data processing device preferably used for controlling a fuel injection amount, fuel injection timing and the like in a fuel injection pump for supplying fuel to a diesel engine.

2. Description of Related Art

The fuel injection accuracy of a fuel injection pump for supplying fuel by injection to a diesel engine is greatly influenced by the accuracy of each mechanism element. Accordingly, as disclosed in Japanese Patent Examined Publication B2 4-28901, for example, the fuel injection pump is equipped with a ROM-type memory pre-storing correction data for absorbing dispersion of the mechanism elements. For driving a pump, the correction data stored in the memory is transferred to a control unit. The fuel injection by the pump is controlled by adding the correction data to the basic injection amount and the injection timing which are determined by other sensor signal inputs. Such correction data processing enables a reduction in the system dispersion.

The correction data becomes 2-byte data or more depending on resolution and range. That is, if strict resolution and accurate correction are required, the more minute the notch becomes, the necessary byte number is increased in relation to the same correction data range. However, the capacity of memory is increased to have a memory structure according to the maximum byte number. Therefore, the byte number of correction data is normally 1 byte to lower the number of active data as possible, but a useless 1-byte memory region for 1 byte data exists in a memory structure according to the 2 byte type data.

In addition, the correction data includes a large number of items. In such a case, an address corresponding to an item is generally provided in advance, but this method is not preferable from the standpoint of flexibility. Therefore, increasing the flexibility of the system is desired.

SUMMARY OF THE INVENTION

Therefore, it is an object of this invention to use correction data with different data lengths, with the entire memory region of the correction data, and to increase the flexibility of the storage of the items.

The above object is achieved according to a first aspect of the present invention by providing an operating device which carries out an operation based on correction data stored in a first storing device and correction data stored in a second storing device.

The correction data at this time have different data lengths depending on the item. However, since the second storing device stores a discrimination code for item discrimination and data length discrimination of the correction data in a pair with corresponding correction data, the storing region can be utilized more effectively compared with a case where a storing region for a maximum data length item is provided.

In addition, as the correction data is provided with the aforementioned discrimination code, replaceable correction data of a given item and a given data length can be prepared, thereby improving the flexibility of storing the item and increasing the versatility of the system.

According to claim 2, the first storing device and the second storing device can be separated. Accordingly, the data of a third storing device can be changed without changing the control data of the first storing device by transmitting the correction data stored in the second storing device, thereby correcting data based on the data of the third storing device.

According to claims 3 and 8, data may be transmitted between the second storing device and the third storing device by a serial communicating device, and a receiving device may discriminate the data length of the transmitted correction data by discriminating the most significant bit. Therefore, the data length can be discriminated by determining the discrimination code transmitted prior to the correction data.

According to claim 4, the system changes data in the memory from the state of the whole bits of "1" in the unwritten region of the replaceable ROM to the whole bits of "0" before replacing renewal data in the unwritten region. Accordingly, unnecessary data is determined if the data bits are all "0", thereby enabling quick processing (preventing meaningless data reading).

In addition, data replacement is performed by using the unwritten region in the replaceable ROM so that data renewal is freely performed.

Further, the transmitting device may successively transmit from the leading address of the second storing device up to the address one address before the address of the region storing the discrimination code and the correction data indicating whole bit data of "1" and skip the address of the region storing the discrimination code and the correction data indicating whole bit data of "0". Therefore, all bit data except the address of the region having whole bit data of "0" can be successively transmitted from the leading address up to the address of the region having whole bit data of "1".

Since the second storing device storing data of instrumental error for the fuel injection pump is provided, the second storing means and the fuel injection pump can be integrally controlled.

Still further, even if the fuel injection pump is exchanged, preferable control reflecting the instrumental error for the fuel injection pump can be obtained without changing the control data of the first storing device.

When a predetermined condition is realized, the correction data may be transmitted from the second storing device to the third storing device and/or the received data of the third storing device may be checked. Accordingly, a suitable transmitting timing for the correction data and/or a suitable check timing of the received data can be obtained.

Here, the time when the predetermined condition is realized means, when the electric power source is supplied, in every predetermined period, or when the operation load is light.

Other objects and features of the present invention will appear in the course of the description thereof, which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and advantages of the present invention will be more readily apparent from the following detailed description of preferred embodiments thereof when taken together with the accompanying drawings in which:

FIG. 1 is an entire block diagram of a control unit of a fuel injection pump according to a first preferred embodiment of the present invention;

FIG. 2 is a flowchart showing processing up to calculating a fuel injection amount in the embodiment;

FIG. 3 is a block diagram of memory of an OTPROM in the embodiment;

FIG. 4 is a diagram showing a definition table of discrimination codes according to the embodiment;

FIG. 5 is a diagram showing a correction point in a governor pattern according to the embodiment;

FIG. 6 is a flowchart showing communication processing of correction data according to the embodiment;

FIG. 7 is a diagram of data communication state in the embodiment;

FIG. 8 is a timing chart relating to serial data output in the embodiment;

FIG. 9 is a block diagram of a serial communication interface including the OTPROM in the embodiment;

FIG. 10 is a flowchart for explaining a second preferred embodiment of the present invention;

FIG. 11 is a flowchart for explaining a modification of the second embodiment;

FIG. 12 is a flowchart for explaining a third preferred embodiment of the present invention;

FIG. 13 is a flowchart for explaining a fourth preferred embodiment of the present invention;

FIG. 14 is an another flowchart for explaining the fourth embodiment;

FIG. 15 is a block diagram for explaining the fourth embodiment; and

FIG. 16 is an a time chart for explaining the fourth embodiment.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EXEMPLARY EMBODIMENTS

A first embodiment of the present invention is described hereinafter with reference to the drawings.

The present embodiment is implemented as a control unit of a fuel injection pump for a vehicle-mounted diesel engine. FIG. 1 shows the entire structure of the control unit of the fuel injection pump.

In a diesel fuel injection pump (control object) 1 for supplying fuel to a diesel engine, an actuator 2 for controlling an injection amount and an actuator 3 for controlling injection timing are provided. A control unit for controlling the fuel injection pump 1 is constituted by a pump side controller (characteristic dispersion memory device) 4 which is mounted on the pump 1 and a non-pump side controller (main body of the control unit) 5 which is not mounted on the pump 1. The non-pump side controller 5 is packaged as an electronic control unit (ECU).

The non-pump side controller 5 includes a ROM 6 storing a basic control data. The pump side controller 4 and the non-pump side controller 5 communicate via synchronous serial communication. The correction data stored in an OTPROM 7 of the pump side controller 4 are transmitted to a back-up memory 8 of the non-pump side controller 5. The actuators (electrical actuators) 2 and 3 are drive-controlled by using the correction data.

The following is a detailed description of the control unit.

The pump side controller 4 includes the aforementioned OTPROM (characteristic dispersion element) 7, a serial communication interface 10, a communication buffer 11, an input filter 12, a capacitor 13 for a power source, and

diodes

14 and 15 for preventing reverse current. Data stored in the OTPROM 7 is data of instrumental error for the fuel injection pump. The data corresponds to a difference between a standard pump injection characteristic and a pump injection characteristic examined by actually injecting the fuel injection pump 1 during inspection at a factory. The OTPROM 7 is a writable non-volatile storage element in which data can be written only one time. Accordingly, 8-byte data becomes all "1" in an initial condition, that is, FFH in hexadecimal notation (H indicates a hexadecimal number, and so forth) so that a given byte can be written from "1" to "0" only one time (not from "0" to "1"). However, even if any data is written, the byte of "1" can be replaced to "0". Namely, if any one of the bytes is left "1", all bytes are replaced to "0", resulting in the data of "00H". In addition, the OTPROM 7 does not need electric power source for maintaining data, but the OTPROM 7 is an element which requires the electric power source for access.

Accordingly, the controller 4 is mounted on the diesel fuel injection pump 1 and is controlled integrally with the diesel fuel injection pump 1 without any need for readjustment of a control unit when exchanging the diesel fuel injection pump 1.

The non-pump side controller 5 is for carrying out various operations regarding control of the diesel fuel injection pump 1. The non-pump side controller 5 includes a CPU 9, an input signal buffer 16, an analog-digital converter (ADC) 17, an electric power supply circuit 18, a PNP transistor 19, resistor 20, a communication buffer 21, an actuator drive circuit 22, the ROM 6 and the back-up memory 8. The electric power supply circuit 18 receives electric power from a battery via an ignition key switch 23 and supplies a pre-determined electric voltage to each of the apparatuses (circuits) in the non-pump side controller 5. The CPU 9 incorporates various kinds of sensor signals via the input signal buffer 16.

If the sensor signal is an analog signal, the signal is converted to a digital value by the ADC 17 and incorporated in the CPU 9. The sensor signal is an accelerator opening signal from an accelerator opening sensor, an engine rotation speed signal from an engine rotation speed sensor (crank angle sensor), an intake air pressure signal from an intake air pressure sensor, an intake air temperature signal from an intake air temperature sensor, a coolant temperature signal from an engine coolant temperature sensor, or the like.

Relevant data for each kind of engine (control data under no pump instrumental error) is stored in the ROM 6. That is, the ROM 6 functions as a storage element for storing a central value control data.

The back-up memory 8 is a writable storage element which stores data by the electric power supplied from the battery 24 even when the ignition key switch 23 is turned off. The correction data transmitted from the OTPROM 7 of the pump side controller 4 is stored in the back-up memory. This is for the purpose of storing the correction data with a minimum communication frequency by continuing the electric power supply to the back-up memory 8 when the electric power source is supplied while the system is in operation, of course, and even when the ignition key switch 23 is turned off. Accordingly, the back-up memory 8 functions as a storage element for storing the correction data.

The non-pump side controller 5 and the pump side controller 4 are connected by three signal lines L1, L2, and L3 for communication. With power source voltage Vcc (5 volts) applied to an emitter terminal of the PNP transistor 19 of the non-pump side controller 9, a base terminal of the PNP transistor 19 is connected to the CPU 9. Furthermore, a collector terminal of the PNP transistor 19 passes through a power supply and clock signal line L1 via the resistance 20 and is connected to the capacitor 13 via the input filter 12 and the diode 14 of the pump side controller 4. Simultaneously, the power supply and clock signal line L1 branches off from an upstream side of the diode 14 inside of the pump side controller 4 and are connected to the serial communication interface 10. In the pump side controller 4, the capacitor 13 for the electric power source is connected to the OTPROM 7 via the diode 15, and also is connected to the serial communication interface 10.

The CPU 9 performs on-off control of the transistor 19 to send pulse signals of an L level (ground electrical potential) and an H level (Vcc electrical potential; 5 volts) via the power supply and clock signal line L1 to the pump side controller 4. The pulse signals are transmitted to the serial communication interface 10 after removing noise via the input filter 12. The signals become clock signal for the serial communication interface 10. The pulse signal from the power supply and clock signal line L1 becomes an electric power source for the OTPROM 7 and the serial communication interface 10. Accordingly, the capacitor 13 for the electric power source stores the electric power and the OTPROM 7 and the serial communication interface 10 are supplied with the electric power.

The serial communication interface 10 of the pump side controller 4 is connected to the CPU 9 through the communication buffer 11, the serial communication line L2 and a communication buffer 21 in the non-pump side controller 5. In addition, the ground line L3, directly connected to the ground electric potential at the non-pump side controller 5 side and the ground electric potential at the pump side controller 4, functions as an operation reference electric potential for both of the

controllers

4 and 5.

During data communication under normal control, the corrected data pre-written in the writable OTPROM 7 in the pump side controller 4 can be transmitted to the non-pump side controller 5 by connecting the three lines L1, L2 and L3 only. Additionally, a voltage supply line for writing L4 is disposed as a terminal of the pump side controller 4. This terminal is used only for writing or reloading data in the writable OTPROM 7 in the pump side controller 4 when or after delivering. That is, a data input tool 25 is connected to L1 through L4 as illustrated in alternate long and short dash lines, and writing voltage is applied to the voltage supply line for writing L4 to input data. In the present embodiment, the serial communication line L2 is used as a signal line for inputting write data, but an input signal line only for writing may be individually provided.

When communicating, synchronous with the clock signal outputted from the non-pump side controller 5, the correction data is outputted one byte at a time successively from the OTPROM 7 in the pump side controller 4 through the serial communication interface 10 and the communication buffer to the serial communication line L2, that is, a clock synchronous communication is operated. At this point, the serial interface 10 repeats sending data of the OTPROM 7 as long as the power source and the clock signal are supplied. In addition, signal level conversion or impedance conversion is performed by the communication buffer 11.

An actuator drive circuit 22 of the non-pump side controller 5 and the actuator 2 for controlling the injection amount in the diesel fuel injection pump 1 are connected by a drive line 26. The actuator drive circuit 22 is also connected to the actuator 3 for controlling injection timing by a drive line 27.

The CPU 9 of the non-pump side controller 5 carries out an operation using relevant data (data under no pump instrumental error) for each kind of engine stored in the ROM by various sensor signals. On the basis of the operation result, an actuator drive signal SG1 for controlling the injection amount and an actuator drive signal SG2 for controlling the injection timing are outputted via the actuator drive circuit 22 to obtain the fuel injection amount and the fuel injection timing required corresponding to the engine operational condition. Therefore, the drive signals SG1 and SG2 drive the actuator 2 for controlling the injection amount and the actuator 3 for controlling the injection timing.

For the fuel injection operation, more specifically, as illustrated in FIG. 2 (a data flowchart of fuel injection amount calculating process by the CPU 9), a basic injection amount calculator 30 calculates a basic injection amount Qa based on the accelerator opening and the engine rotation speed. A basic largest injection amount calculator 31 calculates a basic largest injection amount Qb based on the engine rotation speed and the intake air pressure. Further, a correction calculator 32 corrects the basic largest injection amount based on a correction coefficient K1 by the intake air temperature and a correction coefficient K2 by the coolant temperature and calculates a basic largest injection amount after correction Qb' (= Qb*K1*K2). Next, a selector 33 selects a smaller one of the basic injection amount Qa and the basic largest injection amount after correction Qb'. An adder 34 performs acceleration correction by the accelerator opening in relation to the minimum value.

An instrumental error correction calculator 35 calculates an instrumental error dispersion correction ΔQ based on the correction data received as serial communication data by the pump side controller 4, the engine rotational speed and the basic injection amount Qa obtained by the basic injection amount calculator 30. Next, an adder-subtracter 36 adds or subtracts the instrumental error dispersion correction ΔQ obtained from the instrumental error dispersion calculator 35 in relation to an output value of the adder 34 in order to correct the correction according to the instrumental dispersion of the injection pump. Further, an adder-subtracter 37 outputs a calculation result as a final injection amount after adding and subtracting various corrections in relation to the output value of the adder-subtracter 36.

Accordingly, the correction corresponding to the instrumental error dispersion for the injection pump is made based on the characteristic dispersion correction data received as serial communication data by the pump side controller 4. The correction is then reflected in the final injection amount.

The fuel injection timing can be corrected in the same way as above without limiting specific process.

Therefore, since the characteristic dispersion between individual devices caused by machine work accuracy and assembly accuracy exists in the diesel fuel injection pump 1, the actual fuel injection amount and the fuel injection timing obtain dispersion by the fuel injection pump instrumental error even if the same drive signal is outputted in the same engine operation state. However, the characteristic dispersion is closely corrected by using the correction data of the OTPROM 7 stored in the back-up memory 8 so that the fuel injection amount and the fuel injection timing close to the desired value are obtained, thereby improving engine performance.

Data contents of the OTPROM 7 and communication processing of the same data will now be described in detail.

FIG. 3 shows a memory structure of the OTPROM 7.

To simplify the memory structure, when a clock signal is supplied from the outside after supplying the electric power, the OTPROM 7 has a function of only outputting data successively from the top synchronously with the clock signal. The OTPROM 7 has a structure which successively writes data on a write region in a whole write region and leaves the rest of the whole write region unwritten as a reserve region. However, the structure of the OTPROM 7 automatically detects this unwritten area 58 to output the top data continuously after the first data of the unwritten area 58. Therefore, when continuing supplying the clock signals, the data of the region only where the data is actually written is continuously outputted.

In FIG. 3, data is written in a specific data pattern as lead discrimination data 50 for discriminating the first six bytes as the lead (top). That is, the top can be discriminated even if the data is continuously outputted.

Additionally, in lower-ranking regions lower than the lead discrimination data 50, a discrimination code 51 and correction data 52 are paired up, and a discrimination code 53 and

correction data

54 and 55 are also paired up to be written in a given order. The

discrimination codes

51 and 53 are codes for discriminating items and data lengths of the

correction data

52, 54 and 55.

Namely, the correction data include items such as engine rotational speed, injection amount and injection correction amount as two or more-byte data depending on resolution per item and a data range. That is, the number of bytes of correction data is generally one byte in order to reduce the number of operating bits, but the necessary number of bytes is increased in relation to the same correction data range because the intervals become detailed when detailed resolution and accurate correction is desired: for instance, for the injection correction amount, when the data range is 0 to 256mm³/st, one byte for resolution of 1mm³/st, two bytes for resolution of 1/256mm³/st, and three bytes for resolution of 1/256/256/mm³. Accordingly, the discrimination codes are classified as the discrimination codes for the correction data of one byte from the discrimination codes for the correction data of two bytes so that the number of bytes of the correction data for the identification codes can be distinguished by checking the discrimination codes. In FIG. 3, correction data of two bytes is constituted by the correction data 54 of a least significant byte (least significant 8 bits) and the correction data 55 of a most significant byte (most significant 8 bits). The discrimination code 53 is provided for the

correction data

54 and 55.

In addition, the correction data in the OTPROM 7 is stored in the back-up memory 8.

FIG. 4 shows a relationship between the discrimination code and the correction data (definition of the discrimination code). FIG. 4 illustrates the content of the four most significant bits of the discrimination code in column and the content of the four least significant bits of the discrimination code in row. The matrix (an intersection) is the correction data corresponding to the discrimination codes. That is, the discrimination code is a combination of the most significant four bits and the least significant four bits, and FIG. 4 shows what kind of correction data the correction data in the matrix is. For instance, a discrimination code of "10H" is one of the correction data of an engine rotational speed N1. Namely, when a discrimination code "10H" is received, the obtained correction data is the engine rotational speed N1.

Here, a region of the most significant four bits in the discrimination code is divided into two regions: a 0H through 7H region of the discrimination code corresponding to one-byte data and a 8H through FH region of the discrimination code corresponding to two-byte data. Accordingly, the number of the correction data can be easily discriminated by determining the most significant bit in the discrimination code is "0" or "1". For example, the aforementioned engine rotational speed N1 is one-byte data because its discrimination code is "10H" and the most significant bit is "0". In the same way, the byte number of the correction data can be determined by subdividing the most significant bit regions of the discrimination code.

In addition, "00H" in the discrimination codes in FIG. 4 is prohibited for use as a reservation code so that the "00H" data can be discriminated after overwriting is performed during replacement of data. Further, "FFH" in the discrimination codes in FIG. 4 is also prohibited for use as a reservation code because an initial state of the discrimination code is "FFH" so that initial state data can be discriminated.

Back to the description of FIG. 3, a discrimination code 56 of a block-check character BCC is written in a byte which is less significant than a correction data written region in order to write BCC value 57 for obtaining reliability of the entire data in the less significant byte. That is, "7FH" as a discrimination code of the BCC value is prohibited in use as a discrimination code for other correction data.

A process of replacing a part of the correction data in a memory structure of the OTPROM 7 using the data input tool 25 in FIG. 1 will now be described. Namely, described here is a process of replacing a part of the previously written data when the characteristics to be corrected are transformed due to recycling of the OTPROM 7 itself, exchanging and repairing parts of a fuel injection pump, and the like after shipping.

From the condition illustrated in FIG. 3, first of all, given unnecessary data (a discrimination code plus correction data) is overwritten to be "00H". Next, to change the variable BCC value, a discrimination code (in this embodiment "7FH") indicating the block-check character BCC value and the following BCC value are all changed to "00H". Further, data desired to be changed (the discrimination code and the correction data) is written in a top of an unwritten region 58, and in succession, the recalculated BCC value is written with the discrimination code "7FH".

In this way, the unwritten region 58 in FIG. 3 is replaced. As a result of this, in reading the OTPROM 7 after the replacement, when "00H" data exist, the "00H" data is skipped as unnecessary data because "00H" is previously allotted as a non-discrimination code. Although the replaced data changes the order to be read later, that is not a problem at all. Accordingly, as long as the unwritten spared region 58 exists, data can be replaced in the OTPROM 7.

By using a governor pattern illustrated in FIG. 5, a relationship between the discrimination codes in FIG. 4 and a correction point on the actual governor pattern will now be described.

The governor pattern is a pattern illustrating a required injection amount per engine rotational speed using the accelerator opening as a parameter. That is, the governor patter illustrates just the injection amount characteristics of the fuel injection pump, thereby requiring correction data for correcting the characteristic dispersion of the individual injection pump in each point on the governor pattern to adjust master characteristics. Here, as for determining the correction point, essential operating conditions such as a starting injection amount control point, an idling point, a torque point and the like are applied as points especially important as characteristics.

As aforementioned, the region of the discrimination codes is divided between a one-byte area for the most significant four bits of 0H - 7H and a 2-byte area for the most significant four bits of 8H - FH to indicate the byte number of the corresponding correction data. In FIG. 5, the discrimination codes includes correction points N1(10H), N2(11H) and N3(12H) in an engine rotational speed direction and injection amount correction points [Q1L(20H), Q1H(30H)], [Q2L(21H),Q2H(31H)] and {Q3L(22H),Q3H(32H)} corresponding to the correction points N1(10H), N2(11H) and N3(12H) in the engine rotational speed direction. Here, corresponding discrimination codes are followed in parentheses. The data of the engine rotational speed and the injection amount are all one-byte data because the most significant four bits in the discrimination codes are 1H to 3H.

In relation to the above-mentioned six points in total (three correction points in the engine rotational speed direction * two correction points in the injection amount direction = six points), each point is provided with injection correction A1L(80H), A1H(90H), A2L(81H), A2H(91H), A3L(82H) and A3H(92H), respectively. Here, corresponding discrimination codes are followed in parentheses. The data of the injection correction are two-byte data because the most significant four bits of the discrimination code are 8H - 9H.

As for a concept of the byte size in this case, the engine rotational speed and the injection amount indicating the correction points are the values indicative without subdividing the resolution, while the data of the injection correction themselves are arranged to be two-byte data by subdividing the resolution because accurate correction is required. In addition, two injection amount correction points are provided per engine rotational speed correction point for enabling a linear interpolation operation between the two points. Therefore, conversely, two engine rotational correction points may be provided per injection amount correction point by determining the points in the injection amount direction first.

As shown in FIG. 5, when the idle point changes from N1 to N1' due to the idle rotation change, the correction data N1 corresponding to the discrimination code 10H should change only from N1 to N1'.

Next, a process of transferring the data in the OTPROM 7 to the back-up memory 8 in the non-pump side controller 5 is described.

FIG. 6 is a flowchart illustrating the details of the communication process which the CPU 9 in the non-pump side controller 5 executes. A requirement of starting communication is that in a initial processing by turning on the ignition key switch 23, (1) receiving the correction data is not finished, and (2) an abnormality is detected when data stored in the back-up memory 8 is checked by the block-check character (BBC value).

First, after the CPU 9 in FIG. 1 detects the lead discrimination data (see FIG. 3) for discriminating the lead of the data, the CPU 9 reads one datum, that is a discrimination code, in step 100 and checks whether the code is "00H" or not in step 101. If the code is "00H", because "00H" is prohibited for the discrimination code for discriminating the overwrite data for the data replacement, the CPU 9 proceeds to step 102 to skip to the next data and return to step 100. When the CPU 9 determines the code is a discrimination code other than "00H" in step 101, the CPU 9 proceeds to step 103 to check whether the code is a discrimination code of "7FH" which means an end code, or the block-check character BCC value. If the code is "7FH", the next data is read as a BCC value and this processing is terminated in step 104.

When the code is not "7FH", the CPU 9 proceeds to step 105 to search the discrimination code chart shown in FIG. 4 for the content of the code. If the code doesn't coincide with any of "the discrimination codes", the CPU 9 determines that the code is an undefined code and executes an undefined code error processing routine in step 106.

As a result of searching the code in step 105, if the code coincides with a certain discrimination code, the CPU 9 goes to step 107 to determine whether the uppermost bit of the discrimination data is "0" (one-byte region) or "1" (two-byte region). In consequence, if the uppermost bit is "0", the CPU 9 proceeds to step 108 to read the next data as correction data and to step 109 to store the data in a communication RAM of a prescribed address inferred from the discrimination code.

When the uppermost bit of the discrimination data is "1" in step 107, the CPU proceeds to step 110 to read the next two data as correction data and store the two data in the communication RAM of a prescribed address inferred from the discrimination codes in step 111.

After processing of step 109 or 111, the CPU 9 returns to step 100 to read the next data as a discrimination code.

After the completion of receiving data, a communication error is checked during completion of receiving a final frame by using the BCC value obtained in step 104. If normality is determined, a receiving completion processing is operated. In this receiving completion processing, the data stored in the RAM for communication is stored in the back-up memory 8, the following correction operations are allowed, and an output of the clock signal is terminated in sequence.

Here, if normality is detected in communication error detecting processing operated upon completion of receiving one frame, data may be stored.

After the description of FIG. 6, as mentioned above, the unwritten region 58 in FIG. 3 at the side of the pump side controller 4 is automatically detected to output lead data at the side of the non-pump side controller 5 again after the final data in the written region. A detailed description about this is made below.

FIG. 7 is an explanation view illustrating a state of outputting data from the OTPROM 7 during the data communication.

As illustrated in FIG. 7, a group of data is called a frame. One frame is constituted by one bit as a start bit, eight bits as data bits, one bit as a parity bit and one bit as a stop bit. Written valid data has the start bit of "0" and the stop bit of "1" all the time, and the data becomes "0" or "1" corresponding to the written value. The parity bit becomes "0" or "1" on the basis of the number of "1" in the 8-bit data. For example, in case of even parity, the bit becomes "0" if the number of the "1" is even number, while the bit becomes "1" if the number of "1"'s is odd. In addition, the valid data is written closely one by one from the lead address.

Further, in the unwritten region, all eleven bits of one frame in the unwritten region are "1" since the entire bits in the unwritten region are "1" in the initial state of the OTPROM 7.

FIG. 8 shows a timing chart for related signals when outputting serial data. Below is a description of what time the serial data is successively outputted with reference to FIG. 8.

In a clock synchronous serial communication system, by supply of a clock signal which alternates between an H level and an L level, the serial data is outputted one bit at a time in synchronism with a valid edge (a rising edge from L level to H level). Transmission of idle data (8-bit data of all "1") precedes the output of one frame of data which is valid in the serial data output. This idle data is for holding an interval between the valid data for a predetermined period and obtaining reliable processing at the data receiving side. After the idle data, one frame (eleven bits) of valid data of address m is outputted. Namely, a start bit of address 0 (START), data bit 0 (D0), data bit 1 (D1), data bit 2 (D2) and so on are outputted in order up to data bit 7 (D7), parity bit (P) and stop bit (STOP; "1" fixed). In addition, the data bit 0 (D0) through the data bit 7 (D7) are outputted with LSB in the head of the bits. After that, 8 bits of "1" in total are outputted as idle data to leave some space between the frames. Next, a start bit of address 1 (START), data bit 0 (D0), data bit 1 (D1), data bit 2 (D2) and so on are outputted in order up to data bit 7 (D7), parity bit (P) and stop bit (STOP) in the same way.

Accordingly, while one frame of the data (eleven bits) is outputted in order, in an address counter, stop bit "1" is outputted when the eleventh bit of the stop bit is defined, that is, the stop bit "1" is outputted in synchronism with the rising edge from the L level to the H level of the clock signal. Next, when the clock signal rises from the H level to the L level (a timing of t1 illustrated in FIG. 8), a count value is incremented by 1 to be m+1. 8 bits of the idle data "1" is then outputted.

In FIG. 8, the valid data is written up to address m so that the address region m+1 and after is an unwritten region i.e., all bits are "1". As a frame of data (eleven bits) in address m+1 is an unwritten region and has all bits of "1", stop bit "1" is outputted in the address counter when the eleventh bit of the stop bit is defined, or synchronously with the rising edge of the clock signal from the L level to the H level. After that, the address counter is reset and the count value becomes "0" when the clock signal rises from the H level to the L level (a timing t2 shown in FIG. 8). Therefore, the in case of continuing input of the clock signal after this, serial data output of address 0 is obtained again after the idle data.

Accordingly, as illustrated in FIG. 7, since all eleven bits of one frame in the unwritten region are "1", when "1" is detected from all of the eleven bits of one frame during reading of the data, the address counter is reset, and data only in the written region is read without meaningless reading of "1" data in the unwritten region.

FIG. 9 shows a structural example of the serial communication interface 8 including the OTPROM 7.

The clock signals are supplied to a row decoder 41 and a column decoder 42 via an address counter 40. The row decoder 41 is for selecting eleven-bit word data, while the column decoder 42 is for selecting a bit position. That is, the row decoder 41 selects an address of a given frame (word) in the OTPROM 7 corresponding to an input pulse number of the clock signal, and the column decoder 41 selects the present bit of the bit output among eleven bits of the selected frame.

The obtained information of each bit is then outputted one bit at a time as a serial data output via a sense amplifier 43. This serial data output signal is converted into eleven-bit parallel data again by a serial parallel converter 44. A decode circuit 45 then checks whether this eleven-bit parallel data is all "1".

When the whole serial data output is "1", the decode circuit 45 generates a reset signal for the address counter 40. The count value of the address counter 40 is reset to "0" by the reset signal, and data of address 0 is then selected by the row decoder 41.

In the description using FIG. 9, an output of idle data (8 bits of "1") inserted between the valid data is omitted. In addition, the address counter 40 is constituted in a manner that the counter 40 is reset even the power source is turned off and the counter 40 starts from address 0 all the time regardless of the past operation when the power source is turned on.

Accordingly, the serial communication interface 8 successively transmits from the lead address of the OTPROM 7 up to one address before the address of the unwritten region (the region storing discrimination codes or correction data having whole "1" bit data). In addition, the serial communication interface 8 skips an address in a region overwritten as "00H" when replacing (the region storing discrimination code or correction data having entirely "0" bit data).

Accordingly, the data processing unit according to the present embodiment has following characteristics.

1. The CPU 9 in FIG. 1 performs a predetermined operation based on the control data stored in the ROM 6 and the correction data transmitted from the OTPROM 7 to the back-up memory 7. The correction data at this time have different lengths because 1-byte data and 2-byte data are included due to the items (the engine rotational speed, the injection amount and the injection correction amount). The OTPROM 7, on the other hand, includes discrimination codes for item discrimination and data length discrimination with corresponding correction data in pairs as illustrated in FIG. 3, thereby suppressing the memory region compared with the case of preparing a memory region corresponding to the maximum data length. Accordingly, the correction data having different data lengths can be used while suppressing the size of the memory region of the correction data. In addition, as the correction data is provided with the aforementioned discrimination code, correction data for a given item and a given data length can be prepared and replaced. Therefore, the versatility of the unit of the present embodiment is increased by improving the storage flexibility of the items. That is, in order to reduce the characteristic dispersion caused by machine work accuracy and assembly accuracy of the pump and to correspond the characteristic to required error for a particular kind of engine, when the memory storing the correction data is mounted in the fuel injection pump in one-to-one correspondence, or when the engine and the engine control unit (ECU; Electronic Control Unit) are integrally controlled with the fuel injection pump controlled integrally with the pump side memory system, although maximum flexibility is required by the system, the flexibility in selecting the data length and items of the correction data can be obtained in controlling at the pump side by, as in the present embodiment, providing the correction data with discrimination codes (8 bits) to define 256 kinds of discrimination codes freely.

2. As the serial communication interface 10 transmits the data between the OTPROM 7 and the back-up memory 8, by transmitting correction data stored in the OTPROM 7, data in the back-up memory 8 can be easily changed without changing control data in the ROM 6, thereby correcting the control data based on the changed data.

3. The CPU 9 has the back-up memory 8 store the correction data corresponding to the data length confirmed by discriminating the data length of the correction data transmitted after the decision of the most significant bit in step 107 in FIG. 6. Therefore, the data length can be discriminated by determining the discrimination code transmitted prior to the correction data.

4. From a condition that "1" remains in the whole bits in the unwritten region in the OTPROM 7, data bits before replacing are all "0" when data is replaced so that renewal data is replaced on the unwritten region. Accordingly, unnecessary data can be determined if the data bits are all "0" in the processing of step 101, thereby obtaining a quick processing (preventing meaningless data reading). Data can be replaced by using the unwritten region in the OTPROM 7 so that data renewal can be easily performed. That is, in case of the integral control of the engine and the engine control unit (ECU) with the integral control of the fuel injection pump and the pump side memory system as mentioned above, the flexibility in data length, items and correction data order of the correction data can be obtained in a control system at the pump side by freely defining the provided discrimination code. Namely, in controlling at the engine side, correspondence is obtained even if the required error at the pump side is different per kind of engines (an idle point, a torque point, a rated point or the like can be changed along with changing the correction point position and number at the governor pattern). The data contents of the pump side memory system can be also replaced in case of various requirements and design changes.

5. The serial communication interface 8 transmits the lead address of the OTPROM 7 successively up to the one address before the address of the region storing the discrimination code and correction data whose all bit data are indicated as "1" (unwritten region). The serial communication interface 8 skips the address of the region storing the discrimination code and correction data whose all bit data are indicated as "0" (the region indicated as "00H" when overwriting in replacement). Therefore, all bit data except the address of the region having all "0" bit data are successively transmitted up to the address of the region having all "1" bit data.

6. The OTPROM 7 storing the correction data for the pump is mounted in the fuel injection pump 1, and the ROM 6 storing the control data is mounted in the control unit for controlling the fuel injection pump 1. Accordingly, although the fuel injection pump 1 is changed, appropriate control is performed according to the instrumental error per pump without any changes in the control data of the ROM 6.

Following is a modification of the present embodiment.

Instead of the OTPROM 7 in FIG. 1, a non-volatile memory element such as an EPROM, a EEPROM, a flash memory or the like may be used. In the case of using a multiply erasable ROM as a substitute for the OTPROM 7, for a memory cell with its replacing number exceeding the predetermined number (permissible value), the data bits before replacing data to the memory cell may be all "0" so that renewal data is written in the unwritten region.

In addition, the ROM 6 in FIG. 1 is an external ROM of the CPU 9, but the ROM 6 may be a ROM in the CPU. Further, although the back-up memory 8 is an external memory of the CPU 9 in the embodiment, the back-up memory 8 may be a replaceable non-volatile memory such as a memory in CPU, a EEPROM, a flash memory or the like.

All bits when the initial state in the second store system are "1", but the bits may be all "0".

(Second Embodiment)

Next, a second embodiment of the present invention will now be described with emphasis on difference from the first embodiment.

In transmitting data of the OTPROM 7 to the back-up memory 8 of the non-pump side controller 5, starting requirements for communication processing (flowchart) in FIG. 6 in the first embodiment are (1) when receiving the correction data is not finished, and (2) when abnormality is detected in the data stored in the back-up memory 8 by a block-check character (BCC value). The second embodiment, however, has starting requirements as follows.

FIG. 10 shows check and communication processing of the data stored in the back-up memory according to the second embodiment.

When the ignition key 23 is turned on, the CPU 9 checks whether the data stored in the back-up memory 8 is correct or not in step 200. More specifically, when the previous communication is normally terminated, further to the correction data obtained by the communication, characters for block-check, such as a parity value, SUM value, or the like and keywords for indicating normal termination of the communication are stored so that the data is checked based on those values and keywords. If the result of the check is that the contents of the back-up memory 8 is correct, the CPU 9 proceeds step 202 to perform communication processing corresponding to FIG. 6.

On the contrary, if the result of the check is that the contents of the back-up memory 8 are not correct, the CPU 9 proceeds to step 201 before the communication processing to store an initial value of the correction data. In this way, by storing the initial value of the correction data, wrong correction data is prevented from being used during the period up to obtaining a correct value in communication. After this step 201, the CPU 9 proceeds to step 202 for operating the communication processing.

###Step 203 is followed after step 202 of the communication processing. In step 203, the CPU 9 determines whether or not the communication is normally terminated. If the communication is not normally terminated due to some abnormality, the CPU 9 proceeds to step 205 for abnormality processing. This abnormality processing includes retry of communication, storing an error code, turning on a light and the like and uses the value stored until the communication processing as correction data. If the CPU 9 determines that the communication is normally terminated in step 203, the correction data obtained by the communication is stored in the back-up memory 9 for further processing in step 204.

Accordingly, the present embodiment is structured in a way that one communication processing is performed when the ignition key switch 23 is turned on. Therefore, even if corruption of the correction data stored in the back-up memory occurs in a form that cannot be detected by the check processing in the step 200, the data can be restored by the recommunication when the ignition key switch 23 is turned on again.

Further, even if the present communication is not normally operated due to some abnormality, by the process of

steps

200, 202, 203 and 205, the stored data can be used unless the correction data stored in the back-up memory 8 are destroyed.

The present embodiment is described on condition that the data in the back-up memory 8 is directly used for processing. It may be a system of using memory for control as a normal RAM and of transmitting data stored in the RAM from the back-up memory 8 under a specific condition so that the data stored in the RAM is checked periodically.

Accordingly, the data processing unit according to the second embodiment has following characteristics.

1. The check and data communication (transmitting the correction data from the OTPROM 7 to the back-up memory 8) of the correction data stored in the back-up memory 8 is performed when a predetermined condition is realized, that is, when the ignition key switch 23 is turned on and the electric power source is supplied. Therefore, the correction data check and the data communication can be performed at a desired timing before controlling the actuator.

A modification of the present embodiment is shown in FIG. 11.

As shown in FIG. 11, the CPU 9 checks in step 200 whether or not the data stored in the back-up memory 8 is correct. If the data is correct, the processing bypasses steps 201 through 205 and is terminated without any communication processing. That is, compared with FIG. 10 in which one communication is operated for every turning on of the ignition key 23, in FIG. 11, when step 200 determines that the data stored in the back-up memory 8 is correct, the data is authenticated so that the processing is terminated without any communication. Therefore, the frequency of communication can be minimized when the processing load of the CPU 9 in communication is critical. In addition, the frequency of communication can be also minimized when minimization of noise generated by the communication is critical and when communication equipment is influenced by external noise.

(Third Embodiment)

Next, a third preferred embodiment of the present invention will now be described with emphasis on differences from the second embodiment.

FIG. 12 shows a check and a communication processing of data stored in the back-up memory 8 according to the third embodiment. The processing starts every predetermined period (one second, for example) during control.

The CPU 9 determines whether the processing is now in communication in step 300. If it's now in communication, the processing is terminated. If it's not in communication, the CPU 9 checks whether or not the data stored in the back-up memory 8 is correct in step 301. More specifically, in the same way as the communication processing of the initial processing with turning on the ignition key switch 23 in FIG. 10, the check is operated by character for block-check, such as a parallel parity value, SUM value and the like which are obtained from the calculation of the correction data, and a keyword indicating that the communication is normally terminated. As a result of the check, the CPU 9 terminates the processing when determining that the content of the correction data is correct, while the CPU 9 stores the initial value of the correction data in the back-up memory 8 in step 302 before the communication when determining that the content of the correction data is incorrect. Therefore use of wrong correction data is prevented during the time until a correct value is obtained in the communication.

After processing in step 302, the CPU 9 operates communication processing according to FIG. 6 and determines normal termination in communication in step 304. When the communication is not normally terminated due to some abnormality, the CPU 9 proceeds to step 306 for abnormality processing. This abnormality processing includes a retry of communication, storing a error code, turning on a light or the like, and uses the initial value prestored in step 302 as the correction data for the operation. When the CPU 9 determines normal termination, the CPU 9 stores the correction data obtained by the communication in step 305 in the back-up memory 8 for the further operation.

In this way, the check and the data communication of the correction data stored in the back-up memory 8 are operated in every predetermined time (when prescribed condition is realized). Therefore, even if the correction data is destroyed for some reason during the control, correct correction data can be used again by check and recommunication.

(Fourth Embodiment)

Next, a fourth preferred embodiment of the present invention will now be described with emphasis on differences from the third embodiment.

FIG. 13 illustrates check processing of data stored in the back-up memory 8, and FIG. 14 shows communication processing according to the fourth embodiment. The check processing of FIG. 13 starts at every predetermined period (one second, for example) during control. In addition, the communication processing is performed when the prescribed condition is realized.

The CPU 9 first determines whether or not the processing is in communication. If it's not in communication, the CPU 9 proceeds to step 401 to check if the data stored in the back-up memory 8 is correct. If the data is incorrect, an initial value of the correction data is stored in the back-up memory 8 in step 402 and the processing is terminated.

After checking the data in the back-up memory 8 at every predetermined period during the control, if the CPU 9 determines the content of the back-up memory 8 is incorrect, the CPU 9 stores only the initial value of the correction data and terminates processing without performing communication. That is, since the engine is normally in operation during the control, the CPU stores the initial value in case the influence of the noise generated by the communication on the external equipment and the influence of the noise on the communication from the external equipment are critical or the processing load of the CPU in communication is critical.

The CPU 9 determines whether or not the communication condition is realized in step 500 in FIG. 14 and performs communication processing in step 501 if the condition is realized. Next the CPU 9 determines whether or not the communication is normally terminated in step 502. Abnormality processing is performed in step 504 if normal termination is not determined, and the data obtained by the communication is stored in the back-up memory in step 503 if normal termination is detected.

Here, to explain the condition for starting communication in step 500, the following conditions are considered: (i) in case that the operative position of the key switch is in a engine-stop and electric power is supplied to the control system; (ii) in case of idling the engine; (iii) during continuing the electric power source is supplied after the ignition key switch 23 is turned off. More specifically, when the CPU 9, which monitors the engine rotational speed, finds the rotational speeds is "0" rpm, the CPU 9 starts communication with determining the state of the above-mentioned condition (i) exists. In addition, when the CPU 9 monitors the engine rotational speed of 600-700 rpm, the CPU state starts communication with determining the state of the above-mentioned condition (ii) exists. The operation load of the CPU 9 is light in idling.

Further, as an example of condition (iii), the condition can be applied to a system with a delay function (timer) as shown in FIG. 15. In FIG. 15, the CPU 9 is connected to a coil 70a of a relay circuit 70 for supplying electric power to the non-pump side controller 5. A contact 70b of the relay circuit 70 is disposed between the battery 24 and the electric power source circuit 18. In addition, the CPU 9 is connected to an intake air valve 71, which is provided to an intake pipe of the diesel engine. As shown in FIG. 16, when the CPU 9 detects that the ignition key switch 23 is turned off, the supply of electric current to the coil 70a of the relay circuit 70 is terminated after a predetermined period T (about two seconds, for example) and the contact 70b is opened to terminate the supply of electric power from the battery 24 to the electric power source circuit 18. Meanwhile, the CPU 9 closes the intake air valve 71 in the predetermined period T after the ignition key switch 23 is turned off. In this way, by closing the intake air valve 71 at the time of stopping the engine, discrepancy of engine vibration is resolved to operate engine stop smoothly. In such kinds of engines, the communication processing of step 501 in FIG. 14 is operated in the predetermined period T after turning off the ignition key switch 23.

Accordingly, the communication is operated while supplying the electric power source after turning off the ignition key switch 23. In case of the above-mentioned condition (iii), the vehicle-mounted unit stops so that the influence of the noise from the unit in the communication and the influence of the noise generated by the communication on the vehicle-mounted unit can be reduced. Further, the communication is operated while the operation load of the CPU 9 is light.

Therefore, the present embodiment optimizes communication starting timing so that the influence of the noise generated by the communication on the external equipment is reduced, the influence of the noise from the external equipment on the communication is also reduced and the processing load of the CPU 9 can be reduced.

For a modification of the present embodiment, the processing is once terminated after checking data in step 200 with turning on the ignition key switch 23 and storing the initial value in step 201 as shown in FIG. 10. The communication processing of step 202 may start when the prescribed condition is realized (corresponding to the time when the condition is realized in step 500 of FIG. 14)

Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the present invention as defined by the appended claims.

Claims

A data processing device comprising:

first storing means (6) for storing basic control data;

second storing means (7) for storing correction data related to said basic control data; and

operating means (9) for carrying out a predetermined operation based on data stored in said first (6) and second (7) storing means;
wherein said correction data have different data lengths depending on items to which they relate, and
said second storing means (7) includes a discrimination code for item discrimination and data length discrimination of said correction data associated with corresponding correction data.
A data processing device according to claim 1, wherein:
said second storing means (7) is mounted on a fuel injection pump (1) for supplying fuel to a diesel engine;
said first storing means (6) is mounted on a controller (5) for controlling said fuel injection pump (1);
said data stored in said first storing means (6) is control data for controlling said fuel injection pump (1); and
said data stored in said second storing means (7) is data for each possible type of said fuel injection pump (1).
A data processing device according to claim 2, further comprising:

third storing means (8), disposed on said controller (5), for storing correction data stored in said second storing means (7);

serial communicating means (10, 11, 21) for transmitting data between said second storing means (7) and said third storing means (8);

receiving means (9) for discriminating data length of said correction data transmitted after determination of a bit pattern in said discrimination code by said serial communication;
wherein said operating means (9) is for carrying out said operation based on said control data stored in said first storing means (6) and said correction data stored in said third storing means (8); and
said receiving means (9) is for storing said correction data corresponding to said data length confirmed by said receiving means (9).
A data processing device comprising:

first storing means (6) for storing basic control data;

second storing means (7), physically separate from said first storing means, for storing correction data related to said basic control data;

third storing means (8) for storing correction data stored in said second storing means, said correction data being transmitted from said second storing means (7); and

operating means (9) for carrying out a predetermined operation based on data stored in said first (6) and third (8) storing means;
wherein said correction data include data having different lengths depending on items to which they relate, and
said second storing means (7) includes a discrimination code for item discrimination and data length discrimination of said correction data associated with corresponding said correction data.
A data processing device according to claim 4, further comprising:

serial communicating means (10, 11, 21) for performing data transmission between said second storing means (7) and said third storing means (8); and

receiving means (9) for discriminating a data length of said correction data transmitted after determination of a most significant bit in said discrimination code;
wherein said third storing means (8) is for storing said correction data corresponding to said data length confirmed by said receiving means (9).
A data processing device according to claim 4, wherein:
said second storing means is a replaceable ROM having all bits set to "1" in an initial state; and
said bits before replacement change to "0" under data replacement to replace renewal data in an unwritten region of said ROM.
A data processing device according to claim 6, further including transmitting means (10, 11, 21) for transmitting data from a leading address of said second storing means (7) up to an address one address before an address of a region storing entire bit data of "1" are successively transmitted, and skipping an address of a region storing said discrimination code and correction data indicating entire bit data of "0".
A data processing device according to claim 4, wherein:
said second storing means (7) is mounted on a fuel injection pump (1) for supplying fuel to a diesel engine;
said first (6) and third (8) storing means are mounted on a controller (5) for controlling said fuel injection pump (1); and
said data stored in said second storing means (7) is data to correct dispersion of the mechanism elements for each possible type of said fuel injection pump (1).
A data processing device according to claim 4, wherein at least one of transmission of said correction data from said second storing means (7) to said third storing means (8) and a check of received data of said third storing means (8) is performed when a predetermined condition is realized.
A data processing device according to claim 9, wherein said predetermined condition is realized when electric power is supplied.
A data processing device according to claim 9, wherein said predetermined condition is realized when a predetermined time period has passed.
A data processing device according to claim 9, wherein said predetermined condition is realized when an operation load is light.
A data processing device according to claim 2 or 8, wherein:
said second storing means (7) is for storing correction data of multiple points in a governor pattern of said fuel injection pump (1) and a discrimination code corresponding to said correction data; and
said receiving means (9) is for determining a data length and an item of said correction data by a combination of a bit pattern of said discrimination code.