EP0817072A3 - Système multiprocesseur capable de stocker des états cohérence dans plusieurs sous-noeuds d'un noeud de traitement - Google Patents

Système multiprocesseur capable de stocker des états cohérence dans plusieurs sous-noeuds d'un noeud de traitement Download PDF

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Publication number
EP0817072A3
EP0817072A3 EP97304617A EP97304617A EP0817072A3 EP 0817072 A3 EP0817072 A3 EP 0817072A3 EP 97304617 A EP97304617 A EP 97304617A EP 97304617 A EP97304617 A EP 97304617A EP 0817072 A3 EP0817072 A3 EP 0817072A3
Authority
EP
European Patent Office
Prior art keywords
access rights
transaction
subnode
processing node
subnodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP97304617A
Other languages
German (de)
English (en)
Other versions
EP0817072A2 (fr
Inventor
Erik E. Hagersten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oracle America Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of EP0817072A2 publication Critical patent/EP0817072A2/fr
Publication of EP0817072A3 publication Critical patent/EP0817072A3/fr
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
EP97304617A 1996-07-01 1997-06-27 Système multiprocesseur capable de stocker des états cohérence dans plusieurs sous-noeuds d'un noeud de traitement Ceased EP0817072A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US674274 1984-11-23
US08/674,274 US5878268A (en) 1996-07-01 1996-07-01 Multiprocessing system configured to store coherency state within multiple subnodes of a processing node

Publications (2)

Publication Number Publication Date
EP0817072A2 EP0817072A2 (fr) 1998-01-07
EP0817072A3 true EP0817072A3 (fr) 2001-11-14

Family

ID=24705992

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97304617A Ceased EP0817072A3 (fr) 1996-07-01 1997-06-27 Système multiprocesseur capable de stocker des états cohérence dans plusieurs sous-noeuds d'un noeud de traitement

Country Status (3)

Country Link
US (1) US5878268A (fr)
EP (1) EP0817072A3 (fr)
JP (1) JPH10187645A (fr)

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US6067611A (en) * 1998-06-30 2000-05-23 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency
US6085293A (en) * 1998-08-17 2000-07-04 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6081874A (en) * 1998-09-29 2000-06-27 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6108764A (en) * 1998-12-17 2000-08-22 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention
US6490661B1 (en) 1998-12-21 2002-12-03 Advanced Micro Devices, Inc. Maintaining cache coherency during a memory read operation in a multiprocessing computer system
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6275905B1 (en) * 1998-12-21 2001-08-14 Advanced Micro Devices, Inc. Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
US6370621B1 (en) 1998-12-21 2002-04-09 Advanced Micro Devices, Inc. Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US6275900B1 (en) * 1999-01-27 2001-08-14 International Business Machines Company Hybrid NUMA/S-COMA system and method
US6115804A (en) * 1999-02-10 2000-09-05 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that permits multiple caches to concurrently hold data in a recent state from which data can be sourced by shared intervention
US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US7234029B2 (en) * 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6791412B2 (en) * 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US20020087775A1 (en) * 2000-12-29 2002-07-04 Looi Lily P. Apparatus and method for interrupt delivery
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US20020087766A1 (en) * 2000-12-29 2002-07-04 Akhilesh Kumar Method and apparatus to implement a locked-bus transaction
US6971098B2 (en) 2001-06-27 2005-11-29 Intel Corporation Method and apparatus for managing transaction requests in a multi-node architecture
US6748479B2 (en) 2001-11-20 2004-06-08 Broadcom Corporation System having interfaces and switch that separates coherent and packet traffic
US7394823B2 (en) * 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US7206879B2 (en) * 2001-11-20 2007-04-17 Broadcom Corporation Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
FR2832859B1 (fr) * 2001-11-28 2004-01-09 Commissariat Energie Atomique Generateur electrochimique au lithium comprenant au moins une electrode bipolaire avec substrats conducteurs en aluminium ou alliage d'aluminium
US6965973B2 (en) 2002-05-15 2005-11-15 Broadcom Corporation Remote line directory which covers subset of shareable CC-NUMA memory space
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US6993631B2 (en) * 2002-05-15 2006-01-31 Broadcom Corporation L2 cache maintaining local ownership of remote coherency blocks
US7003631B2 (en) * 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7089376B2 (en) * 2003-03-20 2006-08-08 International Business Machines Corporation Reducing snoop response time for snoopers without copies of requested data via snoop filtering
US7395380B2 (en) * 2003-03-20 2008-07-01 International Business Machines Corporation Selective snooping by snoop masters to locate updated data
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US6988173B2 (en) * 2003-05-12 2006-01-17 International Business Machines Corporation Bus protocol for a switchless distributed shared memory computer system
US7085898B2 (en) * 2003-05-12 2006-08-01 International Business Machines Corporation Coherency management for a “switchless” distributed shared memory computer system
US7644221B1 (en) 2005-04-11 2010-01-05 Sun Microsystems, Inc. System interface unit
US7360032B2 (en) * 2005-07-19 2008-04-15 International Business Machines Corporation Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks
US7395376B2 (en) * 2005-07-19 2008-07-01 International Business Machines Corporation Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks
US20080082622A1 (en) * 2006-09-29 2008-04-03 Broadcom Corporation Communication in a cluster system
US7636816B2 (en) * 2006-09-29 2009-12-22 Broadcom Corporation Global address space management
US7698523B2 (en) * 2006-09-29 2010-04-13 Broadcom Corporation Hardware memory locks
US7631150B2 (en) * 2006-09-29 2009-12-08 Broadcom Corporation Memory management in a shared memory system
US7519780B2 (en) * 2006-11-03 2009-04-14 International Business Machines Corporation System and method for reducing store latency in symmetrical multiprocessor systems
EP2650794A1 (fr) 2010-12-06 2013-10-16 Fujitsu Limited Système de traitement d'informations et procédé de transmission d'informations
US10747298B2 (en) 2017-11-29 2020-08-18 Advanced Micro Devices, Inc. Dynamic interrupt rate control in computing system
US10503648B2 (en) 2017-12-12 2019-12-10 Advanced Micro Devices, Inc. Cache to cache data transfer acceleration techniques
US10452547B2 (en) * 2017-12-29 2019-10-22 Oracle International Corporation Fault-tolerant cache coherence over a lossy network
US11210246B2 (en) 2018-08-24 2021-12-28 Advanced Micro Devices, Inc. Probe interrupt delivery

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Also Published As

Publication number Publication date
JPH10187645A (ja) 1998-07-21
EP0817072A2 (fr) 1998-01-07
US5878268A (en) 1999-03-02

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