EP0806719B1 - Circuit for generating a voltage reference - Google Patents
Circuit for generating a voltage reference Download PDFInfo
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- EP0806719B1 EP0806719B1 EP97106833A EP97106833A EP0806719B1 EP 0806719 B1 EP0806719 B1 EP 0806719B1 EP 97106833 A EP97106833 A EP 97106833A EP 97106833 A EP97106833 A EP 97106833A EP 0806719 B1 EP0806719 B1 EP 0806719B1
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- 238000010079 rubber tapping Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/265—Current mirrors using bipolar transistors only
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Definitions
- the invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential connected and with a controlled power source, that between a supply potential and the output terminal is switched and the input side with the Collector of the third transistor is coupled.
- bandgap reference Such a circuit arrangement, also referred to as a bandgap reference is described in EP-A-0 411 657.
- a another bandgap reference is from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pp. 293-296.
- a bandgap reference is often used with integrated circuits used as internal reference voltage source.
- a frequency-compensated bandgap reference is also in GB 2 256 949 A.
- the object of the invention is to provide a circuit arrangement Specify the type mentioned, despite good noise behavior has short on and off times.
- the controlled current source has a circuit arrangement fourth transistor whose collector has the supply potential, its emitter with the output terminal and its Base connected to the collector of the third transistor is. Is between the base and collector of the fourth transistor switched another power source.
- the further current source can have a fifth transistor have its base with the output terminal and its emitter with the interposition of a fourth resistor is connected to the reference potential. Furthermore are a sixth transistor whose emitter is interposed a fifth resistor with the supply potential is connected, the collector of which is connected to the base of the fourth transistor is connected and its base with the Collector of the fifth transistor is coupled, as well as a seventh transistor, its base and collector together and coupled to the collector of the fifth transistor are and its emitter with the interposition of a sixth Resistance is connected to the supply potential, intended.
- the noise of the circuit arrangement according to the invention is further reduced.
- the noise of the others Current source has an influence especially at high frequencies on the noise behavior of the entire circuit arrangement. This is particularly annoying when the other Current source pnp transistors are used because of this the noise and the size of the parasitic capacitances are far from an ideal transistor.
- the inserted eighth resistor insulates especially at high Frequencies the not ideal working other power source and thus improves the noise behavior and the output resistance.
- the stability is improved because the effective capacity at the output of the further power source now not so much the phase reserve of the whole Circuit arrangement affects.
- the insertion of a series resistor is particularly recommended when realizing sixth and seventh transistor as pnp transistors on one Current output of the circuit arrangement.
- an npn transistor T1 is provided, whose emitter is connected to a reference potential M and whose base and collector are both interconnected as also via a common resistor R1 with a reference potential leading output terminal U are coupled.
- the base and collector of transistor T1 is the base of one npn transistor T2 connected, the emitter via a Resistor R3 with the reference potential M and its collector coupled to the output terminal U via a resistor R2 is.
- the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected.
- the basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.
- a capacitor C1 is connected in parallel with the resistor R2.
- the base of the transistor T4 is also a Resistor R8 and a current source circuit to the supply potential V connected.
- the current source circuit has a pnp transistor T6, its emitter via a resistor R5 with the supply potential V and its collector via resistor R8 the base of the transistor T4 or the collector of the transistor T3 is connected.
- the base of transistor T6 is connected to the base and collector of a pnp transistor T7, whose emitter via a resistor R6 with the supply potential V is coupled.
- Base and collector of the transistor T7 and the base of transistor T6 are above it also connected to the collector of an npn transistor T5, its emitter via a resistor R4 to the reference potential M is connected and its base with the output connection U is connected.
- an output connection I which carries a reference current. Is to the output terminal I with the collector of a pnp transistor T8 connected, the emitter via a resistor R7 is connected to the supply potential V and its base is connected to the bases of transistors T6 and T7.
- the dimensioning of the capacitor C1 depends on the respective application from, although here with higher capacities Noise behavior and, at lower capacities, the switch-on behavior becomes cheaper.
- the resistor R8 becomes like this chosen as large as possible to ensure the highest possible insulation guarantee.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Description
Die Erfindung betrifft eine Schaltungsanordnung zur Erzeugung eines Referenzpotentials mit einem ersten Transistor, dessen Emitter mit einem Bezugspotential verbunden ist und dessen Basis und Kollektor miteinander verschaltet sind, mit einem zweiten Transistor, dessen Basis mit der Basis des ersten Transistors verbunden ist, mit einem ersten Widerstand, der zwischen den Kollektor des ersten Transistors und einem Ausgangsanschluß zum Abgreifen des Referenzpotentials geschaltet ist, mit einem zweiten Widerstand, der zwischen den Kollektor des zweiten Transistors und den Ausgangsanschluß geschaltet ist, mit einem dritten Widerstand, der zwischen den Emitter des zweiten Transistors und das Bezugspotentials geschaltet ist, mit einem dritten Transistor, dessen Basis mit dem Kollektor des zweiten Transistors und dessen Emitter mit dem Bezugspotential verbunden ist, und mit einer gesteuerten Stromquelle, die zwischen ein Versorgungspotential und den Ausgangsanschluß geschaltet ist und die eingangsseitig mit dem Kollektor des dritten Transistors gekoppelt ist.The invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential connected and with a controlled power source, that between a supply potential and the output terminal is switched and the input side with the Collector of the third transistor is coupled.
Eine solche, auch als Bandgap-Referenz bezeichnete Schaltungsanordnung ist in der EP-A-0 411 657 beschrieben. Eine weitere Bandgap-Referenz ist aus Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, S.293-296 bekannt. Eine Bandgap-Referenz wird häufig bei integrierten Schaltkreisen als interne Referenzspannungsquelle verwendet. Eine frequenzkompensierte Bandgap-Referenz ist zudem in der GB 2 256 949 A beschrieben.Such a circuit arrangement, also referred to as a bandgap reference is described in EP-A-0 411 657. A another bandgap reference is from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pp. 293-296. A bandgap reference is often used with integrated circuits used as internal reference voltage source. A frequency-compensated bandgap reference is also in GB 2 256 949 A.
In Zukunft wird es bei integrierten Schaltkreisen zunehmend wichtiger, daß die Schaltkreise sich zum Zwecke der Stromersparnis über einen externen Anschluß ein- und ausschalten lassen. Das Ausschalten sollte dabei moglichst schnell erfolgen, um effektiv die Stromaufnahme und damit die Verlustleistung senken zu können. Ebenso sollte auch die Einschaltzeit möglichst klein gehalten werden, um den Schaltkreis binnen kürzester Zeit in den Arbeitszustand zu bringen. Ein weiteres wichtiges Kriterium von Schaltungsanordnungen zur Erzeugung eines Referenzpotentials ist das Rauschverhalten. Dies kann durch Kondensatoren zur Bandbegrenzung, die das Rauschen bei hohen Frequenzen wegfiltern, günstig beeinflußt werden. Jedoch steigen durch diese Maßnahmen die Ein- und Ausschaltzeiten des jeweiligen Schaltkreises an.In the future it will be increasingly with integrated circuits more importantly, that the circuits are for the purpose of saving electricity on and off via an external connection have it switched off. Switching off should be as possible done quickly to effectively draw power and thus the To be able to reduce power loss. Likewise, the Switch-on time should be kept as short as possible by Circuit in the shortest possible time in the working state bring. Another important criterion of circuit arrangements to generate a reference potential Noise behavior. This can be done with capacitors for band limitation, that filter out the noise at high frequencies, be influenced favorably. However, these measures increase the on and off times of the respective circuit on.
Aufgabe der Erfindung ist es, eine Schaltungsanordnung der eingangs genannten Art anzugeben, die trotz guten Rauschverhaltens kurze Ein- und Ausschaltzeiten aufweist.The object of the invention is to provide a circuit arrangement Specify the type mentioned, despite good noise behavior has short on and off times.
Die Aufgabe wird durch eine Schaltungsanordnung gemäß Patentanspruch 1 gelöst. Ausgestaltungen und Weiterbildungen des Erfindungsgedankens sind Gegenstand von Unteransprüchen.The object is achieved by a circuit arrangement according to claim 1 solved. Refinements and developments of the The concept of the invention is the subject of dependent claims.
Vorteilhaft ist, daß die günstigen Ein- und Ausschaltzeiten sowie das güngstige Rauschverhalten mit geringstem technischen Aufwand erreicht wird. Zu diesem Zweck wird eine Kapazität dem zweiten Widerstand parallel geschaltet. Gegenüber einer Kapazität, die beispielsweise zwischen Basis und Emitter des dritten Transistors geschaltet ist, kann der als Emitterfolger betriebene vierte Transistor mehr Strom liefern und verkürzt dadurch die Einschaltzeit. Der zur Kapazität parallel liegende zweite Widerstand trägt hingegen zur Verkürzung der Ausschaltzeit bei. Stabilität und Rauschverhalten bleiben dabei praktisch unverändert. Schließlich wird die Betriebsspannungsunterdrückung bei hohen Frequenzen verbessert. It is advantageous that the favorable on and off times as well as the most favorable noise behavior with the least technical Effort is achieved. For this purpose there is a capacity connected in parallel with the second resistor. Across from a capacitance between base and emitter, for example of the third transistor is connected, the Emitter follower operated fourth transistor deliver more current and thereby shortens the switch-on time. The one for capacity however, the second resistance lying in parallel helps to shorten it the switch-off time at. Stability and noise behavior remain practically unchanged. Eventually the operating voltage suppression improved at high frequencies.
Bei einer bevorzugten Ausgestaltung der erfindungsgemäßen Schaltungsanordnung weist die gesteuerte Stromquelle einen vierten Transistor auf, dessen Kollektor mit dem Versorgungspotential, dessen Emitter mit dem Ausgangsanschluß und dessen Basis mit dem Kollektor des dritten Transistors verbunden ist. Zwischen Basis und Kollektor des vierten Transistors ist dabei eine weitere Stromquelle geschaltet.In a preferred embodiment of the invention The controlled current source has a circuit arrangement fourth transistor whose collector has the supply potential, its emitter with the output terminal and its Base connected to the collector of the third transistor is. Is between the base and collector of the fourth transistor switched another power source.
Weiterhin kann die weitere Stromquelle einen fünften Transistor aufweisen, dessen Basis mit dem Ausgangsanschluß und dessen Emitter unter Zwischenschaltung eines vierten Widerstandes mit dem Bezugspotential verbunden ist. Des weiteren sind ein sechster Transistor, dessen Emitter unter Zwischenschaltung eines fünften Widerstandes mit dem Versorgungspotential verbunden ist, dessen Kollektor mit der Basis des vierten Transistors verschaltet ist und dessen Basis mit dem Kollektor des fünften Transistors gekoppelt ist, sowie ein siebter Transistor, dessen Basis und Kollektor miteinander sowie mit dem Kollektor des fünften Transistors gekoppelt sind und dessen Emitter unter Zwischenschaltung eines sechsten Widerstandes mit dem Versorgungspotential verbunden ist, vorgesehen.Furthermore, the further current source can have a fifth transistor have its base with the output terminal and its emitter with the interposition of a fourth resistor is connected to the reference potential. Furthermore are a sixth transistor whose emitter is interposed a fifth resistor with the supply potential is connected, the collector of which is connected to the base of the fourth transistor is connected and its base with the Collector of the fifth transistor is coupled, as well as a seventh transistor, its base and collector together and coupled to the collector of the fifth transistor are and its emitter with the interposition of a sixth Resistance is connected to the supply potential, intended.
Bei einer Weiterbildung der Erfindung ist in die Kollektorleitung des sechsten Transistors in Reihe zur weiteren Stromquelle ein achter Widerstand geschaltet. Dies hat den Vorteil, daß das Rauschen der erfindungsgemäßen Schaltungsanordnung weiter herabgesetzt wird. Das Rauschen der weiteren Stromquelle hat insbesondere bei hohen Frequenzen einen Einfluß auf das Rauschverhalten der gesamten Schaltungsanordnung. Dies stört vor allem auch dann, wenn bei der weiteren Stromquelle pnp-Transistoren verwendet werden, da diese hinsichtlich des Rauschens und der Größe der parasitären Kapazitäten weit von einem idealen Transistor entfernt sind. Der eingefügte achte Widerstand isoliert insbesondere bei hohen Frequenzen die nicht ideal arbeitende weitere Stromquelle und verbessert so das Rauschverhalten sowie den Ausgangswiderstand. Darüber hinaus wird die Stabilität verbessert, da die effektive Kapazität am Ausgang der weiteren Stromquelle nun nicht mehr in so starkem Maße die Phasenreserve der gesamten Schaltungsanordnung beeinflußt. Das Einfügen eines Serienwiderstandes empfiehlt sich insbesondere bei Realisierung von sechstem und siebtem Transistor als pnp-Transistoren an einem Stromausgang der Schaltungsanordnung.In a development of the invention is in the collector line of the sixth transistor in series with the further current source an eighth resistor switched. This has the advantage that the noise of the circuit arrangement according to the invention is further reduced. The noise of the others Current source has an influence especially at high frequencies on the noise behavior of the entire circuit arrangement. This is particularly annoying when the other Current source pnp transistors are used because of this the noise and the size of the parasitic capacitances are far from an ideal transistor. The inserted eighth resistor insulates especially at high Frequencies the not ideal working other power source and thus improves the noise behavior and the output resistance. In addition, the stability is improved because the effective capacity at the output of the further power source now not so much the phase reserve of the whole Circuit arrangement affects. The insertion of a series resistor is particularly recommended when realizing sixth and seventh transistor as pnp transistors on one Current output of the circuit arrangement.
Die Erfindung wird nachfolgend anhand des in der einzigen Figur der Zeichnung dargestellten Ausführungsbeispiels näher erläutert.The invention is illustrated below in the single figure the drawing shown embodiment closer explained.
Bei der als Ausführungsbeispiel gezeigten erfindungsgemäßen Schaltungsanordnung ist ein npn-Transistor T1 vorgesehen, dessen Emitter mit einem Bezugspotential M verbunden ist und dessen Basis und Kollektor sowohl miteinander verschaltet als auch über einen gemeinsamen Widerstand R1 mit einem ein Referenzpotential führenden Ausgangsanschluß U gekoppelt sind. An Basis und Kollektor des Transistors T1 ist die Basis eines npn-Transistors T2 angeschlossen, dessen Emitter über einen Widerstand R3 mit dem Bezugspotential M und dessen Kollektor über einen Widerstand R2 mit dem Ausgangsanschluß U gekoppelt ist.In the invention shown as an embodiment Circuit arrangement, an npn transistor T1 is provided, whose emitter is connected to a reference potential M and whose base and collector are both interconnected as also via a common resistor R1 with a reference potential leading output terminal U are coupled. On The base and collector of transistor T1 is the base of one npn transistor T2 connected, the emitter via a Resistor R3 with the reference potential M and its collector coupled to the output terminal U via a resistor R2 is.
An dem Ausgangsanschluß U ist darüber hinaus der Emitter eines npn-Transistors T4 angeschlossen, dessen Kollektor mit einem Versorgungspotential V verbunden ist. Die Basis des Transistors T4 ist mit dem Kollektor eines npn-Transistors T3 verbunden, dessen Emitter an das Bezugspotential M und dessen Basis an den Kollektor des Transistors T2 angeschlossen ist. Dem Widerstand R2 ist eine Kapazität C1 parallel geschaltet. At the output terminal U, the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected. The basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2. A capacitor C1 is connected in parallel with the resistor R2.
Die Basis des Transistors T4 ist darüber hinaus über einen Widerstand R8 sowie eine Stromquellenschaltung an das Versorgungspotential V angeschlossen.The base of the transistor T4 is also a Resistor R8 and a current source circuit to the supply potential V connected.
Die Stromquellenschaltung weist einen pnp-Transistor T6 auf, dessen Emitter über einen Widerstand R5 mit dem Versorgungspotential V und dessen Kollektor über den Widerstand R8 mit der Basis des Transistors T4 bzw. dem Kollektor des Transistors T3 verbunden ist. Die Basis des Transistors T6 ist mit Basis und Kollektor eines pnp-Transistors T7 verschaltet, dessen Emitter über einen Widerstand R6 mit dem Versorgungspotential V gekoppelt ist. Basis und Kollektor des Transistors T7 sowie die Basis des Transistors T6 sind darüber hinaus mit dem Kollektor eines npn-Transistors T5 verbunden, dessen Emitter über einen Widerstand R4 an das Bezugspotential M angeschlossen ist und dessen Basis mit dem Ausgangsanschluß U verbunden ist.The current source circuit has a pnp transistor T6, its emitter via a resistor R5 with the supply potential V and its collector via resistor R8 the base of the transistor T4 or the collector of the transistor T3 is connected. The base of transistor T6 is connected to the base and collector of a pnp transistor T7, whose emitter via a resistor R6 with the supply potential V is coupled. Base and collector of the transistor T7 and the base of transistor T6 are above it also connected to the collector of an npn transistor T5, its emitter via a resistor R4 to the reference potential M is connected and its base with the output connection U is connected.
Neben dem Ausgangsanschluß U, an dem das Referenzpotential abgreifbar ist, kann darüber hinaus ein Ausgangsanschluß I vorgesehen werden, der einen Referenzstrom führt. Dazu ist der Ausgangsanschluß I mit dem Kollektor eines pnp-Transistors T8 verbunden, dessen Emitter über einen Widerstand R7 mit dem Versorgungspotential V verbunden ist und dessen Basis mit den Basen der Transistoren T6 und T7 verschaltet ist.In addition to the output terminal U at which the reference potential can be tapped, an output connection I be provided, which carries a reference current. Is to the output terminal I with the collector of a pnp transistor T8 connected, the emitter via a resistor R7 is connected to the supply potential V and its base is connected to the bases of transistors T6 and T7.
Die Bemessung des Kondensators C1 hängt vom jeweiligen Anwendungsfall ab, wobei auch hier bei höheren Kapazitäten das Rauschverhalten und bei niedrigeren Kapazitäten das Einschaltverhalten günstiger wird. Der Widerstand R8 wird so groß wie möglich gewählt, um eine möglichst hohe Isolation zu gewährleisten.The dimensioning of the capacitor C1 depends on the respective application from, although here with higher capacities Noise behavior and, at lower capacities, the switch-on behavior becomes cheaper. The resistor R8 becomes like this chosen as large as possible to ensure the highest possible insulation guarantee.
Claims (2)
- Circuit arrangement for generating a reference potential,characterized in thathaving a first transistor (T1), whose emitter is connected to a reference-earth potential (M) and whose base and collector are connected up to one another,having a second transistor (T2), whose base is connected to the base of the first transistor (T1),having a first resistor (R1), which is connected between the collector of the first transistor (T1) and an output terminal (U) for tapping off the reference potential,having a second resistor (R2), which is connected between the collector of the second transistor (T2) and the output terminal (U),having a third resistor (R3), which is connected between the emitter of the second transistor (T2) and the reference-earth potential (M),having a third transistor (T3), whose base is connected to the collector of the second transistor (T2) and whose emitter is connected to the reference-earth potential (M), and having a controlled current source (T4), which is connected between a supply potential (V) and the output terminal (U) and, on the input side, is coupled to the collector of the third transistor (T3),a capacitance (C1) is provided, which is connected in parallel with the second resistor (R2), the controlled current source (T3, T4) has a fourth transistor (T4), whose collector is connected to the supply potential (V), whose emitter is connected to the output terminal (U) and whose base is connected to the collector of the third transistor (T3),a further current source (T5, T6, T7, R4, R5, R6) is connected between the base and collector of the fourth transistor (T4), andthe further current source (T5, T6, T7, R4, R5, R6) has:a fifth transistor (T5), whose base is connected to the output terminal (U) and whose emitter is connected to the reference-earth potential (M) with the interposition of a fourth resistor (R4),a sixth transistor (T6), whose emitter (T6) is connected to the supply potential (V) with the interposition of a fifth resistor (R5), whose collector is connected up to the base of the fourth transistor (T4), and whose base is coupled to the collector of the fifth transistor (T5),a seventh transistor (T7), whose base and collector are coupled to one another and also to the collector of the fifth transistor (T5) and whose emitter is connected to the supply potential (V) with the interposition of a sixth resistor (R6).
- Circuit arrangement according to Claim 1,
characterized in that an eighth resistor (R8) is connected in series with the further current source (T6, T7).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19618914A DE19618914C1 (en) | 1996-05-10 | 1996-05-10 | Reference potential generator for analog integrated circuits |
| DE19618914 | 1996-05-10 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0806719A2 EP0806719A2 (en) | 1997-11-12 |
| EP0806719A3 EP0806719A3 (en) | 1998-09-16 |
| EP0806719B1 true EP0806719B1 (en) | 2001-08-01 |
Family
ID=7793979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP97106833A Expired - Lifetime EP0806719B1 (en) | 1996-05-10 | 1997-04-24 | Circuit for generating a voltage reference |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5883543A (en) |
| EP (1) | EP0806719B1 (en) |
| DE (2) | DE19618914C1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002008708A1 (en) * | 2000-07-26 | 2002-01-31 | Stmicroelectronics Asia Pacifc Pte Ltd | A thermal sensor circuit |
| DE10357772A1 (en) * | 2003-12-10 | 2005-07-14 | Siemens Ag | Control unit as for an oil level sensor in a motor vehicle comprises current mirror whose output current governs the voltage drop over a sensor resistance |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4553083A (en) * | 1983-12-01 | 1985-11-12 | Advanced Micro Devices, Inc. | Bandgap reference voltage generator with VCC compensation |
| JPS60229125A (en) * | 1984-04-26 | 1985-11-14 | Toshiba Corp | Voltage output circuit |
| US5028527A (en) * | 1988-02-22 | 1991-07-02 | Applied Bio Technology | Monoclonal antibodies against activated ras proteins with amino acid mutations at position 13 of the protein |
| JPH0680486B2 (en) * | 1989-08-03 | 1994-10-12 | 株式会社東芝 | Constant voltage circuit |
| US5029295A (en) * | 1990-07-02 | 1991-07-02 | Motorola, Inc. | Bandgap voltage reference using a power supply independent current source |
| KR930001577A (en) * | 1991-06-19 | 1993-01-16 | 김광호 | Reference voltage generator |
| JP2953226B2 (en) * | 1992-12-11 | 1999-09-27 | 株式会社デンソー | Reference voltage generation circuit |
| US5757224A (en) * | 1996-04-26 | 1998-05-26 | Caterpillar Inc. | Current mirror correction circuitry |
-
1996
- 1996-05-10 DE DE19618914A patent/DE19618914C1/en not_active Expired - Fee Related
-
1997
- 1997-04-24 EP EP97106833A patent/EP0806719B1/en not_active Expired - Lifetime
- 1997-04-24 DE DE59704169T patent/DE59704169D1/en not_active Expired - Lifetime
- 1997-05-12 US US08/855,842 patent/US5883543A/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| BIRRITTELLA M S ET AL: "DESIGN TECHNIQUES FOR IC VOLTAGE REGULATORS WITHOUT P-N-P TRANSISTORS" IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK, NY, US, Bd. 22, Nr. 1, Februar 1987. * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0806719A2 (en) | 1997-11-12 |
| DE59704169D1 (en) | 2001-09-06 |
| US5883543A (en) | 1999-03-16 |
| EP0806719A3 (en) | 1998-09-16 |
| DE19618914C1 (en) | 1997-08-14 |
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