Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0877—Cache access modes
  • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Definitions

• the present invention relates to pipelined microprocessors and, more particularly, to a pipelined microprocessor that makes memory requests to a cache memory and an external memory controller during the same clock cycle when the system bus that connects an external memory to the processor is available.
• a pipelined microprocessor is a microprocessor that operates on instructions in stages so that, at each stage of the pipeline, a different function is performed on an instruction. As a result, multiple instructions move through the pipe at the same time much like to-be-assembled products move through a multistage assembly line.
• FIG. 1 shows a block diagram that illustrates the flow of an instruction through a conventional pipelined processor.
• the first stage in the pipe is a prefetch stage.
• the to-be-executed instructions are retrieved from either a cache memory or an external memory, and are then sequentially loaded into a prefetch buffer.
• the purpose of the prefetch stage is to fill the prefetch buffer so that one instruction can be advanced to the decode stage, the next stage in the pipe, with each clock cycle.
• each instruction moving through the pipe is decoded to determine what operation is to be performed.
• an operand stage determines if data will be needed to perform the operation and, if needed, retrieves the data from either one of several data registers, a data cache memory, or the external memory.
• the operation specified by the instruction is performed in an execution stage, while the results of the operation are stored in a write-back stage.
• each instruction is advanced from one stage to the next with each successive clock cycle.
• the processor appears to complete the execution of each instruction in only one clock cycle.
• the branch instruction With the branch instruction, the next instruction to be executed is determined by the outcome of the operation.
• the pipeline continues to function as described above. However, if the outcome of the operation requires an instruction not currently in the pipe, then the instructions in the prefetch, decode, and operand stages must be flushed from the pipeline and replaced by the alternate instructions required by the branch condition.
• DRAM dynamic random-access-controller
• One problem with this approach is that when the needed instruction is not stored in the cache memory, the processor must waste at least one clock cycle to establish this fact.
• One solution to this problem is to simply increase the size of the cache memory, thereby increasing the likelihood that the needed instruction will be stored in the cache memory.
• a memory request is first made to a cache memory and then, if the request is not stored in the cache memory, to an external memory.
• several clock cycles can be lost by first accessing the cache memory rather than the external memory.
• these lost clock cycles are eliminated by utilizing a dual memory access circuit that makes a memory request to both the cache memory and an external memory controller during the same clock cycle when the bus that connects the external memory to the processor is available.
• the cycle time lost when the request is not stored in the cache memory can be eliminated.
• the unneeded external memory requests that result each time the request is stored in the cache memory are eliminated by gating the request to the external memory controller with a logic signal output by the cache memory that indicates whether the request is present.
• a dual memory access circuit in accordance with the present invention includes a memory access controller that monitors the availability of a system bus, and that outputs a first request in response to needed information when the system bus is unavailable. On the other hand, when the system bus is available, the memory access controller outputs the first request and a second request in response to the needed information. In addition, when both the first and second requests are output, the memory access controller also asserts a dual request signal.
• the dual memory access circuit further includes a cache controller that determines whether the needed information is stored in the cache memory and, if the needed information is found and the dual request signal is asserted, asserts a terminate request signal. An external memory controller gates the second request and the terminate request signal so that when the terminate request signal is asserted, the second request is gated out, and so that when the terminate request signal is deasserted, the second request signal is latched by the external memory controller.
• FIG. 1 is a block diagram illustrating the flow of an instruction through a conventional pipelined processor.
• FIG. 2 is a block diagram illustrating a dual memory access circuit 100 in accordance with the present invention.
• FIG. 3 is a block diagram illustrating the operation of cache memory 120 and cache controller 130.
• FIG. 4 is a timing diagram illustrating the dual memory request.
• FIG. 5 is a block diagram illustrating the operation of DRAM controller 140.
• DETAILED DESCRIPTION FIG. 2 shows a block diagram of a dual memory access circuit 100 in accordance with the present invention.
• circuit 100 includes a memory access controller 110 that controls memory requests to a cache memory 120 and an external memory to obtain instructions requested by the prefetch and execution stages of a pipelined microprocessor. Both cache memory 120 and the external memory, in turn, supply the requested instructions back to the prefetch stage of the microprocessor.
• an eight-bit word is output by cache memory 120 whereas a 16-bit word is output by the external memory.
• a prefetch buffer stores the next sequence of instructions to be decoded.
• Memory access controller 110 monitors the status of the prefetch buffer and, when the prefetch buffer is less than full, requests the next instruction in the sequence from memory.
• memory access controller 110 determines which memory the request will be directed to in response to the status of the system bus that connects the external memory to the processor.
• memory access controller 110 requests the next instruction from cache memory 120 by outputting a requested address RADl, as defined by a prefetch instruction pointer, to a cache controller 130.
• Cache controller 130 determines whether the requested address RADl is stored in cache memory 120 by comparing the requested address RADl to the address tags stored in cache memory 120.
• FIG. 3 shows a block diagram that illustrates the operation of cache memory 120 and cache controller 130. As shown in FIG.
• cache memory 120 which is configured as a direct-mapped memory, includes a data RAM 122 that stores eight bytes of data in each line of memory (the number of bytes per line is arbitrary), and a tag RAM 124 that stores tag fields which identify the page of memory to which each line of memory corresponds.
• a valid bit RAM 126 indicates whether the information stored in data RAM 122 is valid.
• the requested address RADl output from memory access controller 110 includes a page field that identifies the page of memory, a line field that identifies the line of the page, and a "don't care" byte position field.
• cache controller 130 utilizes the line field of the requested address RADl to identify the corresponding page field stored in tag RAM 124.
• the page field from tag RAM 124 is then compared to the page field of the requested address RADl to determine if the page fields match. If the page fields match and the corresponding bit in valid bit RAM 125 indicates that the information is valid, cache controller 130 asserts a cache hit signal CHS, which indicates a match, while cache memory 120 outputs the instruction associated with the requested address RADl. If, on the other hand, the page fields do not match, thereby indicating that the requested address RADl is not stored in cache memory 120, then the instruction associated with the requested address RADl must be retrieved from the external memory.
• memory access controller 110 requests the next instruction from both cache memory 120 and the external memory during the same clock cycle. (In the FIG. 2 embodiment, the request is also output to an external bus controller which controls, among other things, the read-only-memory (ROM) and the disk drives). Controller 110 initiates the requests by outputting the requested address RADl to cache controller 130 while also outputting a requested address RAD2 to a dynamic random access memory (DRAM) controller 140. In most cases, the requested addresses RADl and RAD2 will be identical but may differ as required by the addressing scheme being utilized.
• DRAM dynamic random access memory
• FIG. 4 shows a timing diagram that illustrates the dual memory request.
• memory access controller 110 also asserts a dual address signal DAS which indicates that requests are going to both memories, and a bus request signal BRS which indicates that the requested address RAD2 is valid.
• DAS dual address signal
• BRS bus request signal
• cache controller 130 when cache controller 130 matches the requested address RADl with one of the address tags while the dual address signal DAS is asserted, cache controller 130 asserts a terminate address signal TAS at approximately the same time that the cache hit signal CHS is asserted. (See FIG. 3).
• DRAM controller 140 gates the bus request signal BRS with the terminate address signal TAS to determine whether the external memory request should continue.
• FIG. 5 shows a block diagram that illustrates the operation of DRAM controller 140. As shown in FIG. 5, when the terminate address signal TAS is asserted, the bus request signal
• BRS is gated out, thereby terminating the memory request made to the external memory.
• the terminate address signal TAS is deasserted
• the second requested address RAD2 is latched by DRAM controller 140 on the falling edge of the same system clock cycle that initiated the requested addresses RADl and RAD2.
• Cache controller 130 deasserts the cache hit signal CHS and the terminate address signal TAS when cache controller 130 determines that the requested address RADl does not match any of the address tags, i.e., the page fields do not match.
• the present invention also follows the same approach with respect to instructions requested by the execution stage.
• the outcome of a branch instruction frequently calls for an instruction which is not in the pipeline.
• memory access controller 110 must request the instruction from either cache memory 120 or the external memory.
• memory access controller 110 when the system bus is available, memory access controller 110 asserts the dual address signal DAS and the bus request signal BRS, and outputs the requested addresses RADl and RAD2 to cache controller 130 and DRAM controller 140, respectively. On the other hand, if the system bus is unavailable, memory access controller 1 10 only outputs the requested address RADl to cache controller 130.
• the advantage of simultaneously requesting the next instruction from both cache controller 130 and DRAM controller 140 when the bus is available is that each time the next instruction is absent from cache memory 120, the present invention saves the wasted clock cycle that is required to first check cache memory 120. This, in turn, improves the performance of the processor. If, on the other hand, the system bus is unavailable, memory access controller 110 must wait at least one clock cycle to access the system bus in any case. Thus, no cycle time can be saved when the bus is unavailable. As a result, controller 110 only outputs the requested address RADl to cache controller 130 when the bus is unavailable.
• Terminating the bus request signal BRS when cache controller 130 determines that the page fields match also has the added advantage of decreasing the bus utilization by the processor. If the bus request signal BRS was not terminated each time the page fields match, the system bus would be tied up servicing an unneeded request, thereby limiting the utilization of the bus. In addition, the logic within the memory access controller 110 would have to be configured to wait for the unneeded instruction to return from the DRAM. Further, terminating the bus request signal BRS when cache controller 130 determines that the page fields match has the additional advantage of maintaining the page hit registers stored in DRAM controller 140. When a DRAM is accessed by DRAM controller 140, the address is divided into a row address which defines a page of memory, and a column address which defines the individual bytes stored in the page.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Advance Control (AREA)
• Memory System Of A Hierarchy Structure (AREA)

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• 1996
  • 1996-05-16 KR KR1019970700548A patent/KR970705086A/ko not_active Application Discontinuation
  • 1996-05-16 EP EP96920253A patent/EP0772829A1/de not_active Withdrawn
  • 1996-05-16 WO PCT/US1996/007091 patent/WO1996037844A1/en not_active Application Discontinuation

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