EP0766163B1 - Circuit for generating a bias voltage - Google Patents

Circuit for generating a bias voltage Download PDF

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Publication number
EP0766163B1
EP0766163B1 EP96114180A EP96114180A EP0766163B1 EP 0766163 B1 EP0766163 B1 EP 0766163B1 EP 96114180 A EP96114180 A EP 96114180A EP 96114180 A EP96114180 A EP 96114180A EP 0766163 B1 EP0766163 B1 EP 0766163B1
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EP
European Patent Office
Prior art keywords
transistor
emitter
collector
base
potential
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EP96114180A
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German (de)
French (fr)
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EP0766163A2 (en
EP0766163A3 (en
Inventor
Wilhelm Dr. Wilhelm
Josef Hölzle
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • the invention relates to a circuit arrangement for generation a bias potential as in document EP-A-375998 is known.
  • bias potentials are necessary Influence of the supply voltage on the function of the circuit prevent.
  • the bias potentials should be with regard to the application in a bipolar circuit also in bipolar circuit technology can be generated. With such a bias potential independent of the supply voltage both digital and analog circuits can be implemented, those with higher as well as with lower supply voltages can be operated.
  • the object of the invention is to provide a circuit arrangement for Generation of an independent of the supply voltage Specify bias potential, even at low supply voltages can be operated.
  • a transistor 2 is provided, the collector of which is connected to a Supply potential 1 is connected. Between base and A transistor 3 is connected to the collector of transistor 2. The base of transistor 2 is also via a current source 5 connected to a reference potential 4. A power source 6 is between the emitter of transistor 2 and the reference potential 4 switched. A transistor 7 whose collector is on the supply potential 1 is connected is on the base side connected to the emitter of transistor 2. The emitter of the Transistor 7 is connected to the reference potential via a current source 8 4 coupled. Furthermore, a transistor 9 is provided the base of which is connected to the emitter via a resistor 10 of the transistor 7 and its emitter via a resistor 11 is connected to the supply potential 1.
  • the basis of the Transistor 9 is also a resistor 27 and a Diode 12 connected in series with this in the forward direction coupled to the reference potential 4.
  • the transistor 9 has two emitters, each via a resistor 13 or 13 'are connected to the reference potential 4.
  • the Resistors 10, 11, 13, 13 'and 27 are all the same Resistance value.
  • the two resistors 13 and 13 ' also by a single resistance with one against it half resistance value to be replaced if the Transistor 9 has only one emitter.
  • that is Design with two emitters and the associated resistors cheaper in terms of specimen scatter.
  • all the resistors 10, 11, 13, 13 ' have the same Resistance value on what in integrated circuit technology is much easier and more precise to implement than certain resistance relationships.
  • the resistor 27 can also have the same resistance value, but can possibly also to adapt the diode 12 to the base-emitter path of the transistor 9 can be changed and, if necessary completely eliminated.
  • To the base of transistor 14 is on the one hand the emitter of a transistor 15, the collector is connected to the supply potential 1, and another the collector of a transistor 16, whose emitter is connected to the reference potential 4, connected.
  • the base of transistor 15 is on the one hand via the series connection two diodes 17 and 18 in the forward direction with the Reference potential 4 coupled and on the other hand via a Resistor 20 connected to an auxiliary potential 19.
  • the base of transistor 16 is connected to the terminal connected to the diode 12 facing away from the reference potential 4 is.
  • current source 8 is, however in different ways - from the supply voltage dependent.
  • the current source 8 contains the Invention a transistor 21 in which between the collector and Emitter a diode 22 is switched in the forward direction, the emitter of transistor 21 being connected to reference potential 4 and the collector with the interposition of a resistor 23 is connected to the auxiliary potential 19.
  • the collector transistor 21 is also the base of a transistor 24 connected, whose emitter with the reference potential 4 and its collector with the emitter of transistor 7 is connected.
  • the base of transistor 21 is the same Way as the base of the transistor 16 at the the reference potential 4 connected terminal of the diode 12 connected.
  • a transistor 26 is used to generate the auxiliary potential 19 provided, at whose emitter the auxiliary potential 19 can be tapped is.
  • the base of transistor 26, whose collector is on the supply potential 1 is connected to the a bias potential 25 leading collector of the transistor 9 connected.
  • the current source 5 is preferred as a bandgap current source executed.
  • this consists of a Transistor 31, whose emitter with the reference potential 4 and whose collector with the interposition of a diode 29 in Forward direction connected to the base of a transistor 30 is.
  • the base of transistor 30, the collector of which Base of the transistor 2 is connected, is also via a Resistor 28 connected to supply potential 1.
  • the emitter of transistor 30 is one with the collector several, for example two coupled emitters having transistor 32 connected, the two coupled emitter of transistor 32 via a Resistor 33 are connected to the reference potential 4.
  • the bases of the transistors 31 and 32 are with the Collector of the other transistor connected.
  • a current that is dependent on the difference between the supply potential 1 and the desired bias potential 25 is formed according to the invention and is intended to feed the resistor 11 connected to the supply potential 1.
  • the desired value U for the bias potential 25 lies here for example around 3 volts.
  • the current source 5 as Bandgap current source provides a current with a positive temperature response. This is done together with the base-emitter path of the transistor 2 between the supply potential 1 and the emitter of transistor 2 a temperature independent Band gap voltage of about 1.2 volts is formed.
  • the following Transistors 7 and 9 add two base-emitter paths of about 0.9 volts, so that about 3 volts can be achieved. But since the transistors 7 and 9 depending on Supply voltage a different collector current consequently lead to the effect of the supply voltage these currents can still be eliminated.
  • FIG. 2 The application of a circuit arrangement according to the invention to a logic circuit, in particular a memory element, is shown in FIG. 2.
  • the bias potential 25 generated by the circuit arrangement 34 according to FIG. 1 is applied to the base of a transistor 35, the collector of which is connected to the supply potential 1 and the emitter of which is connected to the reference potential 4 with the interposition of a resistor 36.
  • the base of a transistor 37 is connected to the emitter of the transistor 35, the collector of which is connected to the supply potential 1 and the emitter is connected to the reference potential via a resistor 38.
  • a voltage drops across the resistor 38, which is equal to the voltage between the collector and emitter of the transistor 2 from FIG. 1.
  • the base of a transistor 39 is connected to the emitter of transistor 37, the emitter of which is coupled to reference potential 4 with the interposition of a resistor 40.
  • the collector of the transistor 39 is connected to the emitters of two transistors 41 and 42, at the bases of which a clock signal 43 or an inverted clock signal 43 are created.
  • the collector of transistor 41 is connected to the emitters of two transistors 44 and 45, at the bases of which a data signal 46 or an inverted data signal 46 are created.
  • the collector of transistor 42 is connected in the same way to the emitters of two transistors 47 and 48, the base of transistor 47 being connected to the collector of transistor 45 and the base of transistor 48 being connected to the collector of transistor 44.
  • collectors of transistors 44 and 47 are an inverted output signal 49 coupled with each other and with the interposition of a resistor 50 with the supply potential 1.
  • collectors of transistors 45 and 48 are connected to each other in an output signal 49 and connected to supply potential 1 via a resistor 51.
  • the application of the circuit arrangement 34 according to the invention from FIG. 1 to a driver circuit is shown in FIG.
  • the bias potential 25 generated by the circuit arrangement 34 is applied to the base of a transistor 52, the collector of which is connected to the supply potential 1.
  • the emitter of the transistor 52 is connected on the one hand via a resistor 53 to the base of a transistor 55 which forms a signal input 54 and on the other hand via a resistor 56 to the base of a transistor 58 which forms an inverting signal input 57.
  • the emitters of the transistors 55 and 58, the collectors of which are connected to the supply potential 1 are coupled to the reference potential 4 with the interposition of a resistor 59 and 60, respectively.
  • the base of a transistor 61 or 62 is connected to the emitters of transistors 55 and 58, the emitters of which are coupled to one another and connected to reference potential 4 via a resistor 63.
  • the collectors of transistors 61 and 62 are an output signal 64 and an inverting output signal, respectively 64 leading connected to the supply potential 1 via a respective resistor 65 or 66.
  • Figure 4 shows the application of a circuit arrangement according to the invention 34 for a linear amplifier. That from the Circuit arrangement 34 generated bias potential 25 the base of a transistor 67 and the collector of one Transistor 68 fed. The base of transistor 68, whose emitter is connected to the reference potential 4, forms a signal input 69. The base of transistor 68 is also for feedback purposes Series connection of two resistors 70 and 71 with the emitter of the collector side connected to supply potential 1 Transistor 67 coupled. The tap between the two resistors 70 and 71 is via a capacitor 74 out against the reference potential 4. After all, is one Resistor 72 between the emitter forming an output 73 of transistor 67 and the reference potential 4 switched. The Gain of the amplifier circuit results from the Ratio of the over the load path of the transistor 2 Figure 1 falling voltage to thermal voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
  • Logic Circuits (AREA)

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Erzeugung eines Biaspotentials wie aus dem Dokument EP-A-375998 bekannt ist.The invention relates to a circuit arrangement for generation a bias potential as in document EP-A-375998 is known.

Bisher lagen Versorgungsspannungen für integrierte Logikschaltungen meist im Bereich um 5 Volt. So benötigen CMOS-Schaltungen und TTL-Schaltungen beispielsweise 5,0 Volt und ECL-Schaltungen entweder 4,5 Volt oder 5,2 Volt. Moderne CMOS-Bausteine benötigen dagegen nur noch 3,3 Volt als Versorgungsspannung und werden in Zukunft die bisherigen Schaltungen mit einer Versorgungsspannung von 5 Volt ersetzen. Es ist daher wünschenswert, auch künftige bipolare Schaltungen ebenfalls mit einer Versorgungsspannung von 3,3 Volt betreiben zu können. Noch günstiger ist es, wenn die bipolaren Schaltungen beispielsweise in einem Spannungsbereich von 3 bis 6 Volt ohne Änderung der Beschaltung einsetzbar wären, da damit die Schaltung an jede gerade zur Verfügung stehende Spannungsquelle angeschlossen werden kann.So far there were supply voltages for integrated logic circuits mostly around 5 volts. So need CMOS circuits and TTL circuits, for example, 5.0 volts and ECL circuits either 4.5 volts or 5.2 volts. Modern CMOS devices, on the other hand, only need 3.3 volts as the supply voltage and will be the previous circuits in the future replace with a supply voltage of 5 volts. It is therefore desirable, also future bipolar circuits also operate with a supply voltage of 3.3 volts to be able to. It is even cheaper if the bipolar Circuits in a voltage range of 3, for example up to 6 volts could be used without changing the wiring, because so that the circuit to everyone currently available Power source can be connected.

Zu diesem Zweck sind Biaspotentiale notwendig, die einen Einfluß der Versorgungsspannung auf die Funktion der Schaltung verhindern. Die Biaspotentiale sollten im Hinblick auf die Anwendung in einer bipolaren Schaltung ebenfalls in bipolarer Schaltungstechnik erzeugt werden. Mit einem derart von der Versorgungsspannung unabhängigen Biaspotential ließen sich sowohl digitale als auch analoge Schaltungen realisieren, die bei höheren ebenso wie bei niedrigeren Versorgungsspannungen betrieben werden können.For this purpose bias potentials are necessary Influence of the supply voltage on the function of the circuit prevent. The bias potentials should be with regard to the application in a bipolar circuit also in bipolar circuit technology can be generated. With such a bias potential independent of the supply voltage both digital and analog circuits can be implemented, those with higher as well as with lower supply voltages can be operated.

Aufgabe der Erfindung ist es, eine Schaltungsanordnung zur Erzeugung eines von der Versorgungsspannung unabhängigen Biaspotentials anzugeben, die auch bei niedrigen Versorgungsspannungen betrieben werden kann. The object of the invention is to provide a circuit arrangement for Generation of an independent of the supply voltage Specify bias potential, even at low supply voltages can be operated.

Die Aufgabe wird gelöst durch eine Schaltungsanordnung gemäß Patentanspruch 1. Ausgestaltungen und Weiterbildungen des Erfindungsgedankens sind Gegenstand von Unteransprüchen.The object is achieved by a circuit arrangement according to Claim 1. Refinements and developments of The concept of the invention is the subject of dependent claims.

Die Erfindung wird nachfolgend anhand der in den Figuren der Zeichnung dargestellten Ausführungs- und Anwendungsbeispiele näher erläutert. Es zeigt:

Figur 1
ein Ausführungsbeispiel einer erfindungsgemäßen Schaltungsanordnung,
Figur 2
eine Anwendung der Schaltungsanordnung nach Figur 1 bei einer Logikschaltung,
Figur 3
eine Anwendung der Schaltungsanordnung nach Figur 1 bei einer Treiberschaltung und
Figur 4
die Anwendung der Schaltungsanordnung nach Figur 1 bei einer Verstärkerschaltung.
The invention is explained in more detail below with reference to the exemplary embodiments and application examples shown in the figures of the drawing. It shows:
Figure 1
an embodiment of a circuit arrangement according to the invention,
Figure 2
1 an application of the circuit arrangement according to FIG. 1 in a logic circuit,
Figure 3
an application of the circuit arrangement of Figure 1 in a driver circuit and
Figure 4
the application of the circuit arrangement according to Figure 1 in an amplifier circuit.

Bei der erfindungsgemäßen Schaltungsanordnung nach Figur 1 ist ein Transistor 2 vorgesehen, dessen Kollektor an ein Versorgungspotential 1 angeschlossen ist. Zwischen Basis und Kollektor des Transistors 2 ist ein Widerstand 3 geschaltet. Die Basis des Transistors 2 ist zudem über eine Stromquelle 5 an ein Bezugspotential 4 angeschlossen. Eine Stromquelle 6 ist zwischen den Emitter des Transistors 2 und das Bezugspotential 4 geschaltet. Ein Transistor 7, dessen Kollektor an das Versorgungspotential 1 angeschlossen ist, ist basisseitig mit dem Emitter des Transistors 2 verbunden. Der Emitter des Transistors 7 ist über eine Stromquelle 8 mit dem Bezugspotential 4 gekoppelt. Weiterhin ist ein Transistor 9 vorgesehen, dessen Basis über einen Widerstand 10 mit dem Emitter des Transistors 7 und dessen Emitter über einen Widerstand 11 mit dem Versorgungspotential 1 verbunden ist. Die Basis des Transistors 9 ist zudem über einen Widerstand 27 sowie eine seriell dazu in Reihe geschaltete Diode 12 in Durchlaßrichtung mit dem Bezugspotential 4 gekoppelt. Der Transistor 9 weist zwei Emitter auf, die jeweils über einen Widerstand 13 bzw. 13' an das Bezugspotential 4 angeschlossen sind. Die Widerstände 10, 11, 13, 13' und 27 haben alle den gleichen Widerstandswert. Alternativ können die beiden Widerstände 13 und 13' auch durch einen einzigen Widerstand mit einem demgegenüber halben Widerstandswert ersetzt werden, wenn der Transistor 9 nur einen Emitter aufweist. Jedoch ist die Ausgestaltung mit zwei Emittern und den zugehörigen Widerständen günstiger hinsichtlich Exemplarstreuungen. In dem Fall weisen alle die Widerstände 10, 11, 13, 13' den gleichen Widerstandswert auf, was in integrierter Schaltungstechnik wesentlich einfacher und genauer zu realisieren ist als bestimmte Widerstandsverhältnisse. Der Widerstand 27 kann ebenfalls den gleichen Widerstandswert aufweisen, kann aber unter Umständen auch zur Anpassung der Diode 12 an die Basis-Emitter-Strecke des Transistors 9 verändert werden und gegebenenfalls ganz entfallen.In the circuit arrangement according to the invention according to FIG. 1 a transistor 2 is provided, the collector of which is connected to a Supply potential 1 is connected. Between base and A transistor 3 is connected to the collector of transistor 2. The base of transistor 2 is also via a current source 5 connected to a reference potential 4. A power source 6 is between the emitter of transistor 2 and the reference potential 4 switched. A transistor 7 whose collector is on the supply potential 1 is connected is on the base side connected to the emitter of transistor 2. The emitter of the Transistor 7 is connected to the reference potential via a current source 8 4 coupled. Furthermore, a transistor 9 is provided the base of which is connected to the emitter via a resistor 10 of the transistor 7 and its emitter via a resistor 11 is connected to the supply potential 1. The basis of the Transistor 9 is also a resistor 27 and a Diode 12 connected in series with this in the forward direction coupled to the reference potential 4. The transistor 9 has two emitters, each via a resistor 13 or 13 'are connected to the reference potential 4. The Resistors 10, 11, 13, 13 'and 27 are all the same Resistance value. Alternatively, the two resistors 13 and 13 'also by a single resistance with one against it half resistance value to be replaced if the Transistor 9 has only one emitter. However, that is Design with two emitters and the associated resistors cheaper in terms of specimen scatter. By doing In this case, all the resistors 10, 11, 13, 13 'have the same Resistance value on what in integrated circuit technology is much easier and more precise to implement than certain resistance relationships. The resistor 27 can also have the same resistance value, but can possibly also to adapt the diode 12 to the base-emitter path of the transistor 9 can be changed and, if necessary completely eliminated.

Die Stromquelle 6, deren Strom von der zwischen dem Bezugspotential 4 und dem Versorgungspotential 1 auftretenden Versorgungsspannung abhängig ist, weist bei einer Weiterbildung der Erfindung einen Transistor 14 auf, dessen Emitter mit dem Bezugspotential 4 und dessen Kollektor mit dem Emitter des Transistors 2 verbunden ist. An die Basis des Transistors 14 ist zum einen der Emitter eines Transistors 15, dessen Kollektor mit dem Versorgungspotential 1 verbunden ist, und zum anderen der Kollektor eines Transistors 16, dessen Emitter mit dem Bezugspotential 4 verbunden ist, angeschlossen. Die Basis des Transistors 15 ist einerseits über die Reihenschaltung zweier Dioden 17 und 18 in Durchlaßrichtung mit dem Bezugspotential 4 gekoppelt und andererseits über einen Widerstand 20 an ein Hilfspotential 19 angeschlossen. Schließlich ist die Basis des Transistors 16 mit dem Anschluß der Diode 12 verbunden, der dem Bezugspotential 4 abgewandt ist.The current source 6, whose current is different from that between the reference potential 4 and the supply potential 1 occurring supply voltage is dependent on further training Invention a transistor 14, the emitter with the Reference potential 4 and its collector with the emitter of Transistor 2 is connected. To the base of transistor 14 is on the one hand the emitter of a transistor 15, the collector is connected to the supply potential 1, and another the collector of a transistor 16, whose emitter is connected to the reference potential 4, connected. The The base of transistor 15 is on the one hand via the series connection two diodes 17 and 18 in the forward direction with the Reference potential 4 coupled and on the other hand via a Resistor 20 connected to an auxiliary potential 19. Finally, the base of transistor 16 is connected to the terminal connected to the diode 12 facing away from the reference potential 4 is.

Wie die Stromquelle 6 ist auch die Stromquelle 8 -allerdings in unterschiedlicher Weise- von der Versorgungsspannung abhängig. Die Stromquelle 8 enthält in Weiterbildung der Erfindung einen Transistor 21, bei dem zwischen Kollektor und Emitter eine Diode 22 in Durchlaßrichtung geschaltet ist, wobei der Emitter des Transistors 21 an das Bezugspotential 4 und der Kollektor unter Zwischenschaltung eines Widerstandes 23 an das Hilfspotential 19 angeschlossen ist. Mit dem Kollektor des Transistors 21 ist zudem die Basis eines Transistors 24 verbunden, dessen Emitter mit dem Bezugspotential 4 und dessen Kollektor mit dem Emitter des Transistors 7 verschaltet ist. Die Basis des Transistors 21 ist in gleicher Weise wie die Basis des Transistors 16 an dem dem Bezugspotential 4 abgewandten Anschluß der Diode 12 angeschlossen.Like current source 6, current source 8 is, however in different ways - from the supply voltage dependent. In a further development, the current source 8 contains the Invention a transistor 21 in which between the collector and Emitter a diode 22 is switched in the forward direction, the emitter of transistor 21 being connected to reference potential 4 and the collector with the interposition of a resistor 23 is connected to the auxiliary potential 19. With the collector transistor 21 is also the base of a transistor 24 connected, whose emitter with the reference potential 4 and its collector with the emitter of transistor 7 is connected. The base of transistor 21 is the same Way as the base of the transistor 16 at the the reference potential 4 connected terminal of the diode 12 connected.

Zur Erzeugung des Hilfspotentials 19 ist ein Transistor 26 vorgesehen, an dessen Emitter das Hilfspotential 19 abgreifbar ist. Die Basis des Transistors 26, dessen Kollektor an das Versorgungspotentials 1 angeschlossen ist, ist mit dem ein Biaspotential 25 führenden Kollektor des Transistors 9 verbunden.A transistor 26 is used to generate the auxiliary potential 19 provided, at whose emitter the auxiliary potential 19 can be tapped is. The base of transistor 26, whose collector is on the supply potential 1 is connected to the a bias potential 25 leading collector of the transistor 9 connected.

Bevorzugt wird die Stromquelle 5 als Bandgap-Stromquelle ausgeführt. Diese besteht beim Ausführungsbeispiel aus einem Transistor 31, dessen Emitter mit dem Bezugspotential 4 und dessen Kollektor unter Zwischenschaltung einer Diode 29 in Durchlaßrichtung mit der Basis eines Transistors 30 verbunden ist. Die Basis des Transistors 30, dessen Kollektor mit der Basis des Transistors 2 verbunden ist, ist zudem über einen Widerstand 28 an das Versorgungspotential 1 angeschlossen. Der Emitter des Transistors 30 ist mit dem Kollektor eines mehrere, beispielsweise zwei miteinander gekoppelte Emitter aufweisenden Transistors 32 verschaltet, wobei die beiden miteinander gekoppelten Emitter des Transistors 32 über einen Widerstand 33 an das Bezugspotential 4 angeschlossen sind. Die Basen der Transistoren 31 und 32 sind dabei mit dem Kollektor des jeweils anderen Transistors verbunden.The current source 5 is preferred as a bandgap current source executed. In the exemplary embodiment, this consists of a Transistor 31, whose emitter with the reference potential 4 and whose collector with the interposition of a diode 29 in Forward direction connected to the base of a transistor 30 is. The base of transistor 30, the collector of which Base of the transistor 2 is connected, is also via a Resistor 28 connected to supply potential 1. The emitter of transistor 30 is one with the collector several, for example two coupled emitters having transistor 32 connected, the two coupled emitter of transistor 32 via a Resistor 33 are connected to the reference potential 4. The bases of the transistors 31 and 32 are with the Collector of the other transistor connected.

Zur Erzeugung eines von der Versorgungsspannung unabhängigen Biaspotentials 25 wird erfindungsgemäß ein von der Differenz des Versorgungspotentials 1 und des gewünschten Biaspotentials 25 abhängiger Strom gebildet, der den an das Versorgungspotential 1 angeschlossenen Widerstand 11 speisen soll. Der Wert I dieses Stroms, der durch den Kollektorstrom des Transistors 9 gegeben ist, ergibt sich aus dem Wert V des Versorgungspotentials 1 und den gewünschten Wert U des Biaspotentials 25 bei einem Widerstandswert R des Widerstands 11 wie folgt: I = (V-U)/R. To generate a bias potential 25 that is independent of the supply voltage, a current that is dependent on the difference between the supply potential 1 and the desired bias potential 25 is formed according to the invention and is intended to feed the resistor 11 connected to the supply potential 1. The value I of this current, which is given by the collector current of the transistor 9, results from the value V of the supply potential 1 and the desired value U of the bias potential 25 at a resistance value R of the resistor 11 as follows: I = (VU) / R.

Der gewünschte Wert U für das Biaspotential 25 liegt dabei beispielsweise im Bereich um 3 Volt. Die Stromquelle 5 als Bandgap-Stromquelle liefert einen Strom mit positivem Temperaturgang. Dadurch wird zusammen mit der Basis-Emitter-Strecke des Transistors 2 zwischen dem Versorgungspotential 1 und dem Emitter des Transistors 2 eine temperaturunabhängige Bandgap-Spannung von etwa 1,2 Volt gebildet. Die nachfolgenden Transistoren 7 und 9 fügen dem zwei Basis-Emitter-Strecken von etwa 0,9 Volt hinzu, so daß in etwa 3 Volt erreicht werden. Da aber die Transistoren 7 und 9 je nach Versorgungsspannung einen unterschiedlichen Kollektorstrom führen, muß folglich die Wirkung der Versorgungsspannung auf diese Ströme noch eliminiert werden.The desired value U for the bias potential 25 lies here for example around 3 volts. The current source 5 as Bandgap current source provides a current with a positive temperature response. This is done together with the base-emitter path of the transistor 2 between the supply potential 1 and the emitter of transistor 2 a temperature independent Band gap voltage of about 1.2 volts is formed. The following Transistors 7 and 9 add two base-emitter paths of about 0.9 volts, so that about 3 volts can be achieved. But since the transistors 7 and 9 depending on Supply voltage a different collector current consequently lead to the effect of the supply voltage these currents can still be eliminated.

Der gewünschte Wert U des Biaspotentials ergibt sich aus dem Wert I5 der Stromquelle 5, dem Wert R3 des Widerstands 3, der Thermospannung UT, dem Wert I6 des von der Stromquelle 6 abgegebenen Stroms, dem Wert I8 des von der Stromquelle 8 abgegebenen Stroms, dem Wert IS des Transistorsperrstroms sowie den Wert I des als Ausgangsstrom vorgesehenen Kollektorstroms des Transistors 9: U = I5R3+UT ln I 6(I 8+I/2)·I 2IS 3 . The desired value U of the bias potential results from the value I 5 of the current source 5, the value R 3 of the resistor 3, the thermal voltage U T , the value I 6 of the current emitted by the current source 6, the value I 8 of the current source 8 emitted current, the value I S of the transistor reverse current and the value I of the collector current of the transistor 9 provided as the output current: U = I 5 R 3rd + U T ln I. 6 ( I. 8th + I. / 2) I. 2nd I. S 3rd .

Bei einem konstanten Wert I6 und einem Wert I8 = 0 ist der Wert I abhängig von dem Wert V und damit auch von dem Wert U. Wählt man nun I6 = 2IK 2/I und I8 = IK-I/2, wobei IK ein konstanter Wert ist, so wird U = I5R3+3UT ln(IK/IS) und damit unabhängig von dem Wert V.With a constant value I 6 and a value I 8 = 0, the value I is dependent on the value V and thus also on the value U. Now choose I. 6 = 2I K 2nd / I and I. 8th = I K -I / 2, where I K is a constant value, then U = I 5 R 3rd + 3U T ln (I K / I S ) and therefore regardless of the value V.

Die Anwendung einer erfindungsgemäßen Schaltungsanordnung bei einer Logikschaltung, insbesondere einem Speicherelement, ist in Figur 2 dargestellt. Das von der Schaltungsanordnung 34 nach Figur 1 erzeugte Biaspotential 25 wird dabei an die Basis eines Transistors 35 angelegt, dessen Kollektor mit dem Versorgungspotential 1 und dessen Emitter unter Zwischenschaltung eines Widerstandes 36 an das Bezugspotential 4 angeschlossen ist. An dem Emitter des Transistors 35 ist die Basis eines Transistors 37 angeschlossen, dessen Kollektor mit dem Versorgungspotential 1 und dessen Emitter über einen Widerstand 38 mit dem Bezugspotential verbunden ist. An dem Widerstand 38 fällt eine Spannung ab, die gleich der Spannung zwischen Kollektor und Emitter des Transistors 2 aus Figur 1 ist. An den Emitter des Transistors 37 ist die Basis eines Transistors 39 angeschlossen, dessen Emitter unter Zwischenschaltung eines Widerstandes 40 mit dem Bezugspotential 4 gekoppelt ist. Der Kollektor des Transistors 39 ist mit den Emittern zweier Transistoren 41 und 42 verbunden, an deren Basen ein Taktsignal 43 bzw. ein invertiertes Taktsignal 43 angelegt sind. Der Kollektor des Transistors 41 ist mit den Emittern zweier Transistoren 44 und 45 verbunden, an deren Basen ein Datensignal 46 bzw. ein invertiertes Datensignal 46 angelegt sind. Der Kollektor des Transistors 42 ist in gleicher Weise mit den Emittern zweier Transistoren 47 und 48 verbunden, wobei die Basis des Transistors 47 mit dem Kollektor des Transistors 45 und die Basis des Transistors 48 mit dem Kollektor des Transistors 44 verschaltet ist. Außerdem sind die Kollektoren der Transistoren 44 und 47 ein invertiertes Ausgangssignal 49 führend miteinander sowie unter Zwischenschaltung eines Widerstands 50 mit dem Versorgungspotential 1 gekoppelt. Ebenso sind die Kollektoren der Transistoren 45 und 48 ein Ausgangssignal 49 führend miteinander verschaltet und über einen Widerstand 51 an das Versorgungspotential 1 angeschlossen.The application of a circuit arrangement according to the invention to a logic circuit, in particular a memory element, is shown in FIG. 2. The bias potential 25 generated by the circuit arrangement 34 according to FIG. 1 is applied to the base of a transistor 35, the collector of which is connected to the supply potential 1 and the emitter of which is connected to the reference potential 4 with the interposition of a resistor 36. The base of a transistor 37 is connected to the emitter of the transistor 35, the collector of which is connected to the supply potential 1 and the emitter is connected to the reference potential via a resistor 38. A voltage drops across the resistor 38, which is equal to the voltage between the collector and emitter of the transistor 2 from FIG. 1. The base of a transistor 39 is connected to the emitter of transistor 37, the emitter of which is coupled to reference potential 4 with the interposition of a resistor 40. The collector of the transistor 39 is connected to the emitters of two transistors 41 and 42, at the bases of which a clock signal 43 or an inverted clock signal 43 are created. The collector of transistor 41 is connected to the emitters of two transistors 44 and 45, at the bases of which a data signal 46 or an inverted data signal 46 are created. The collector of transistor 42 is connected in the same way to the emitters of two transistors 47 and 48, the base of transistor 47 being connected to the collector of transistor 45 and the base of transistor 48 being connected to the collector of transistor 44. In addition, the collectors of transistors 44 and 47 are an inverted output signal 49 coupled with each other and with the interposition of a resistor 50 with the supply potential 1. Likewise, the collectors of transistors 45 and 48 are connected to each other in an output signal 49 and connected to supply potential 1 via a resistor 51.

Die Anwendung der erfindungsgemäßen Schaltungsanordnung 34 aus Figur 1 bei einer Treiberschaltung ist in Figur 3 dargestellt. Das von der Schaltungsanordnung 34 erzeugte Biaspotential 25 wird dabei an die Basis eines Transistors 52, dessen Kollektor mit dem Versorgungspotential 1 verbunden ist, angelegt. Der Emitter des Transistors 52 ist zum einen über einen Widerstand 53 mit der einen Signaleingang 54 bildenden Basis eines Transistors 55 und zum anderen über einen Widerstand 56 mit der einen invertierenden Signaleingang 57 bildenden Basis eines Transistors 58 verbunden. Die Emitter der Transistoren 55 und 58, deren Kollektoren an das Versorgungspotential 1 angeschlossen sind, sind unter Zwischenschaltung jeweils eines Widerstandes 59 bzw. 60 mit dem Bezugspotential 4 gekoppelt. An die Emitter der Transistoren 55 und 58 ist die Basis jeweils eines Transistors 61 bzw. 62 angeschlossen, deren Emitter miteinander gekoppelt und über einen Widerstand 63 mit dem Bezugspotential 4 verbunden sind. Die Kollektoren der Transistoren 61 und 62 sind ein Ausgangssignal 64 bzw. ein invertierendes Ausgangssignal 64 führend über jeweils einen Widerstand 65 bzw. 66 an das Versorgungspotential 1 angeschlossen.The application of the circuit arrangement 34 according to the invention from FIG. 1 to a driver circuit is shown in FIG. The bias potential 25 generated by the circuit arrangement 34 is applied to the base of a transistor 52, the collector of which is connected to the supply potential 1. The emitter of the transistor 52 is connected on the one hand via a resistor 53 to the base of a transistor 55 which forms a signal input 54 and on the other hand via a resistor 56 to the base of a transistor 58 which forms an inverting signal input 57. The emitters of the transistors 55 and 58, the collectors of which are connected to the supply potential 1, are coupled to the reference potential 4 with the interposition of a resistor 59 and 60, respectively. The base of a transistor 61 or 62 is connected to the emitters of transistors 55 and 58, the emitters of which are coupled to one another and connected to reference potential 4 via a resistor 63. The collectors of transistors 61 and 62 are an output signal 64 and an inverting output signal, respectively 64 leading connected to the supply potential 1 via a respective resistor 65 or 66.

Figur 4 zeigt die Anwendung einer erfindungsgemäßen Schaltungsanordnung 34 bei einem linearen Verstärker. Das von der Schaltungsanordnung 34 erzeugte Biaspotential 25 wird dabei der Basis eines Transistors 67 sowie dem Kollektor eines Transistors 68 zugeführt. Die Basis des Transistors 68, dessen Emitter an das Bezugspotential 4 angeschlossen ist, bildet einen Signaleingang 69. Die Basis des Transistors 68 ist darüber hinaus zum Zwecke der Rückkopplung über eine Reihenschaltung zweier Widerstände 70 und 71 mit dem Emitter des kollektorseitig an das Versorgungspotential 1 angeschlossenen Transistors 67 gekoppelt. Der Abgriff zwischen den beiden Widerständen 70 und 71 ist über einen Kondensator 74 gegen das Bezugspotential 4 geführt. Schließlich ist ein Widerstand 72 zwischen den einen Ausgang 73 bildenden Emitter des Transistors 67 und das Bezugspotential 4 geschaltet. Die Verstärkung der Verstärkerschaltung ergibt sich dabei aus dem Verhältnis der über der Laststrecke des Transistors 2 Figur 1 abfallenden Spannung zur Thermospannung.Figure 4 shows the application of a circuit arrangement according to the invention 34 for a linear amplifier. That from the Circuit arrangement 34 generated bias potential 25 the base of a transistor 67 and the collector of one Transistor 68 fed. The base of transistor 68, whose emitter is connected to the reference potential 4, forms a signal input 69. The base of transistor 68 is also for feedback purposes Series connection of two resistors 70 and 71 with the emitter of the collector side connected to supply potential 1 Transistor 67 coupled. The tap between the two resistors 70 and 71 is via a capacitor 74 out against the reference potential 4. After all, is one Resistor 72 between the emitter forming an output 73 of transistor 67 and the reference potential 4 switched. The Gain of the amplifier circuit results from the Ratio of the over the load path of the transistor 2 Figure 1 falling voltage to thermal voltage.

Sowohl bei dem Ausführungsbeispiel nach Figur 1 als auch bei dem Anwendungsbeispielen der Figuren 2 bis 4 werden ausschließlich npn-Transistoren verwendet, so daß in dem Fall das Versorgungspotential 1 positiv und das Bezugspotential 4 negativ ist. Eine Realisierung mit ausschließlich pnp-Transistoren oder gemischt mit npn- und pnp-Transistoren ist jedoch ebenfalls möglich. Die gezeigten Schaltungen arbeiten in einem Spannungsbereich von 3 Volt bis 6 Volt und weisen dabei mit gleichbleibenden Eigenschaften auf.Both in the embodiment of Figure 1 and in The application examples of Figures 2 to 4 are exclusive NPN transistors are used, so in the case the supply potential 1 positive and the reference potential 4 is negative. A realization with only pnp transistors or mixed with npn and pnp transistors however also possible. The circuits shown work in a voltage range from 3 volts to 6 volts and have while maintaining the same properties.

Claims (7)

  1. Circuit arrangement for generating a bias potential, having
    a first transistor (2), which is connected to a supply potential (1) on the collector side,
    a first resistor (3), which is connected between the base and the collector of the transistor (2),
    a first current source (5), which is connected between the base of the first transistor (2) and a reference potential (4),
    a second current source (6), which is connected between the emitter of the first transistor (2) and the reference potential (4),
    a second transistor (7), which is connected to the supply potential (1) on the collector side and to the emitter of the first transistor (2) on the base side,
    a third current source (8), which is connected between the emitter of the second transistor (7) and the reference potential (4),
    a third transistor (9), which carries the bias potential on the collector side,
    a second resistor (10), which is connected between the emitter of the second transistor (7) and the base of the third transistor (9),
    a third resistor (11), which is connected between the collector of the third transistor (9) and the supply potential (1),
    a first, forward-biased diode (12), which is connected between the base of the third transistor (9) and the reference potential (4),
    and a fourth resistor (13), which is connected between the emitter of the third transistor (9) and the reference potential, the fourth resistor (13) having half the resistance of the second or third resistor (10, 11), which have mutually identical resistances,
    and the second and third current sources supplying a current which is dependent on the collector current of the third transistor (9).
  2. Circuit arrangement according to Claim 1,
    characterized in that
    the third transistor (9) has a further emitter connected to the reference potential (4) via a respective fifth resistor (13'), and
    in that the second, third, fourth and fifth resistors (10, 11, 13, 13') have the same resistance.
  3. Circuit arrangement according to one of the preceding claims,
    characterized in that the second current source (6) has a fourth transistor (14), which is connected to the reference potential (4) on the emitter side and to the emitter of the first transistor (2) on the collector side,
    a fifth transistor (15), which is connected to the supply potential (1) on the collector side and to the base of the fourth transistor (14) on the emitter side, a sixth transistor (16), which is connected to the reference potential (4) on the emitter side and to the base of the fourth transistor (14) on the collector side,
    two second, forward-biased diodes (17, 18), which are serially connected between the base of the fifth transistor (15) and the reference potential (4), and
    a sixth resistor (20), which is connected between the base of the fifth transistor (15) and an auxiliary potential (19),
    and in that the base of the sixth transistor (16) is connected to that terminal of the first diode (12) which is remote from the reference potential (4).
  4. Circuit arrangement according to one of the preceding claims,
    characterized in that the third current source (8) has a seventh transistor (21); which is connected to the reference potential (4) on the emitter side,
    a third, forward-biased diode (22) which is connected between the collector and the emitter of the seventh transistor (21),
    a seventh resistor (23), which is connected between the auxiliary potential (19) and the collector of the seventh transistor (21),
    an eighth transistor (24), which is connected to the reference potential (4) on the emitter side and to the collector of the seventh transistor (21) on the base side, and
    in that the base of the seventh transistor (21) is connected to that terminal of the first diode (12) which is remote from the reference potential (4), and the collector of the eighth transistor (24) is connected to the emitter of the second transistor (7).
  5. Circuit arrangement according to one of the preceding claims,
    characterized in that the auxiliary potential (19) can be picked off at the emitter of a ninth transistor (26), whose collector is connected to the supply potential (1) and whose base is connected to the collector of the third transistor (9).
  6. Circuit arrangement according to one of the preceding claims,
    characterized in that the first current source (5) is provided by a bandgap current source.
  7. Circuit arrangement according to one of the preceding claims,
    characterized in that a resistor (27) has a resistance like that of the second or third resistor (10, 11) and is connected between the first diode (12) and the base of the third transistor (9).
EP96114180A 1995-09-26 1996-09-04 Circuit for generating a bias voltage Expired - Lifetime EP0766163B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19535807A DE19535807C1 (en) 1995-09-26 1995-09-26 Bias potential generating circuit for bipolar circuit
DE19535807 1995-09-26

Publications (3)

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EP0766163A2 EP0766163A2 (en) 1997-04-02
EP0766163A3 EP0766163A3 (en) 1998-04-01
EP0766163B1 true EP0766163B1 (en) 1999-04-21

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DE (2) DE19535807C1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920184A (en) * 1997-05-05 1999-07-06 Motorola, Inc. Low ripple voltage reference circuit
DE10011670A1 (en) * 2000-03-10 2001-09-20 Infineon Technologies Ag Circuit arrangement, especially integrated bipolar BIAS circuit - comprises several collector current sources which are respectively formed by transistor, whose base is respectively connected with output of reference voltage source

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4091321A (en) * 1976-12-08 1978-05-23 Motorola Inc. Low voltage reference
NL7803607A (en) * 1978-04-05 1979-10-09 Philips Nv VOLTAGE REFERENCE CIRCUIT.
US5027016A (en) * 1988-12-29 1991-06-25 Motorola, Inc. Low power transient suppressor circuit
NL9002392A (en) * 1990-11-02 1992-06-01 Philips Nv BANDGAP REFERENCE SWITCH.
IT1244341B (en) * 1990-12-21 1994-07-08 Sgs Thomson Microelectronics REFERENCE VOLTAGE GENERATOR WITH PROGRAMMABLE THERMAL Drift
IT1252324B (en) * 1991-07-18 1995-06-08 Sgs Thomson Microelectronics HIGH STABILITY VOLTAGE REGULATOR INTEGRATED CIRCUIT AND LOW CURRENT CONSUMPTION.
US5258703A (en) * 1992-08-03 1993-11-02 Motorola, Inc. Temperature compensated voltage regulator having beta compensation
US5352973A (en) * 1993-01-13 1994-10-04 Analog Devices, Inc. Temperature compensation bandgap voltage reference and method
US5325045A (en) * 1993-02-17 1994-06-28 Exar Corporation Low voltage CMOS bandgap with new trimming and curvature correction methods
US5410241A (en) * 1993-03-25 1995-04-25 National Semiconductor Corporation Circuit to reduce dropout voltage in a low dropout voltage regulator using a dynamically controlled sat catcher
US5424628A (en) * 1993-04-30 1995-06-13 Texas Instruments Incorporated Bandgap reference with compensation via current squaring
JP3335754B2 (en) * 1994-03-16 2002-10-21 三菱電機株式会社 Constant voltage generator

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DE59601698D1 (en) 1999-05-27
EP0766163A2 (en) 1997-04-02
EP0766163A3 (en) 1998-04-01
DE19535807C1 (en) 1996-10-24
US5656927A (en) 1997-08-12

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