Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
  • H03F3/45197—Pl types
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
  • G05F3/262—Current mirrors using field-effect transistors only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
  • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45048—Calibrating and standardising a dif amp
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45202—Indexing scheme relating to differential amplifiers the differential amplifier contains only resistors in the load
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45356—Indexing scheme relating to differential amplifiers the AAC comprising one or more op-amps, e.g. IC-blocks
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45466—Indexing scheme relating to differential amplifiers the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45471—Indexing scheme relating to differential amplifiers the CSC comprising one or more extra current sources

Definitions

• the present invention relates to current mirrors, and more particularly, to output current mirrors for use with transconductor circuits. It is known to provide current mirrors which include two transistors as shown in Fig. 1. In such a current mirror, transistor Nl is diode connected. The gate of transistor Nl is connected to the gate and drain of transistor N2, thus forcing the same gate to source voltage on both Nl and N2. If transistor Nl is in the "saturated" mode of operation (i.e., V ds of Nl is > V gs - V, of Nl where V ds is the drain to source voltage, V.
• the current into the drain node of Nl is ideally proportional to the current into the drain node of N2 by the ratio of the transistor's gate widths and inversely proportional to the transistor's gate lengths.
• the threshold voltage of Nl is not equal to the threshold voltage of N2
• 1 to 2 millivolts of threshold mismatch between transistors Nl and N2 can produce distortion levels of -60dB or more.
• Current mirrors are required in the design of high linearity, low distortion, continuous time transconductors in CMOS.
• a transconductor is a circuit which receives an input voltage and generates an output current.
• the magnitude of the output current is proportional to the input voltage received; the ratio by which the output current changes for a given ratio of input voltage change is known as the conversion gain, or transconductance (GM) , of the transconductor.
• GM conversion gain
• a differential transconductor receives a differential voltage impressed between two input terminals (ignoring the common-mode voltage) and generates a differential current on two current output terminals.
• a differential transconductor 20 which is known in the art is shown in Fig. 2. The topology of this circuit is generally known as a degenerated pair linearized by servo-feedback.
• Transconductor 20 includes current source circuit 30 as well as input circuits 32, 34.
• Current source circuit 30 includes current sources 36, 37 which provide currents in the amount of I 0 to summing nodes 38, 39, respectively.
• Input circuit 32 includes operational amplifier 40 having a non-inverting input coupled to input voltage terminal 22 and an inverting input coupled to summing node 38. The output of operational amplifier 40 drives the gate of transistor 42, which in this embodiment is shown as a P channel MOS transistor. Transistor 42 couples summing node 38 to current output terminal 26.
• Input circuit 34 includes operational amplifier 50 having a non-inverting input terminal coupled to input voltage terminal 24 and an inverting input terminal coupled to summing node 39.
• the output of operational amplifier 50 drives the gate of transistor 52, which is also shown as a P channel MOS transistor.
• Transistor 52 couples summing node 39 to current output terminal 28.
• Transconductor 20 also includes resistor 54 having a resistance of R ohms. Resistor 54 couples summing node 38 to summing node 39.
• Current output terminals 28, 29 are coupled to respective current mirrors 56, 57, which in turn provide differential current outputs I L ' and I R ' to current mirror current output terminals 58, 59.
• Current mirrors 56, 57 are similarly configured to provide output currents having the same ratio to the currents which are provided to the respective current mirrors.
• Input circuit 32 forces the voltage of summing node 38 to follow the voltage, V L , received on input voltage terminal 22. This occurs because operational amplifier 40 drives the gate of transistor 42 to a suitable voltage such that the voltage of summing node 38, which is coupled to the inverting input of operational amplifier 40, follows the voltage, V L , coupled to the non-inverting input of operational amplifier 40.
• input circuit 34 forces the voltage of summing node 39 to follow voltage, V R , received on input voltage terminal 24.
• V R is greater in magnitude than V L , then a negative current I s flows from summing node 38 to summing node 39 which, of course, is equivalent to a positive current flow from summing node 39 to summing node 38.
• Summing node 38 receives a current I 0 from current source 36 and sources a current I s flowing into summing node 39.
• the net current provided to the source of transistor 42 is I 0 - I s , which is coupled via transistor 42 to current output terminal 26.
• summing node 39 receives a current I 0 from current source 37, and receives a current I s flowing from summing node 38.
• the net current supplied to the source of transistor 52 is I 0 + I s , which is coupled via transistor 52 to current output terminal 28.
• Current output terminals 26, 28 provide respective currents I L and I R to current mirrors 56, 57 which provide output currents I L ' and I R ' to current mirror current output terminals 58, 59.
• Currents I L ' and I R ' are proportional to the currents I L and I R .
• transistor N2 of the current mirrors 56, 57 has a drain to source voltage equal to the threshold voltage of the transistor plus an excess voltage related to the square root of the current into the drain of transistor N2 and its gate width and gate length. Accordingly, the threshold voltage present at the current output terminals of the transconductor is limited by this configuration
• a transconductor with a current mirror with an input resistor through which an input current is passed to provide a first voltage, an output resistor, and an amplifier which senses the input voltage and the voltage across the output resistor and an output transistor having a gate coupled to the output of the amplifier and a source coupled to the output resistor advantageously provides a transconductor having low distortion.
• a programmable current mirror may be provided by providing an amplifier with a plurality of resistance access paths into an output resistor string of the feedback path of the amplifier thus advantageously reducing distortion attributable to the current mirror.
• the branches are provided using switches. Because no current flows through the switches due to the high input impedance of the amplifier, the switches do not contribute noise or distortion to the programmable current mirror.
• Such a system advantageously may be implemented as either a fixed or programmable current divider or multiplier.
• Such a system maximizes the input swing of a transconductor based upon a degenerated pair linearized by servo-feedback, i.e., the range of the input voltage V L or V R while the transconductor maintains high linearity, by keeping the voltage at the output terminals as low as possible.
• the present invention eliminates the threshold voltage present at the output terminals of the transconductor.
• such a system advantageously eliminates MOS threshold mismatch as a source of distortion. Additionally, such a system advantageously controls distortion of the current mirror by removing transistor threshold mismatches from effecting the distortion. Additionally, such a system advantageously makes MOS threshold mismatch in current mirrors an offset which can be trimmed out of the circuit.
• Fig. 1 shows a schematic block diagram of a prior art current mirror.
• Fig. 2 shows a schematic block diagram of a transconductor.
• Fig. 3 shows a schematic block diagram of a current mirror in accordance with the present invention.
• Fig. 4 shows a schematic block diagram of a current mirror of Fig. 3 within a differential transconductor.
• Fig. 5 shows a schematic block diagram of a programmable current mirror in accordance with the present invention.
• Current mirror 60 includes operational amplifier 62, as well as output current sensing transistor 64, input resistor (Rl) 66 and output resistor (R2) 68.
• the gate of transistor 64 is coupled to the output of operational amplifier 62, the drain of transistor 64 is coupled to the output current source of current mirror 60, and the source of transistor 64 is coupled to output resistor 68.
• an input current, I., is provided to input resistor Rl as well as the non- inverting input of operational amplifier 62.
• the input current passing through input resistor Rl generates a voltage V* across resistor Rl.
• the voltage across resistor Rl (V,) is present at the non-inverting input of operational amplifier 62.
• the voltage V, which is present at the inverting input of operational amplifier 62 is also forced at the inverting input of operational s amplifier 62 and thus at the top of output resistor R2 as the voltage V 2 .
• V 2 ideally equal to V,. How closely V 2 tracks V, depends upon the open loop gain of amplifier 62.
• Operational amplifier 62 can be designed such that V 2 can be made arbitrarily close of V,. Accordingly, the o output current 1- ⁇ , of current mirror 60 is a ratio of the resistor sizes Rl and R2.
• the input offset created by threshold and other device mismatches in operational amplifier 62 only creates a fixed DC error between I m and I M . Threshold mismatches are caused by small random s differences in the processing of individual transistors. Accordingly this error does not contribute to the distortion of the current mirror and can be easily trimmed out of the circuit.
• a schematic block diagram of a differential transconductor 80 having a plurality of current mirrors in accordance with the present invention is shown. More specifically, current mirror 60 R and current mirror 60 L are coupled to the respective output o terminals of differential transconductor 80.
• the current, I L which is provided by transconductor 80 is scaled by the ratio R1 L /R2 L and is provided as the output current I OL .
• the current, I R which is provided by transconductor 80 is scaled by the ratio R1 R /R2 R and is 5 provided as the output current I OR . More specifically, a differential input voltage, V L - V R , is received between voltage input terminals 82 and 84, and a corresponding differential output current is generated between current output terminals 86 and 68.
• a current source circuit 90 includes a current source 92 which delivers a current of magnitude I 0 into summing node 96 and further includes a current source 94 which delivers a current of magnitude I 0 into summing node 98.
• Input circuit 100 includes an operational amplifier 102 (functioning as a gain block) having a non-inverting input coupled to the voltage input terminal 82 and an inverting input coupled to a first feedback node 110.
• the output of operational amplifier 102 drives the gate of transistor 104, which in this embodiment is a P channel MOS transistor.
• Transistor 104 couples summing node 96 to the current output terminal 86.
• a second input circuit 120 includes an operational amplifier 122 having a non-inverting input coupled to the voltage input terminal 84 and an inverting input coupled to a second feedback node 124.
• the output of operational amplifier 122 drives the gate of transistor 126, which in this embodiment is also a P channel MOS transistor.
• Transistor 126 couples summing node 98 to the current output terminal 88.
• Circuit 130 includes a selector circuit having an array of switch circuits and includes a resistor circuit having a total resistance of R ohms coupling summing node 96 to summing node 98, and which resistor circuit includes resistors 132, 134, 136, 138, and 140 connected in series and defining a group of intermediate nodes 142, 144, 146, and 148 respectively therebetween. These intermediate nodes, together with summing nodes 96 and 98, form a group of tap nodes of the resistor circuit.
• the selector circuit includes an array of switch circuits.
• Switch circuit 150 couples summing node 96 to feedback node 110 when enabled by logical signal S3.
• Switch circuit 152 couples intermediate node 142 to feedback node 110 when enabled by logical signal S2, and switch circuit 153 couples intermediate node 144 to feedback node 110 when enabled by logical signal SI.
• switch circuit 154 couples summing node 98 to feedback node 124 when enabled by logical signal S3
• switch circuit 155 couples intermediate node 148 to feedback node 124 when enabled by logical signal S2, and switch circuit 156 couples intermediate node 146 to feedback node 124 when enabled by logical signal SI.
• Logical signals SI, S2, and S3 are preferably digital control signals which select the desired transconductance of the circuit, but may also be a hardwired or some other fixed connection.
• operational amplifier 102 drives the gate of transistor 104 to a suitable voltage such that the voltage of summing node 96 is driven to a voltage higher than V L , so that the voltage of feedback node 110, which is coupled to the inverting input of operational amplifier 102, follows the input voltage V L . Due to the high input impedance of operational amplifier 102, virtually no DC current flows through switch circuit 64 and consequently the voltage of feedback node 110 follows the voltage of intermediate node 142 with negligible voltage drop, noise, or distortion effects.
• input circuit 120 functions to force the voltage of intermediate node 148 to follow the voltage, V R , received on voltage input terminal 84.
• V R voltage input terminal 84.
• the differential input voltage V L - V R is placed directly across an effective resistance, R ⁇ , consisting of resistors 134, 136, and 138 (since for this discussion logical signal S2 is active) .
• summing node 98 receives a current I 0 from current source 94, and receives a current I s flowing from summing node 96.
• the net current provided to transistor 126 is I 0 + I s , which is then coupled by transistor 126 to the current output terminal 88.
• This programmable topology is achieved by using a string of series-connected resistors, with a group of switch circuits to selectively "tap off" two nodes from the string, and to feedback these nodes to the inverting inputs of the operational amplifiers 102 and 122, respectively.
• the selected nodes are symmetrically displaced around resistor 136.
• the taps By changing the taps, the value of the effective resistor R eff is varied, with a resultant change in the transconductance GM (which varies as l/ ⁇ ) .
• Individual switch circuits are enabled by digital control signals which are provided based upon information which is stored in internal or external memory.
• the lower limit of the dynamic range of the input of transconductor 80 is set by the voltage at the top of resistors R1 R and R1 L of current mirrors 60 R and 60 L , respectively.
• the dynamic range of the input of transconductor 80 can be set to maximize the input signal swing as both the maximum input voltage and transconductor resistor, R, ⁇ are known. More specifically, the system maximizes the input swing of a transconductor based upon a degenerated pair linearized by servo-feedback, i.e., the range of the input voltage V L or V R while the transconductor maintains high linearity, by keeping the voltage at the output terminals as low as possible.
• V RL The maximum voltage of V RL is controlled by the values of R1 L and R ⁇ *. More specifically, the voltage of V RL is set forth as
• V, ⁇ is the highest desired voltage for V R and V ⁇ is the lowest desired voltage for V L .
• the design of transistor 42 i.e., its gate width and gate length, is specified such that the transistor is in its saturated mode of operation when the input voltage V L is equal to V, ⁇ .
• current mirror 60' may be configured as a programmable current mirror by providing a programmable output resistance.
• the programmable output resistance is provided using a combination of MOS switches and resistors to provide a variable output resistance which is programmably set.
• the MOS switch which is turned on remains in the feedback loop of operational amplifier 62 but does not contribute to the noise or distortion of the current mirror because no current flows through the switch because of the high input impedance of operational amplifier 62.
• Each switch 120 (SI, S2, S3) is provided by combining an NMOS device with a PMOS device.
• switch can also be composed of either an NMOS or PMOS device.
• the switch 120 which is actuated controls the gain of the current mirror. More specifically, by controlling current mirror 60' so that switch SI is 'on', (i.e., the transistors are operating in their linear region so that the switch provides a short) and switches S2 and S3 are 'off (i.e., the transistors are not conducting so that the switch provides an open circuit) ,
• operational amplifier 62 is implemented with either CMOS folded cascode and two stage amplifiers, these amplifiers may be implemented in any other conventional technology such as MOS, CMOS, BiCMOS or other bipolar technologies.
• output current sensing transistor 64 may be replaced with a bipolar transistor without affecting the operation of current mirror 60.
• current mirror 60 may be configured to source current.
• the preferred embodiment of current mirror 60 sinks current as the resistors are coupled to ground.
• a complementary configuration connects the resistors to a supply voltage and uses a PMOS transistor or a bipolar PNP transistor to create a current source.
• the programmable current mirror shown is Fig. 5 includes three switches and three resistors, it will be appreciated that any number of switches and resistors may be provided and also that different combinations of resistors and switches may also be provided.
• a transistor may be conceptualized as having a control terminal which controls the flow of current between a first current handling terminal and a second current handling terminal. An appropriate condition on the control terminal causes a current to flow from/to the first current handling terminal and to/from the second current handling terminal.
• the first current handling terminal is the collector
• the control terminal is the base
• the second current handling terminal is the emitter. A sufficient current into the base causes a collector-to- emitter current to flow.
• the first current handling terminal is the emitter
• the control terminal is the base
• the second current handling terminal is the collector.
• a current exiting the base causes an emitter-to-collector current to flow.
• a MOS transistor may likewise be conceptualized as having a control terminal which controls the flow of current between a first current handling terminal and a second current handling terminal.
• MOS transistors are frequently discussed as having a drain, a gate, and a source, in most such devices the drain is interchangeable with the source. This is because the layout and semiconductor processing of the transistor is symmetrical (which is typically not the case for bipolar transistors) .
• the current handling terminal normally residing at the higher voltage is customarily called the drain.
• the current handling terminal normally residing at the lower voltage is customarily called the source.
• a sufficient voltage on the gate causes a current to therefore flow from the drain to the source.
• the gate to source voltage referred to in an N channel MOS device equations merely refers to whichever diffusion (drain or source) has the lower voltage at any given time.
• the "source" of an N channel device of a bi-directional CMOS transfer gate depends on which side of the transfer gate is at a lower voltage.
• the control terminal is the gate
• the first current handling terminal may be termed the "drain/source”
• the second current handling terminal may be termed the "source/drain”.

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• 1996
  • 1996-03-01 WO PCT/US1996/002434 patent/WO1996027238A1/en not_active Application Discontinuation
  • 1996-03-01 EP EP96907887A patent/EP0759229A1/en not_active Ceased
  • 1996-03-01 JP JP8526344A patent/JPH10505989A/ja not_active Ceased
  • 1996-03-01 AU AU51333/96A patent/AU5133396A/en not_active Abandoned

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