EP0742660A1 - Processeur à signaux à conversion de données - Google Patents

Processeur à signaux à conversion de données Download PDF

Info

Publication number
EP0742660A1
EP0742660A1 EP96201266A EP96201266A EP0742660A1 EP 0742660 A1 EP0742660 A1 EP 0742660A1 EP 96201266 A EP96201266 A EP 96201266A EP 96201266 A EP96201266 A EP 96201266A EP 0742660 A1 EP0742660 A1 EP 0742660A1
Authority
EP
European Patent Office
Prior art keywords
symbol
symbols
path
signal processor
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96201266A
Other languages
German (de)
English (en)
Other versions
EP0742660B1 (fr
Inventor
Aart Cornelis Bochove
Jan Marcel Rijnders
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke KPN NV
Original Assignee
Koninklijke PTT Nederland NV
Koninklijke KPN NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke PTT Nederland NV, Koninklijke KPN NV filed Critical Koninklijke PTT Nederland NV
Publication of EP0742660A1 publication Critical patent/EP0742660A1/fr
Application granted granted Critical
Publication of EP0742660B1 publication Critical patent/EP0742660B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E1/00—Devices for processing exclusively digital data
    • G06E1/02—Devices for processing exclusively digital data operating upon the order or content of the data handled

Definitions

  • the invention relates to a signal processor.
  • the invention relates to the conversion of digital signals in the physical, for example optical, domain.
  • This is, inter alia, relevant in optical ATM systems in which at the inputs of sub-systems, such as switches, control codes such as VPIs and VCIs (Virtual Path and Channel Identifiers respectively) have to be changed.
  • sub-systems such as switches
  • VPIs and VCIs Virtual Path and Channel Identifiers respectively
  • VPIs and VCIs Virtual Path and Channel Identifiers respectively
  • the present application concerns the conversion of logical codes, represented by optical physical codes, by means of physical manipulation of said physical codes, namely the conversion of physical "1" bits into “0" bits and vice versa.
  • the problem in that case is simplicity and optical transparency, without making use of (auxiliary) lasers.
  • the present invention can also be applied in "add-drop" multiplexers in optical networks, for example.
  • the invention is based on the insight that by a suitable time shift (forwards or backwards) of physical optical bits originating from the input signal, which represent certain logical codes, other logical codes can be formed without a light source being necessary for that purpose.
  • the time for which the signal must be shifted is dependent upon the properties of the bit stream and thus of the physical code words. In general it holds that the shift must be such that in each time slot in which a bit is to be changed, a physical bit of the desired other physical kind (desired physical value or property) is present.
  • the logical codes are represented by amplitude-modulated bits, use can be made of the fact that a physical "0" can always be obtained by means of signal interruption during one time slot; in those cases the presence of a "0" bit need not be provided for by shifting of the bit stream. If on the other hand use is made of angularly modulated (frequency- or phase-modulated) physical bits, a physical "0" must in fact always be present. If the signal consists of more than two kinds of symbols (digits), a representative of each of those symbols must be present in the time slot. For the time being, a signal with two kinds of (binary) symbols, called “bits”, will hereinafter be taken as point of departure.
  • the signal processor comprises a bit-shifting device which, under the control of a control device, shifts the bit stream -- or a part thereof -- in such a way that, whenever a bit selected by that control device is to be converted, a bit with the desired value, which can replace the original bit, is always present at the right moment.
  • a delay device can be successfully used from which, besides the undelayed signal, a signal can be derived which is delayed by 1, 2, ..., d max (1) bit times (time slots).
  • this formulation not only holds for non-amplitude modulated bits, but also for indeed amplitude-modulated bits.
  • amplitude-modulated bits can be obtained by interruption of the signal, it is not at all forbidden or impossible to generate those "0" bits in the same way as the "1" bits.
  • angularly modulated bits this is a necessity.
  • Claim 5 pertains to the processing of binary or non-binary symbols, Claim 6 to that of amplitude-modulated or non-amplitude modulated bits, and Claim 7 to that of amplitude-modulated bits.
  • Fig. 1 shows an alternative embodiment of a device according to the invention; likewise Fig. 4.
  • Fig. 5 shows the similarity and the difference between two processing rules and
  • Fig. 6 illustrates the processing of a non-binary symbol string.
  • the device of Fig. 1 is formed by a number of parallel optical paths 1 ... 3, optical fibres or other wave-guides, of different length or at any rate with a different delay time, in each of which an optical switch is included.
  • Each switch is controlled by a control device which on the one hand -- via an optical receiver (O/E converter) -- receives information about the bits which are presented to the device (digits, symbols), and on the other hand receives information about which bits are to be passed on by the device unchanged and which bits are to be changed, either from "1" to "0” or from "0" to "1", from the logical domain (the system control).
  • O/E converter optical receiver
  • the Figure visualises that the device serves for the processing, in the optical domain, of the headers of presented ATM cells. Of course this is only a noncommittal example which in no regard whatsoever restricts the invention. At the time the invention was made, the processing of ATM cells and other optical wide-band applications in particular was indeed held in mind.
  • a code string "B A A B A A B B A” is received by the device in the form "_ ⁇ _ ⁇ __ ⁇ _ ⁇ __ ⁇ _ ⁇ _” (N.B.: the transmission direction shown is, as in Fig. 1, from left to right, so that the rightmost bit is read first; the time slot sequence is therefore 1234567890123.). If it is assumed that the code string received forms part of the header of the ATM cell and that some of the bits of that header are to be changed (which is controlled by the Header Translation Control Codes shown in the Figure), then it is clear that, if a "1" (“ ⁇ ”) has to be changed into a "0” (_), that can be simply carried out by opening all switches in the right time slot, as a result of which the bit stream is interrupted. To change a "0" into a “1” (without supplying external (laser) power), however, measures according to the invention are necessary.
  • the maximal distance d max (1) between two consecutive "0" bits is 2 (namely in the logical code word AB: " ⁇ __ ⁇ ”).
  • the bits To the end of always having a " ⁇ ” available, the bits must always be delayed by both one bit time as well as by two bit times (time slots).
  • the two characters A and B are encoded differently.
  • the coding of the "A” is the same as in the previous example, but the "B” is encoded by " ⁇ " ("11").
  • the run-length specification (see reference 2) of this coding is (0,1), since in an arbitrary character string the number of "_"s between two consecutive " ⁇ ”s is 0 (minimally) or 1 (maximally).
  • the present invention prescribes that for amplitude-modulated bits the number of delay paths does not need to be greater than the maximum number of consecutive "_”s, so that for this coding the number of delay paths can be restricted to 1 (in Fig. 1, path 3 may therefore be cancelled).
  • Table 2/2 it can be seen that in each time slot a " ⁇ " can be derived from the device, either from path 1 or from path 2.
  • Example 2/3 illustrates the case in which two logical characters A and B are each represented by two angularly modulated (angularly encoded) bits.
  • P and Q represent the phases or frequencies of physical "1" and "0" bits respectively. Since in this case a physical "0" bit cannot be obtained by interrupting the bit stream, as in the case of amplitude modulation, the number of delay paths in which both a P bit and a Q bit is always available is equal to 2, since d max (1)(d max ("Q")) is equal to 2 (namely for the logical word AB, physically represented by P QQ P) and d max (2)(d max ("P")) is also equal to 2 (namely for the logical word BA, represented by Q PP Q).
  • bit can be derived from at least one of the two delayed bit streams and can be inserted through control of the switches in the bit stream.
  • Example 2/4 illustrates the case in which, for angularly modulated bits, d max (1)(d max ("Q")) is not equal to d max (2)(d max ("P")), wherein it can be seen that, if the number of paths is (minimally) equal to the largest of d max (1) or d max (2), in each time slot P can be converted into Q or Q can be converted into P with the aid of the bits which are present in the delay paths.
  • the value of d max (1) (the maximum number of consecutive Q bits) is 1, since in each combination of the logical characters A and B the number of physical Q bits is never more than 1 (see the undelayed bits shown).
  • a When deriving physical bits one can, as it were, reach forward or backward. If in example 2/1, for instance, the bits which are not to be converted are passed on by the undelayed path (path 1), a bit stream which is delayed with respect to the default path 1 (path 2 or 3) is used on the conversion of a "0" bit into a "1" bit, which would result in a problem should the first bit (time slot 1) already have to be converted.
  • bit stream through the other paths (1 and 2) leads, as a result of which it is possible to reach forward to one of the relatively leading bit streams through path 1 or 2 when deriving "1" bits.
  • the invention is therefore not based on and restricted to “delaying" the bit stream, but on its “shifting", either forward in time or backward.
  • bit stream pass through path 2 by default, as a result of which conversion bits can be obtained from the leading bit stream through path 1, or from the lagging bit stream through path 3.
  • Claim 3 pertains to the case that bit derivation takes place by bit delay;
  • Claim 4 pertains to the case where the bits are derived from a bit stream which is leading with respect to the main bit stream.
  • That "1" bit is, as it were, buffered for a short time and subsequently injected into the slot of the "0" bit which is to be converted.
  • the invention lends itself just as well to the processing of a bit stream with more than two kinds (thus non-binary) symbols (digits).
  • the optical bits manifested themselves through time slots with an optical signal having the phase, frequency or wavelength P and Q respectively.
  • a first symbol (a symbol of a first kind) can always be converted into a second symbol (a symbol of a second kind): the first symbol has phase Q, for example, and is converted by shifting into a second symbol having phase T, or a first symbol having frequency S is converted into a second symbol having frequency P, etc.
  • Fig. 5 shows the processing of two symbol strings in different ways. For both strings in succession, per symbol (P, Q), the numbers of consecutive time slots with equal symbols (P, Q) are determined, and for both strings, per symbol (P, Q), the numbers of consecutive time slots with unequal symbols (non-P, non-Q). Per string, per processing manner, the maximum of those numbers of time slots is determined.
  • the symbol string of example 5/1 comprises two symbols, P and Q, and can therefore represent a string of bits.
  • the number of consecutive P symbols (P bits) is 8 and 9; the number of Q symbols (Q bits) is 5 and 7.
  • the maximum is therefore 9.
  • a device is therefore necessary which can provide a lead or lag of 9 time slots.
  • the numbers of consecutive non-P bits are 5 and 7 respectively, and the numbers of consecutive non-Q bits 8 and 9. The maximum is therefore again 9.
  • the result is actually the same as the foregoing, since of course in each string with P and Q bits each non-P bit is a Q bit, and each non-Q bit is a P bit.
  • Fig. 6 shows the complete elaboration of an arbitrary string of symbols P, Q, R and S, in which all numbers of directly consecutive non-P, non-Q, non-R and non-S symbols were determined, resulting in a maximum value thereof of 15.
  • the calculated maximum shift of 15 time slots is necessary if the Q symbol in time slot 28 should have to be replaced by a P symbol, which takes place by delaying a P symbol which was presented to the processor 15 time slots earlier (in time slot 13) for 15 time slots, and injecting it into time slot 28 in the symbol string instead of the original Q symbol.
  • Claim 8 pertains to a processor of an architecture as shown in Fig. 1.
  • FIG. 3 An alternative exemplary embodiment for the implementation of the invention is diagrammatically shown in Fig. 3.
  • the device of Fig. 3 comprises an undelayed path with a switch as in Fig. 1, and a delay path with a controllable delay.
  • the switch in that delay path is of the type which in a first position is capable of excluding from the main circuit a connected delay circuit having a delay time of one slot (T) (and simultaneously closing the delay circuit in itself) or, in a second position, of including it; such switches are known as cross-bar switches.
  • T delay time of one slot
  • a fixed delay circuit is further included. If the switch is in the first position, the signal is delayed by the fixed delay circuit for 1 time slot. If the switch is in the second position the delay, by both delay circuits, is 2 time slots.
  • the switch is controlled by a control device which calculates the positions of the switch on the basis of the incoming bit stream and the (header) translation codes.
  • a control device which calculates the positions of the switch on the basis of the incoming bit stream and the (header) translation codes.
  • Claim 9 pertains to a processor of an architecture as shown in Fig. 3.
  • FIG. 4 shows another exemplary embodiment of a processor which, besides a control device, comprises one controllable delay device, in the form of a cross-bar switch.
  • a processor is well applicable for the permutation of bits in bit words with only very few consecutive equivalent bits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optical Communication System (AREA)
  • Saccharide Compounds (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Communication Control (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
EP96201266A 1995-05-09 1996-05-08 Processeur à signaux à conversion de données Expired - Lifetime EP0742660B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
NL1000326 1995-05-09
NL1000326 1995-05-09
NL1000682 1995-06-28
NL1000682A NL1000682C2 (nl) 1995-05-09 1995-06-28 Signaal Processor.

Publications (2)

Publication Number Publication Date
EP0742660A1 true EP0742660A1 (fr) 1996-11-13
EP0742660B1 EP0742660B1 (fr) 2004-08-04

Family

ID=26642067

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96201266A Expired - Lifetime EP0742660B1 (fr) 1995-05-09 1996-05-08 Processeur à signaux à conversion de données

Country Status (4)

Country Link
EP (1) EP0742660B1 (fr)
AT (1) ATE272918T1 (fr)
DE (1) DE69633035T2 (fr)
NL (1) NL1000682C2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275311B1 (en) 1997-06-30 2001-08-14 Pirelli Cavi E Sistemi S.P.A. Optical device for processing an optical digital signal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541855A1 (fr) * 1991-11-15 1993-05-19 Siemens Aktiengesellschaft Détection de mots de code dans un signal transmis en série
WO1994021088A2 (fr) * 1993-03-02 1994-09-15 British Telecommunications Public Limited Company Signaux a codage optique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541855A1 (fr) * 1991-11-15 1993-05-19 Siemens Aktiengesellschaft Détection de mots de code dans un signal transmis en série
WO1994021088A2 (fr) * 1993-03-02 1994-09-15 British Telecommunications Public Limited Company Signaux a codage optique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275311B1 (en) 1997-06-30 2001-08-14 Pirelli Cavi E Sistemi S.P.A. Optical device for processing an optical digital signal

Also Published As

Publication number Publication date
ATE272918T1 (de) 2004-08-15
DE69633035T2 (de) 2005-08-18
EP0742660B1 (fr) 2004-08-04
NL1000682C2 (nl) 1996-11-12
DE69633035D1 (de) 2004-09-09

Similar Documents

Publication Publication Date Title
KR100336496B1 (ko) 무직류, 최소대역폭특성을 갖는 선로부호의 설계방법 및 부호화/복호화 장치
US6269137B1 (en) Method and apparatus for fast burst mode data recovery
US6963697B2 (en) Increased transmission capacity for a fiber-optic link
US6642864B1 (en) Method and apparatus for encoding/decoding N-bit data into 2N-bit codewords
US5874910A (en) Analog signal coding and transmission apparatus and method capable of operation with multiple types of analog and digital signals
JP2011160478A (ja) パルス振幅変調による光差分可変マルチレベル位相シフトキーイング（ｏｄｖｍｐｓｋ／ｐａｍ）信号の生成及び検出のための方法及び装置
US6595707B1 (en) Code conversion circuit for optical duobinary transmission and optical transmitter and receiver using same
JPH02501432A (ja) デジタル信号通信方法及びこの方法を使用する受信機
US6819878B1 (en) Packet-based optical communications networks
CA1123957A (fr) Appareil et methode pour produire un signal correlatif de grande precision a 7 niveaux
EP0742660B1 (fr) Processeur à signaux à conversion de données
US6895023B2 (en) Packet-based optical communications networks
US5991914A (en) Clock recovery using maximum likelihood sequence estimation
US7933354B2 (en) Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
US20050232644A1 (en) Optical heterodyne receiver based on oversampling
WO1991011064A1 (fr) Systeme de transmission a code de correlation
JP2813774B2 (ja) 光符号分割多重伝送アクセス方式及び装置
KR19990044464A (ko) 디지탈 정보신호의 전송, 기록 및 재생
WO1985004775A1 (fr) Circuit a boucle d'asservissement de phase numerique
US4656646A (en) Serial minimum shift-keyed modem
McEwen et al. Trellis codes for (1, k) E/sup 2/PR4ML with squared distance 18
JP3796144B2 (ja) 光信号処理回路
US7236702B2 (en) Method and system for duobinary coding of optical signals
Gagliardi et al. System design for optical PPM communications with diode combining
US6492919B2 (en) Circuit system suitable for codifying NRZ type binary signals into CMI type binary signals

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU NL PT SE

17P Request for examination filed

Effective date: 19970513

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: KONINKLIJKE KPN N.V.

17Q First examination report despatched

Effective date: 20020207

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU NL PT SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20040804

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20040804

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: ISLER & PEDRAZZINI AG

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 69633035

Country of ref document: DE

Date of ref document: 20040909

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20041104

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20041104

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20041104

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20041115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050508

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050509

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20050506

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20070515

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 20070531

Year of fee payment: 12

REG Reference to a national code

Ref country code: CH

Ref legal event code: PCAR

Free format text: ISLER & PEDRAZZINI AG;POSTFACH 1772;8027 ZUERICH (CH)

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050104

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20080515

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20080527

Year of fee payment: 13

BERE Be: lapsed

Owner name: KONINKLIJKE *KPN N.V.

Effective date: 20080531

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080531

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080531

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20090513

Year of fee payment: 14

Ref country code: DE

Payment date: 20090525

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20090522

Year of fee payment: 14

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20091201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20091201

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20100508

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20110131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090508

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100508