EP0732658B1 - Processeur d'entrée/sortie virtuelle - Google Patents

Processeur d'entrée/sortie virtuelle Download PDF

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Publication number
EP0732658B1
EP0732658B1 EP96301490A EP96301490A EP0732658B1 EP 0732658 B1 EP0732658 B1 EP 0732658B1 EP 96301490 A EP96301490 A EP 96301490A EP 96301490 A EP96301490 A EP 96301490A EP 0732658 B1 EP0732658 B1 EP 0732658B1
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EP
European Patent Office
Prior art keywords
data
interrupt
unit
read
programmed
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EP96301490A
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German (de)
English (en)
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EP0732658A1 (fr
Inventor
Thomas L. Lyon
Sun-Den Chen
William Joy
Leslie D. Kohn
Charles E. Narad
Robert Yung
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Sun Microsystems Inc
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Sun Microsystems Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • the present invention relates to the field of computer systems.
  • the present invention relates to input/output I/O methods and apparatus of computer systems.
  • PIO Programmable I/O
  • CPU central processing unit
  • DMA direct memory access
  • dedicated I/O processor is well known in the art.
  • the CPU stalls for the completion of an access to an I/O device.
  • CPU cycles are lost when the PIO cannot, on its own initiative, re-access the I/O device without the CPU being interrupted - see EP 0464615 A2.
  • I/O access tends to have a high latency compared to CPU cycle time
  • programmed I/O has the disadvantage of wasting CPU cycles. The disadvantage is especially aggravating for the modern processors running much faster than the average access time to the I/O devices.
  • Each programmed I/O access to an I/O device could easily waste hundreds of CPU clock cycles. The situation becomes worse as the discrepancy between CPU cycle time and I/O access time becomes larger.
  • Hardware optimizations such as store buffers have been used to reduce the overhead of programmed I/O accesses.
  • the CPU can continue its execution of other programs after a store operation is correctly issued.
  • the store buffer approach typically improves programmed I/O write performance, but does not alleviate the latency problem for programmed I/O read operations.
  • Another approach is the employment of an I/O processor dedicated to performing programmed high level I/O operations.
  • the I/O processor interprets and executes the high level commands received from the CPU, thereby freeing the CPU, allowing it to continue execution of other programs.
  • the I/O processor can report the status through some pre-defined mechanisms upon the completion of command execution.
  • the dedicated I/O processor approach is inherently costly.
  • the present invention provides a virtual I/O processor which achieves the aims and desired results described earlier.
  • a computer system with programmed I/O capability having a programmable input/output (I/O) unit for accessing an I/O device, an interrupt triggering mechanism for triggering an interrupt to interrupt execution of a processor, said interrupt being asserted by said programmable I/O unit at the end of an access of an I/O device, said computer system being characterized by: an interrupt handler, executed by said processor and responsive to the assertion of said interrupt, adapted to perform control and data management functions for a sequence of programmed I/Os being performed by repetitively using said programmable I/O unit, said interrupt triggering mechanism, and said interrupt handler.
  • I/O input/output
  • the desired results of supporting programmed I/O without wasting a lot of CPU cycles, nor incurring expensive hardware cost, are advantageously achieved by implementing a virtual I/O processor (VIOP), using a programmed I/O (PIO) unit.
  • the PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures.
  • the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations.
  • these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.
  • the VIOP handler automatically reinvokes the PIO unit if the sequence of programmed I/Os has not been completed.
  • the PIO unit performs actual non-blocking I/O read/write accesses against the target I/O devices.
  • the VIOP interrupt and its handler facilitate returns from the PIO unit at the completion of I/O accesses by the PIO unit.
  • Each VIOP data structure facilitates control and data management for a sequence of programmed I/Os.
  • the VIOP handler maintains the VIOP data structures accordingly. In one embodiment, the VIOP handler automatically reinvokes the PIO unit if the sequence of programmed I/Os has not been completed.
  • the preferred set of dedicated I/O global registers facilitate the transfer of I/O data between system memory and the PIO unit, as well as the performance of the programmed I/O control and data management functions.
  • the preferred VIOP library read/write routines perform programmed I/Os against target I/O devices of various device types, using the PIO unit and its complimentary facilities.
  • Application programs selectively invoke the appropriate VIOP library read/write routines to perform read/write accesses against the I/O devices.
  • the VIOP library read/write routines are responsible for repetitively invoking the PIO unit if the sequence of programmed I/Os has not been completed.
  • FIGURE 1 is an exemplary computer system incorporating the teachings of the present invention.
  • FIGURE 2a illustrates the relevant portions of one embodiment of the execution unit of Figure 1 in further detail, in particular, the preferred I/O global registers of the present invention.
  • FIGURE 2b illustrates an exemplary VIOP interrupt entry in the interrupt receive buffer of Figure 1 .
  • FIGURE 3 illustrates the relevant portions of one embodiment of the PIO unit of Figure 1 in further detail.
  • FIGURE 4 illustrates the key software elements and their relationships to each other, in particular, the VIOP interrupt handler and the VIOP data structures.
  • Figure 4 also illustrates the VIOP library read/write routines, and the non-block read/write statements.
  • FIGURE 5 illustrates one embodiment of the VIOP data structures in further detail.
  • FIGURE 6 illustrates the method steps of the present invention for performing a sequence of programmed I/Os for a read operation.
  • FIGURE 7 illustrates the method steps of the present invention for performing a sequence of programmed I/Os for a write operation.
  • the exemplary computer system 10 comprises a processor 11 including an instruction prefetch and dispatch unit (PDU) 12 , a load/store unit (LSU) 14 , and an execution unit (EU) 16 incorporated with the teachings of the present invention, coupled to each other as shown.
  • the processor 11 further includes an instruction cache (i-cache) 18 , a data cache (d-cache) 22 , a memory management unit (MMU) 20 , and a bus interface 24 , coupled to each other, the PDU 12 , the LSU 14 , and the EU 16 as shown.
  • the computer system 10 comprises a system interconnect 13 and an I/O controller 15 including a bus interface 25 , a programmed I/O unit (PIO) 26 of the present invention, an interrupt generator 27 and DMA control 29 .
  • PIO programmed I/O unit
  • instructions are fetched from the system memory (not shown), stored in the instruction cache 18 , and dispatched to the LSU 14 and EU 16 for execution.
  • the execution results are stored back into the data cache 22 , and if applicable, to the system memory.
  • I/O devices (not shown) are accessed through the I/O controller 15 .
  • Some I/Os are performed by programmed I/Os using the PIO unit 26 of the present invention.
  • the PIO unit 26 performs the actual I/O accesses against the I/O devices (not shown) for programmed I/Os, and cooperates with a VIOP interrupt and a VIOP interrupt handler of the present invention, which will be described in more detail below.
  • the PIO unit 26 can be built at a relatively low cost in terms of both circuitry and real estate required. Additionally, the present invention may be practiced with one or more PIO units 26 .
  • the EU 16 comprises conventional elements such as a number of control and state registers 32 and 34 , an integer and a floating point execution unit 28 and 30 , an integer and a floating point register file 40 and 42 , and an interrupt receive buffer 36 . Additionally, in accordance to the present invention, the EU 16 preferably comprises a number of dedicated I/O global registers 38 .
  • the interrupt receive buffer 36 stores received interrupts, including VIOP interrupts 37 of the present invention.
  • VIOP interrupts are used by the PIO unit 26 to transfer execution to a VIOP interrupt handler.
  • a VIOP interrupt 37 includes a PC 39 denoting the starting address of the VIOP interrupt handler, a pointer 41 to a VIOP descriptor and optionally, data just read from an I/O device, if the VIOP interrupt 37 was triggered as a part of a programmed read I/O. Alternatively, a pointer to be resolved indirectly, for example through a trap base register, may be used instead of PC 39 .
  • VIOP interrupt 37 , VIOP interrupt handler, and VIOP descriptor will all be described in more detail below.
  • the preferred dedicated I/O global registers 38 facilitate I/O data transfers between the system memory and the PIO unit 26 as well as performance of control and data management functions for a sequence of programmed I/Os, which will be described in more detail below. As will be appreciated by those skilled in the art, the dedicated I/O global registers 38 are preferred for performance reasons. The provision of the dedicated I/O global registers 38 avoids having to spill a portion of the current content of the register files 40 and 42 to facilitate the above described I/O data transfers and performance of management functions.
  • the PIO unit 26 comprises a sequencer 50 , a number of data buffers 48 , and a number of control and status registers 46 , and non-blocking read/write control circuitry 44 coupled to each other as shown.
  • the sequencer 50 executes a pre-defined sequence of operations for performing actual I/O accesses against an I/O device, after the PIO unit 26 has been allocated and properly initialized.
  • the non-blocking read/write control circuitry 44 controls the actual non-blocking read/write from/to an I/O device. Additionally, the sequencer 50 asserts the VIOP interrupt at the completion of each I/O access.
  • the data buffers 48 buffer the I/O data being transferred by the programmed I/Os to and from the I/O device.
  • the control and status registers 46 store current control and status information of the PIO unit 26 . Allocation and initialization of the PIO unit 26 , transfer of data between the data buffers 48 and the dedicated I/O global registers 38 , as well as assertion and servicing of the VIOP interrupt will also be described in more detail below.
  • the key software elements include a VIOP interrupt handler 116 and a number of VIOP data structures 118 .
  • the VIOP interrupt handler 116 in cooperation with the VIOP interrupt facilitate returns from the PIO unit 26 at the completion of actual I/O accesses performed by the PIO unit 26 .
  • the VIOP interrupt handler 116 is invoked and given execution control through the VIOP interrupt, as described earlier.
  • the VIOP interrupt handler 116 performs control and data management functions for programmed I/Os utilizing the VIOP data structures 118 .
  • the VIOP interrupt handler 116 also automatically reinvokes the PIO unit 26 if a series of programmed I/Os has not been completed.
  • the VIOP data structures 118 facilitates the control and data management functions performed by the VIOP handler 116 .
  • One VIOP data structure 118 is used for each sequence of programmed I/Os.
  • Each VIOP data structure 118 comprises a VIOP descriptor 122 and a VIOP data buffer 124 .
  • the VIOP descriptor 122 holds the control information for a sequence of programmed I/Os, whereas, the VIOP data buffer 124 holds the actual I/O data being transferred by the sequence of programmed I/Os between the system memory and the I/O devices.
  • a VIOP descriptor 122 comprises a VIOP data buffer pointer 126 , an I/O word count 128 , an I/O device address 130 , and a VIOP address 132 .
  • the VIOP data buffer area pointer 126 points to a location in the VIOP data buffer area 124 where the next group of programmed I/O data are to be read or written.
  • the I/O word count 128 keeps track of the amount of I/O data remains to be transferred by the programmed I/Os between the system memory and the target I/O device.
  • the device address 130 points to the target I/O device against which the programmed I/Os are performed.
  • the VIOP address 132 denotes the address of a PIO unit 26.
  • the software elements further include a number of VIOP library read-write routines 112 and 114.
  • the VIOP library 110 contains VIOP read and write routines 112 and 114 perform programmed I/Os against I/O devices of various device types, using the above described PIO unit 26 and its complementary facilities.
  • Application programs 102 invoke VIOP library read/write routines 112 and 114 to access I/O devices.
  • the VIOP read/write routine 112 or 114 automatically reinvokes the PIO unit 26 if a series of programmed read/write I/Os has not been completed.
  • the VIOP read and write routines 112 and 114 may be statically linkedited as integral parts of an application program 102, or they may be dynamically loaded during execution.
  • the application program 102 contains a routine for invoking a read/write 104. Additionally, a data structure 106 is used for the data transfer area 108.
  • the VIOP library read routine 112 allocates a VIOP descriptor 122 and a VIOP data buffer area 124 in the system memory.
  • the VIOP library read routine 112 initializes the VIOP descriptor 122 with a VIOP data buffer pointer 126 pointing to the VIOP data buffer area 124 , and an I/O word count 128 denoting the amount of I/O data to be read from the target I/O device.
  • the VIOP library read routine 112 initializes the VIOP descriptor 122 with an I/O device address 130 locating the target I/O device where the I/O data are to be read, and an VIOP address 132 locating the PIO unit 26 for performing the programmed read I/Os.
  • the VIOP library read routine 112 allocates the PIO unit 26 and initializes the PIO unit 26 with the proper control information, such as the device address of the target I/O device.
  • the VIOP library read routine 112 starts VIOP by issuing a non-blocking PIO read 206 .
  • a non-blocking read/write instruction is a read/write instruction where the processor does not wait for the completion of the read/write operation initiated on behalf of the read/write instruction, before proceeding to execute other instructions.
  • the PIO unit 26 makes an actual I/O access against the target I/O device and reads a predetermined quantity of data from the target I/O device.
  • the PIO unit 26 repeats the access against the target I/O device until the PIO data buffer 48 is full or the PIO unit 26 has read all the data as instructed by the VIOP library read routine 112 , step 210 . If the PIO unit 26 detects either one of these conditions, at step 212 , the PIO unit 26 stops accessing the target I/O device, and generates a VIOP interrupt 37 instead.
  • the VIOP interrupt 37 is delivered to the processor 11 through the system interconnect 15 .
  • the processor 11 stores the VIOP interrupt 37 in its Interrupt Receive Buffer 36 .
  • the processor 11 Upon detecting the VIOP interrupt, the processor 11 transfers execution control to the VIOP interrupt handler 116 .
  • the VIOP interrupt handler 116 upon given execution control, obtains the VIOP descriptor address from the Interrupt Receive Buffer 36 , step 214 .
  • the VIOP interrupt handler 116 loads the VIOP descriptor 122 into the dedicated I/O global registers 38 .
  • the VIOP interrupt handler 116 then moves the read data from the Interrupt Receive Buffer 36 to the dedicated I/O global registers 38 , step 218 , and then into the VIOP buffer 124 , step 220 .
  • the VIOP interrupt handler 116 Upon moving the read data from the dedicated I/O global registers 38 , the VIOP interrupt handler 116 updates and saves the VIOP descriptor 122 , in particular, the VIOP data buffer pointer 126 , and the I/O word count 128 denoting the amount of I/O data remaining to be read 128 , step 222 .
  • the VIOP interrupt handler 116 determines if the I/O word count 128 has reached zero denoting completion of the sequence of programmed read I/Os, step 224 . If I/O word count 128 is non-zero, VIOP interrupt handler 116 automatically reinvokes the PIO unit 26 again by issuing a non-blocking PIO read 228 , which in turn repeats steps 208 through 212 as described earlier. Eventually, the VIOP interrupt handler 116 will determine at step 224 that the I/O word count has reached zero.
  • the VIOP interrupt handler 116 transfers execution control to the VIOP library read routine 112 , which in turn performs a block move, moving the read data from the VIOP data buffer 124 to the application program's data transfer area 108 , step 226 .
  • the present invention may be practiced with the VIOP interrupt handler 116 returning to the VIOP library read routine 112 after step 222 , and have the VIOP library read routine 112 be responsible for reinvoking the PIO unit 26 if the sequence of programmed read I/Os has not been completed.
  • the VIOP library write routine 114 allocates a VIOP descriptor 122 and a VIOP data buffer 124 in the system memory.
  • the VIOP library write routine 112 initializes the VIOP descriptor 122 with a VIOP data buffer pointer 126 pointing to the VIOP data staging area 124 , and an I/O word count 128 denoting the amount of I/O data to be written into the target I/O device.
  • the VIOP library write routine 112 initializes the VIOP descriptor 122 with an I/O device address 130 locating the target I/O device where the I/O data are to be written, and an VIOP address 132 locating the PIO unit 26 for performing the programmed write I/O.
  • the VIOP library write routine 114 block moves the I/O data from the application program's data transfer area 108 to the VIOP data buffer area 124 .
  • the VIOP library write routine 114 further loads portions of the write data from the VIOP data buffer area 124 into the dedicated I/O global registers 38 , step 250 .
  • the VIOP library write routine 114 allocates the PIO unit 26 and initializes the PIO unit 26 with the proper control information, such as the device address of the target I/O device, step 252 .
  • the VIOP library write routine 114 moves the write data from the I/O global registers 38 to the PIO data buffers 48 by issuing a non-blocking PIO write, step 254 .
  • the PIO unit 26 makes an actual I/O access against the target I/O device and writes a predetermined quantity of data to the target I/O device.
  • the PIO unit 26 repeats the access against the target I/O device until the PIO data buffer 48 is empty or the PIO unit 26 has written all the data as instructed by the VIOP library write routine 114 , step 258 . If the PIO unit 26 detects either one of these conditions, at step 260 , the PIO unit 26 stops accessing the target I/O device, and generates a VIOP interrupt 37 instead, step 260 .
  • the VIOP interrupt 37 is delivered to the processor 11 through the system interconnect 15 . Upon receiving the interrupt, the processor 11 stores the VIOP interrupt 37 in its Interrupt Receive Buffer 36 .
  • the processor 11 Upon detecting the VIOP interrupt 37 , the processor 11 transfers execution control to the VIOP interrupt handler 116 .
  • the VIOP interrupt handler 116 upon given execution control, obtains the VIOP descriptor address from the Interrupt Receive Buffer 36 , step 262 .
  • the VIOP interrupt handler 116 loads the VIOP descriptor 122 into the dedicated I/O global registers 38 .
  • the VIOP interrupt handler 116 then updates and saves the VIOP descriptor 122 , in particular, the VIOP data staging area pointer 126 , and the I/O word count 128 denoting the amount of I/O data remaining to be written, step 266 .
  • the VIOP interrupt handler 116 determines if the I/O word count 128 has reached zero, denoting the programmed write I/O has been completed, step 268 . If the I/O word count 128 has not reached zero, the VIOP interrupt handler 116 loads additional portions of write data into the I/O global registers 38 , step 270 , and then to the PIO data buffers 48 by issuing a non-blocking PIO write, step 272 . Upon moving the write data to the PIO data buffers 48 , VIOP interrupt handler 116 automatically reinvokes the PIO unit 26 , which repeats steps 256 - 260 as described earlier. Eventually, the VIOP interrupt handler 116 will determine at step 268 that the I/O word count 128 has reached zero.
  • the present invention may be practiced with the VIOP interrupt handler 116 returning to the VIOP library write routine 114 after step 266 , and have the VIOP library write routine 114 be responsible for reinvoking the PIO unit 26 if the sequence of programmed write I/Os has not been completed.

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Claims (19)

  1. Système d'ordinateur (10) à capacité E/S programmée ayant une unité d'entrée/sortie (E/S) programmable (26) pour solliciter un périphérique E/S, un mécanisme de déclenchement d'interruption adapté pour déclencher une interruption (37) en vue d'interrompre l'exécution d'un processeur (11), ladite interruption étant activée par ladite unité E/S programmable (26) à la fin d'une sollicitation d'un périphérique E/S, ledit système d'ordinateur étant caractérisé par :
       un gestionnaire d'interruption (116), exécuté par ledit processeur (11) et sensible à l'activation de ladite interruption, adapté en vue d'effectuer des fonctions de commande et de gestion de données pour une séquence d'E/S programmées exécutées en utilisant de manière répétée ladite unité E/S programmable (26), ledit mécanisme de déclenchement d'interruption, et ledit gestionnaire d'interruption.
  2. Système d'ordinateur selon la revendication 1, dans lequel ladite unité E/S programmable (26) comprend :
    (a.1) un séquenceur (50) couplé au mécanisme de déclenchement d'interruption adapté en vue d'exécuter une séquence prédéfinie d'opérations pour solliciter un périphérique E/S, et activer ladite interruption à la fin d'une sollicitation d'un périphérique E/S ;
    (a.2) une mémoire tampon de données (48) couplée au séquenceur (50), au périphérique E/S et au mécanisme de déclenchement d'interruption adaptée pour mettre en mémoire tampon des données E/S transférées depuis et vers un périphérique E/S ;
    (a.3) une pluralité de registres (46) couplés à une interface de bus et audit séquenceur (50) adaptés en vue de mémoriser des informations de commande et d'état de ladite unité E/S programmable (26) ; et
    (a.4) des circuits de commande de lecture/écriture non bloquants (44) couplés au séquenceur (50) et au périphérique E/S adaptés en vue de commander des transferts de données entre la mémoire tampon de données et le périphérique E/S.
  3. Système d'ordinateur selon la revendication 1, dans lequel ledit gestionnaire d'interruption est adapté en vue d'effectuer ladite fonction de commande et de gestion de données pour une séquence d'E/S programmées en utilisant une structure de données (118) comprenant un bloc descripteur (122) et une mémoire tampon de données (124) ; et
       ledit bloc descripteur comprend (c.1) un pointeur (126) pointant dans ladite mémoire tampon de données indiquant où lire ou écrire ensuite des données E/S.
  4. Système d'ordinateur selon la revendication 3, dans lequel ledit bloc descripteur comprend en outre (c.2) un compte de mots de données E/S (128) indiquant une quantité de données E/S qu'il reste à lire ou à écrire pour une séquence d'E/S programmées.
  5. Système d'ordinateur selon la revendication 4, dans lequel ledit bloc descripteur comprend en outre :
    (c.3) une première adresse (130) localisant le périphérique E/S ; et
    (c.4) une deuxième adresse (132) pour localiser l'unité E/S programmée (26).
  6. Système d'ordinateur selon la revendication 1, dans lequel ledit système d'ordinateur comprend en outre une pluralité de registres dédiés (38) couplés à ladite unité E/S programmable (26) adaptés en vue de mémoriser des données E/S transférées depuis ou vers un périphérique E/S par ladite unité E/S programmable (26), et adaptés en vue de mémoriser des données de gestion de commande sur lesquelles agit ledit gestionnaire d'interruption pour une séquence d'E/S programmées.
  7. Système d'ordinateur selon la revendication 1, dans lequel ledit système d'ordinateur comprend en outre :
    un sous-programme de lecture (112) adapté en vue d'effectuer une séquence d'E/S programmées pour une opération de lecture effectuée en association avec un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption (37) et gestionnaire d'interruption (116) ; et
    un sous-programme d'écriture adapté en vue d'effectuer une séquence d'E/S programmées pour une opération d'écriture effectuée en association avec un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption (37) et gestionnaire d'interruption (116).
  8. Système d'ordinateur selon la revendication 7, dans lequel ledit système d'ordinateur comprend en outre :
    une opération de lecture non bloquante adaptée en vue de lire à partir d'un périphérique E/S ;
    une opération d'écriture non bloquante adaptée en vue d'écrire dans un périphérique E/S ;
    dans lequel, lesdits sous-programmes de lecture et d'écriture, lorsqu'ils sont appelés par un programme d'application, sont adaptés en vue d'utiliser lesdites opérations de lecture et d'écriture non bloquantes en vue de lire à partir de, et d'écrire dans, un périphérique E/S.
  9. Système d'ordinateur selon la revendication 1, dans lequel,
    ladite unité E/S programmable (26) est disposée dans un contrôleur E/S (15) ; et
    ledit processeur (11) comprend en outre une unité d'exécution de nombres entiers (28) adaptée en vue d'exécuter des instructions de nombres entiers, un fichier de registre de nombres entiers (40) couplé à ladite unité d'exécution de nombres entiers, adapté en vue de mémoriser des résultats d'exécution de nombres entiers, et une pluralité de registres de commande et d'état adaptés en vue de mémoriser des informations de commande et d'état dudit processeur (11).
  10. Système d'ordinateur selon la revendication 9, dans lequel
       ledit système d'ordinateur comprend en outre une interconnexion de système (13) couplée audit processeur (11) pour transférer des instructions et des données, une mémoire système couplée à ladite interconnexion de système pour mémoriser des instructions et des données, et un périphérique E/S couplé à ladite interconnexion de système pour fournir des données E/S audit processeur (11).
  11. Procédé mis en oeuvre par ordinateur pour fournir une capacité E/S programmée, contenant les étapes de :
    (a) sollicitation d'un périphérique E/S par une unité E/S programmable (26) pour lire à partir de ou écrire dans ledit périphérique E/S ;
    (b) interruption de l'exécution d'un processeur (11) par ladite unité E/S programmable (26) à la fin d'une sollicitation contre ledit périphérique E/S en utilisant un mécanisme de déclenchement d'interruption ;
       caractérisé par le fait qu'il contient l'étape supplémentaire de
       (c) réponse à ladite interruption (37) par ledit gestionnaire d'interruption (116) exécuté par ledit processeur (11) en vue d'effectuer des fonctions de commande et de gestion de données pour une séquence d'E/S programmées effectuées en utilisant de manière répétée ladite unité E/S programmable (26), ledit mécanisme de déclenchement d'interruption et ledit gestionnaire d'interruption.
  12. Procédé selon la revendication 11, dans lequel :
       ladite performance des fonctions de commande et de gestion de données par ledit gestionnaire d'interruption à ladite étape (c) comprend en outre le maintien d'informations de données de commande dans un bloc descripteur (122) et une mémoire tampon de données (124) d'une structure de données (118), comportant le maintien d'un pointeur dans ledit bloc descripteur pointant dans ladite mémoire tampon de données pour indiquer où des données E/S doivent ensuite être lues ou écrites.
  13. Procédé selon la revendication 12, dans lequel ledit maintien d'informations de données de commande dans ladite structure de données comporte en outre :
    le maintien d'un compte de mots de données E/S (128) dans ledit bloc descripteur indiquant une quantité de données E/S qu'il reste à lire ou à écrire pour une séquence d'E/S programmées ;
    le maintien d'une première adresse localisant le périphérique E/S ; et
    le maintien d'une deuxième adresse localisant l'unité E/S programmée (26) .
  14. Procédé selon la revendication 11, dans lequel ladite étape (a) comprend en outre :
       l'appel d'un sous-programme de lecture (112) à partir d'un programme d'application (102) pour effectuer une séquence d'E/S programmées contre un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption et gestionnaire d'interruption.
  15. Procédé selon la revendication 11, dans lequel ladite étape (a) comprend en outre :
       l'appel d'un sous-programme d'écriture (114) à partir d'un programme d'application (102) pour effectuer une séquence d'E/S programmées contre un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption et gestionnaire d'interruption.
  16. Procédé selon la revendication 11, dans lequel ladite étape (a) comprend les étapes de :
    fourniture d'un séquenceur (50) couplé à un mécanisme de déclenchement d'interruption pour exécuter une séquence prédéfinie d'opérations pour solliciter un périphérique E/S, et activer une interruption à la fin d'une sollicitation du périphérique E/S ;
    fourniture d'une mémoire tampon de données (48) couplée au séquenceur (50) et au mécanisme de déclenchement d'interruption pour mettre en mémoire tampon des données E/S transférées depuis et vers le périphérique E/S ;
    fourniture d'une pluralité de registres (46) couplés à une interface de bus et audit séquenceur (50) pour mémoriser des informations de commande et d'état de ladite unité E/S programmable (26) ; et
    fourniture de circuits de commande de lecture-écriture non bloquants (44) couplés au séquenceur (50) et au périphérique E/S, ledit périphérique E/S étant couplé aux mémoires tampons de données, lesdits circuits de commande de lecture-écriture non bloquants (44) commandant des transferts de données entre la mémoire tampon de données et le périphérique E/S.
  17. Procédé selon la revendication 11, dans lequel ledit procédé comprend en outre l'étape de fourniture d'une pluralité de registres dédiés (38) couplés à ladite unité E/S programmable (26) pour mémoriser des données E/S transférées depuis ou vers un périphérique E/S par ladite unité E/S programmable (26), et pour mémoriser des données de gestion de commande sur lesquelles agit ledit gestionnaire d'interruption pour une séquence d'E/S programmées.
  18. Procédé selon la revendication 11, dans lequel ledit procédé comprend en outre les étapes de :
    fourniture d'un sous-programme de lecture (112) pour effectuer une séquence d'E/S de lecture programmées contre un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption et gestionnaire d'interruption ; et
    fourniture d'un sous-programme d'écriture (114) pour effectuer une séquence d'E/S d'écriture programmées contre un périphérique E/S en utilisant lesdits unité E/S programmable (26), interruption et gestionnaire d'interruption.
  19. Procédé selon la revendication 18, dans lequel ledit procédé comprend en outre les étapes de :
    fourniture d'une opération de lecture non bloquante pour lire à partir d'un périphérique E/S ; et
    fourniture d'une opération d'écriture non bloquante pour écrire dans un périphérique E/S ;
    dans lequel, lesdits sous-programmes de lecture et d'écriture, lorsqu'ils sont appelés par un programme d'application, utilisent lesdites opérations de lecture et d'écriture non bloquantes en vue de lire à partir de, et d'écrire dans, un périphérique E/S.
EP96301490A 1995-03-13 1996-03-05 Processeur d'entrée/sortie virtuelle Expired - Lifetime EP0732658B1 (fr)

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US40287395A 1995-03-13 1995-03-13
US402873 1995-03-13

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SG79185A1 (en) 2001-03-20
US5727219A (en) 1998-03-10
KR960035230A (ko) 1996-10-24
EP0732658A1 (fr) 1996-09-18
JPH0926928A (ja) 1997-01-28
DE69610450T2 (de) 2001-04-26
DE69610450D1 (de) 2000-11-02
KR100392326B1 (ko) 2003-10-23

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