EP0705465B1 - Configurable analog and digital array - Google Patents

Abstract

A configurable analog and digital array is produced in hierarchical structure in at least two planes. It comprises at least two first-order matrix arrangements, each having a plurality of basic units in rows and/or columns which are at least partly analog basic units, and a first switch matrix for the controllable mutual connection of the signal inputs and outputs of the basic units and for the connection thereof with matrix inputs and outputs, and at least one second-order matrix arrangement having a second switch matrix for the controllable mutual connection of the matrix inputs and outputs of the first-order matrix arrangements and for the controllable connection thereof with array inputs and outputs.

Description

The present invention relates to a configurable, analog and digital array. In other words, the subject matter of the invention relates to a configurable analog / digital module array.

User programmable circuits in the form of configurable arrays have been known for a number of years. The customary programmable circuits on the market are designed as configurable digital arrays. Such user-programmable circuits therefore mainly cover the area of digital applications. It is common to such digital, user-programmable circuits that a plurality of cells are provided at gate level or register level, which can be programmed by the user and variably connected via pre-configured connection paths.

In the case of such user-programmable circuits, a particular problem is the decision for the “correct” module for the respective application, since the systems are very different and it is difficult to switch from one system to another.

Frequently, such user-programmable circuits are only used to check a circuit design, and after the final circuit version has been determined, it must be converted into a so-called "full customer circuit". Such an implementation is over with one prototypes existing in several different building blocks are generally not readily possible and generally require a so-called redesign.

So far, there is no corresponding counterpart for the analogue range that could be used as universally as user-programmable digital circuits in the form of configurable digital arrays. There are only a few special modules, such as filters, which can be programmed or trimmed by the user by means of appropriate wiring. There are also integrated arrays with analog components or cells for user-specific wiring. This wiring must be done at the manufacturer via an aluminum mask and can therefore not be done by the customer himself. European patent application EP-0499383A2 shows a user-programmable integrated circuit with an analog section with user-configurable analog circuit modules, a digital section with user-configurable digital circuit modules and an interface section with user-configurable interface circuits for analog / digital signal conversion and for digital / analog signal conversion, and a user configurable Connection and input / output architecture. The networking of the elements made possible by such a circuit is extremely limited. For example, no feedback between circuit elements is possible. In this known circuit, only existing base blocks and signal paths are multiplexed, which can only be changed according to narrowly limited possibilities. The known circuit can be programmed and controlled by wiring solid basic components with other components, as is shown, for example, in FIGS. 3a, 3b of this document. For example, resistors and capacitors can be connected to existing circuit blocks. A hierarchical structuring and organization that enables the construction of completed analog subsystems for subsequent configuration within an overall system, is not possible with this known technique.

DE-3417670A1 shows a programmable analog circuit in the form of a programmable filter, in which a number of filter modules, an attenuator and an isolation amplifier can be interconnected in a user-programmable manner. Here, too, however, there is only a very limited variation of a fixed basic circuit structure.

From DE-3615981A1 a system for parameter-programmable processing of audio signals in combination with a programmable switching matrix is known, which is used in the field of analog and digital processing of audio signals. However, this system cannot be implemented at the chip level, but only at the circuit board level.

US-A-4,847,612 shows a configurable array, with at least two first-order matrix arrangements, with a plurality of basic components arranged in rows and / or columns and a first switch matrix, and at least one second-order matrix arrangement with a second switch matrix, which comprises the at least two matrix arrangements connects first order, in which all the basic components are digital and the outputs are coupled via the first-order matrix arrangements.

The publication E. Price, "Digital and Analog on a Chip", Electronics, Vol. 36, No. 10, May 15, 1987, Munich, describes a mixed analog / digital CMOS standard cell. In this known standard cell, analog / digital functional elements are connected by two fixed wiring levels.

Starting from this prior art, the present invention is therefore based on the object of creating a configurable, analog and digital array with which a complete system with analog and possibly digital basic components can be configured largely freely by the user.

This object is achieved by a configurable analog and digital array according to claim 1.

The configurable analog and digital array according to the invention comprises a hierarchical structure with at least two first-order matrix arrangements and at least one second-order matrix arrangement.

Each of the first-order matrix arrangements has a plurality of basic modules arranged in rows or columns, which are at least partially analog basic modules, and has a first switch matrix for controllable mutual connection of the signal inputs and / or the signal outputs of the basic building blocks and for the controllable connection thereof to matrix inputs and / or matrix outputs of this first-order matrix arrangement. The second-order matrix arrangement comprises a second switch matrix for the controllable mutual connection of the matrix inputs and / or matrix outputs of the first-order matrix arrangement and for the controllable connection thereof to array inputs and / or array outputs.

The system defined in this way can include controllable analog and digital function blocks of different architectures and levels of complexity in the form of an integrated circuit on a common substrate in such a way that the existing sub-modules or basic modules can be flexibly and reversibly interconnected and form a largely arbitrarily predefinable overall system for the mixed analog / digital signal processing can be configured. This system therefore forms a "building block" with a certain basic quantity of basic building blocks in the form of analog and digital blocks, which can be parameterized and thus modified and which can be interconnected or configured to form an overall system within certain limits.

In addition to their signal input and their signal output, the basic modules preferably have an analog and / or digital control input. Certain properties of the basic building blocks can thus be varied, ie parameterized, within specified limits. The signals for the analog and digital control input of a basic module are programmed into writable, readable and erasable memory elements, which serve as parameterization registers and which are located directly on the basic modules, and can be reset or deleted there at any time. In the case of a basic module in the form of an amplifier, properties such as its amplification factor, its bandwidth, its power loss, its offset etc. can be set as required will.

A first-order matrix arrangement can optionally contain a multiplying digital / analog converter, to which a binary data word can be fed from such a parameterization register, so that the digital / analog converter generates an analog control signal on the output side, with which the analog control input of the basic module is controlled can.

In this embodiment, the configuration of basic modules to form an overall system is carried out by controlling the analog and digital control inputs of the basic module and by controlling switches of the first and second matrix arrangement via the matrix inputs and the array inputs.

A shift register is preferably provided, into which the data for the configuration can be read in serially and which forms the parameterization registers.

In the case of a different configuration, a parallel interface can be provided which enables the configuration data to be introduced in parallel into the array. In any case, a host computer can be used to generate the configuration data to generate the control data.

In a further advanced implementation, a microcontroller can also be provided on a chip, which takes over the routing (setting of the configuration registers), whereby it receives information supplied from outside in the form of e.g. evaluates a network list. This can also be buffered in a separate area (RAM, EPROM or similar).

Between the basic components and between the first-order matrix arrangements formed by the basic components, there is a large number of switchable connections, which allow the basic components to be largely wired to one another. Since both the input lines and the output lines of the basic components are routed within the matrix-like arrangements, a feedback structure can also be formed from basic components within the first-order matrix arrangement.

The first-order circuit arrangement formed by the basic components within the first-order matrix arrangement can be assembled into a practically freely selectable overall system by means of the second-order or higher-order matrix arrangement.

The hierarchical structure according to the invention of the configurable array consisting of first-order matrix arrangements and at least one second-order matrix arrangement allows both the testability of the individual basic components and the testability of the configured system by means of measures which are inherently common in the field of digitally configurable arrays. For this purpose, all combinatorial logic functions in digital structures are designed as minimalized functions and are therefore fully testable. There are registers between the combinatorial logic components, which are interconnected via a scan path. Programmable signature registers and a boundary scan path can also be provided.

With analog structures, the observability of special internal nodes of the overall system is provided. This can be done, for example, by means of switchable decoupling elements (e.g. amplifiers), which in turn can optionally be switched to an output pin or an analog basic module. This should lead to a measurement which is essentially load-free for the network node. Likewise, the array structure according to the invention enables certain internal module connections to be separated and internal nodes to be set via external chips Inputs or module outputs. The variable design of the array according to the invention enables the configuration of test systems which carry out an on-chip test and, with a suitable constellation, extensively check the functionality of the overall system. Mixed analog / digital parts can also be included in such self-test systems.

According to a special feature of the invention, at least some of the basic modules are assigned a qualification register which is designed as a read / write memory or as a read-only memory and contains at least information about the total failure of the basic module and possibly information about the operating properties of the basic module. In this embodiment of the array according to the invention, an extraction of component and circuit parameters for each individual chip on which the array is implemented can be carried out after the function test by means of special configuration measures. The results of this parameter extraction are then built into parameterizable functional macro models and used in all further simulations. This makes it possible to largely compensate for parameter variations in the component and circuit parameters caused by process fluctuations individually by adapting the simulation environment. A characterization plan for specific circuit properties can then be drawn up for each chip, which can be used by the configuration software as the basis for qualifying each circuit part for specific tasks. For this purpose, a unique identification code can be stored on each chip. This can be done, for example, in the form of a PROM area that is burned by the user, i.e. can be described as a read-only memory.

By assigning a qualification register to each of the basic modules, information about the functionality of the basic modules can be stored. As mentioned, Such a qualification within the qualification register includes, for example, information about the total failure of the basic building block or features about other properties. On the one hand, this information can be determined by the manufacturer during testing and provided in the qualification registers, so that the chip yield can be increased. Since each module type occurs several times on the chip, there is sufficient redundancy. On the other hand, the qualification can also be carried out by the user at any time. This enables flexible qualification depending on the application. However, this procedure also makes it possible to localize failures that have occurred during operation, to mark them and to avoid them by reconfiguring the system, taking into account all qualification registers. This aspect increases the reliability of the system, since it is possible to "repair" the system on site without having to intervene in the hardware.

According to a special aspect of the invention, those modules that are not statically lossless, such as amplifiers, interface circuits, etc., can be separated from the operating voltage via a power cut-off input. This configuration makes it possible to deselect unused or defective basic components and thus to reduce the power loss of the overall system. In view of the fact that often only a small part of the basic components of such an array is used for the configuration of a specific user-specific circuit, this aspect can be of great importance. Of course, such an input can also be controlled in certain time slots during operation to limit the power loss. A separate memory element within the basic module, which can be programmed separately, is preferably used to deselect a basic module.

The array according to the invention supplies adaptive systems. The configured system can deliver output signals that modify the system itself in a certain way, ie reconfigure it automatically. This can be done, for example, by changing the programmable wiring or by changing the module properties. With a suitable design, the arrangements can be modified in real time.

The array according to the invention is preferably implemented in BICMOS technology. This technology is particularly suitable because, on the one hand, it has the ability to perform high-quality analog functions through bipolar components and, on the other hand, it allows maximum integration through low-loss CMOS technology. In addition, the concept of flexible interconnection requires good driver properties, the driver having to react flexibly to the load capacities. In principle, however, a solution in CMOS technology or in another technology suitable for large-scale integration is also conceivable.

The transfer of a prototype, which is configured on the array according to the invention, to an optimized circuit for larger quantities can be accomplished in a simple manner in that the data determined during the configuration together with the analog and digital library elements form the desired overall system in one suitable CAD environment, whereby unused elements are omitted and the additions for wiring and programmability, such as multiplexers and registers, are replaced by fixed wiring. Since the entire system was already completely replicated within the configurable module array according to the invention, the problem of a transition to other modules does not arise with the technology according to the invention.

The analog basic components of the array according to the invention include, for example, integrators, comparators, amplifiers, phase detectors and adjustable references. The adjustable references can be realized by multiplying digital-to-analog converters.

Fig. 1

ein durch Grundbausteine innerhalb der Matrixanordnung erster Ordnung gebildetes Schleifenfilter zweiter Ordnung;

Fig. 2

einen durch Grundbausteine innerhalb der Matrixanordnung erster Ordnung gebildeten Phasendetektor;

Fig. 3

eine aus den Schaltungen nach den Fig. 1 und 2 durch die Matrixanordnung zweiter Ordnung gebildete Frequenz-gerastete Regelschleife (FLL);

Fig. 4

einen steuerbaren Transkonduktanzverstärker;

Fig. 5

eine minimale Ausführungsform eines erfindungsgemäßen Arrays;

Fig. 6

eine Darstellung eines von der Matrixanordnung erster Ordnung des erfindungsgemäßen Arrays gebildeten Schleifenfilters zweiter Ordnung;

Fig. 7

einen von der Matrixanordnung erster Ordnung des erfindungsgemäßen Arrays gebildeten Phasendetektor; und

Fig. 8

eine der Fig. 5 entsprechende Darstellung des erfindungsgemäßen Arrays bei Programmierung als Frequenz-gerastete Regelschleife.

Preferred exemplary embodiments of the configurable, analog and digital array according to the invention are explained in more detail below with reference to the accompanying drawings. Show it:

Fig. 1

a second-order loop filter formed by basic building blocks within the first-order matrix arrangement;

Fig. 2

a phase detector formed by basic building blocks within the first-order matrix arrangement;

Fig. 3

a frequency-locked control loop (FLL) formed from the circuits according to FIGS. 1 and 2 by the second-order matrix arrangement;

Fig. 4

a controllable transconductance amplifier;

Fig. 5

a minimal embodiment of an array according to the invention;

Fig. 6

a representation of a second-order loop filter formed by the first-order array of the array;

Fig. 7

a phase detector formed by the first-order array of the array; and

Fig. 8

a representation of the array according to the invention corresponding to FIG. 5 when programmed as a frequency-locked control loop.

1 shows a first possible structuring within a first level of the array according to the invention, which, as will be further clarified below, is formed by a first-order matrix arrangement. This is referred to as the first level, since only basic modules I1, I2, V1 are configured within this level. The configuration shown here comprises two integrators I1, I2 or low-pass filters of the first order, which can be controlled both digitally for a coarse adjustment and analogously for a fine adjustment, and an amplifier V1 which can also be controlled. With the reference symbol Vdc; Vac are digital or analog control inputs.

2 shows a further first level of the array according to the invention, that is to say also a partial configuration of basic components, which is formed by a first-order matrix arrangement. In this exemplary circuit, two voltage comparators K1, K2 are provided, which are followed by a phase detector PD.

Fig. 3 shows the block diagram of an FLL (Frequency Locked Loop), i.e. a frequency locked loop. This circuit is formed from three blocks, each of which is formed on the first level of the digital array according to the invention, as is illustrated by FIGS. 1 and 2. Thus, the circuit shown in Fig. 3 can be referred to as a second level circuit. 3, the hierarchical structure of the analog / digital design of the entire array according to the invention is clear. Macros of the first level are formed on the basis of basic building blocks, which in turn can configure a system of the second level, whereby this can also be done in conjunction with basic building blocks from the lower levels.

The exemplary embodiment shown here is structured over two levels. It is obvious to a person skilled in the art that the concept of a hierarchical array according to the invention can be carried out over several levels.

4 shows the circuit architecture of a programmable, controllable transconductance amplifier OTA using differential path technology. This structure is intended to clarify the control options of a basic building block on behalf of the other basic building blocks. The digital setting is a rough setting. This is done by data word W2. The fine adjustment takes place starting from the data word W1 via a programmable, multiplying digital / analog converter MDAC, whereby such analog control voltages can also be provided externally. A 10-bit latch L is used for digital programming both for the coarse adjustment and for the fine adjustment. These latches L are contained in the BBB rows of the basic building blocks, which are shown in FIG. 5 and are explained in more detail below with reference to FIG. 5.

As shown, the analog fine adjustment of the basic building blocks (BBB = basic building block) can be carried out either by multiplying the analog / digital converter using the binary data word W1 or by an external analog control voltage (external or adaptive control). Both methods primarily affect transconductance.

The digital control brings about a rough digital setting by switching on or off pre-configured current and voltage references within the first-order matrix arrangements via data word W2. In this way, for example, the transconductance can also be kept programmable. Furthermore, references for dynamic adjustment can be scaled.

As shown in FIG. 5, the embodiment shown there comprises an inventive configurable analog and digital array arrangement, four matrix arrangements M ₁₁ , M ₁₂ , M ₁₃ , M ₁₄ first order and a matrix arrangement M ₂ second order. Each first-order matrix arrangement M ₁₁ , M ₁₂ , M ₁₃ , M ₁₄ comprises a plurality of basic building blocks BBB, which are shown there as BBB rows / lines 1 to 12. The connections between the basic components within the matrix arrangements M ₁₁ , M ₁₂ , M ₁₃ , M ₁₄ are made by means of first switch matrices S ₁ to S ₄ , which in the example shown can be designed as (8 x 8) switch matrices. The networking logic in connection with the switch matrix units MSU allows crossover-free connections which can be individually programmed for the first-order matrix arrangements via shift registers 13 to 16 which are m ² bit long (m = number of crossover-free connections). In order to increase the number of basic modules grouped around the matrix without providing additional connection paths, decodable line selectors can be used on the periphery, which can separate and / or connect incoming and outgoing signal / supply paths. All external connections of the matrix can be programmed as inputs or outputs or bidirectional connections. Multiplexers in the selectors allow variable signal / supply routing.

In order to achieve the greatest possible variety in the programming of the signal / supply paths, two different elementary networking states, namely the crossing and linking, can be implemented. When programming an intersection point MSU, a conductive, bidirectional connection of a horizontal and a vertical line segment is created. Further intersection points MSU can be connected to these segments, so that line segments which run in parallel can also be realized. If the selectors at the matrix edges are deactivated, these line segments end at the matrix periphery. The switching matrices are only shown without separation units. Unless otherwise shown, the signal paths in the structures shown each end at the matrix periphery.

As is also shown in FIG. 5, the second-order matrix arrangement M2 together with the first-order matrix arrangements M ₁₁ , M ₁₂ , M ₁₃ , M _{14 form} a configurable digital array with two levels. The second-order matrix arrangement M ₂ likewise comprises a switch matrix which, in the exemplary embodiment shown here, is designed as a (16 × 16) switch matrix. The vertical signal lines of this matrix are the input and output lines of the switching matrices S ₁ to S _{4 of} the first-order matrix arrangements. Horizontal lines of the switch matrix of the second-order matrix arrangement are formed by outputs of a 256-bit shift register 17 and array input and array output lines. The latter form an interface 18 for the array.

The switch matrices S ₁ to S ₅ consist of 1-bit switches and memories, which are arranged in a field. By setting a "1" or "0", signal and / or supply paths can be connected or separated.

FIG. 6 shows the implementation of the loop filter according to FIG. 1 by means of a first order matrix arrangement M ₁₁ in the first level of the array. Circuit elements denoted by the same reference numerals denote the same components in all the figures, so that their function and structure need not be explained again. As can be easily seen here, the configuration, which is predetermined by the content of the shift register 13, selects certain basic modules from the BBB rows / lines 1, 2, 3 and interconnects them in the desired manner. The function of the 64-bit shift register 13 for the analog configuration and that of the 16-bit shift register 19 for the rough digital control also become particularly clear here.

FIG. 7 shows a representation corresponding to FIG. 2 of a phase detector with two voltage comparators, as it is formed by the third matrix arrangement M _{13 of the} first order becomes. Here, too, the 64-bit shift register 15 is used for the analog configuration, while the 16-bit shift register 20 is used for the rough digital control.

FIG. 8 shows the entire wiring network which is formed by the array according to FIG. 5 in order to implement the frequency-locked control loop according to FIG. 3 in the second level of the array. Since the components have been explained with reference to the previous figures, no further explanation of the individual matrix arrangements is required.

Claims (14)

1. A configurable array, comprising

   at least two first-order matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄) comprising a plurality of basic elements (BBB) which are arranged in rows and/or columns, and including each a first switch matrix (S₁, S₂, S₃, S₄); and

   at least one second-order matrix array (M₂) including a second switch matrix (S₅) which connects the at least two first-order matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄);

   characterized in that

   the basic elements (BBB) are digital and at least partially analog basic elements;

   the first-order matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄) and the second-order matrix array (M₂) are arranged on a common substrate;

   the configurable array is provided with a device (13, 14, 15, 16) for inputting configuration data and for configuring the array;

   the respective first switch matrix (S₁, S₂, S₃, S₄) is adapted to be controlled by said device (13, 14, 15, 16) for inputting configuration data so as to interconnect the signal inputs and/or the signal outputs of the basic elements and so as to connect the basic elements to matrix inputs and/or matrix outputs of the first-order matrix array;

   the second switch matrix (S₅) is directly connected to the array inputs and array outputs (17, 18) and is adapted to be controlled by said device (13, 14, 15, 16) for inputting configuration data so as to interconnect the matrix inputs and/or the matrix outputs of the first-order matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄) and so as connect the matrix inputs and the matrix outputs of the first-order matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄) to array inputs and array outputs (17, 18).
2. An array according to claim 1, characterized in
   that the basic elements (BBB) additionally have an analog and/or digital control input.
3. An array according to claim 2, characterized in
   that each first-order matrix array (M₁₁, M₁₂, M₁₃, M₁₄) includes a parametrization register (13, 14, 15, 16, 19, 20) containing digital control signals for the digital control inputs of the basic elements (BBB, 19, 20) as well as control bits for the switches (13, 14, 15, 16).
4. An array according to claim 2 or 3, characterized in
   that each first-order matrix array (M₁₁, M₁₂, M₁₃, M₁₄) includes a multiplying digital/analog converter (MDC) which is acted upon by a binary data word (W1) from a parametrization register (19, 20) for generating an analog control signal (Vac) for the analog control input of the basic element (BBB).
5. An array according to claim one of the claims 2 to 4, characterized in
   that the basic elements (BBB) are configured into a complete system by controlling the analog and digital control inputs of said basic elements (BBB) an by controlling the switches (MSU) of said first and second matrix arrays (M₁₁, M₁₂, M₁₃, M₁₄; M₂) via the matrix inputs and the array inputs.
6. An array according to claim 5, characterized in
   that a shift register (13, 14, 15, 16, 17) is provided into which data for the configuration can be read serially and which defines the parametrization register.
7. An array according to claim 5, characterized in
   that a parallel interface is provided, which permits parallel input of the configuration data into the array.
8. An array according to claim one of the claims 1 to 7, characterized in
   that at least some of the basic elements (BBB) have each a qualification register associated with each of them, said qualification register being constructed as a read-write memory or as a read-only memory and containing at least one information on the total failure of the basic element (BBB).
9. An array according to claim 8, characterized in
   that the qualification register additionally contains information on operating characteristics of the basic element (BBB).
10. An array according to claim one of the claims 1 to 9, characterized in
    that at least the basic elements (BBB) which are not statically loss-free can be separated from the operating voltage via a power disconnection input.
11. An array according to one of the claims 1 to 10, characterized in
    that the array is implemented in BICMOS technology.
12. An array according to one of the claims 1 to 11, characterized in

    that the analog basic elements (BBB) comprise at least one of the following components:

    integrators, comparators, amplifiers, phase detectors and adjustable references.
13. An array according to claim 12, characterized in
    that the adjustable references consist of multiplying digital/analog converters (MDAC).
14. An array according to one of the claims 1 to 13, characterized in
    that the first switch matrix (S₁, S₂, S₃, S₄) and the second switch matrix (S₅) consist of a plurality of 1-bit switches and 1-bit memories (MSU) arranged in the form of a matrix.

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