EP0701753B1 - Procede de communication pour systeme de communication amdc adaptatif en sequences directes - Google Patents

Procede de communication pour systeme de communication amdc adaptatif en sequences directes Download PDF

Info

Publication number
EP0701753B1
EP0701753B1 EP94921246A EP94921246A EP0701753B1 EP 0701753 B1 EP0701753 B1 EP 0701753B1 EP 94921246 A EP94921246 A EP 94921246A EP 94921246 A EP94921246 A EP 94921246A EP 0701753 B1 EP0701753 B1 EP 0701753B1
Authority
EP
European Patent Office
Prior art keywords
bit
sequence
chip
receiver
transmitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94921246A
Other languages
German (de)
English (en)
Other versions
EP0701753A4 (fr
EP0701753A1 (fr
Inventor
Edward K. B. Lee
Jimmy Cadd
Tracy L. Fulghum
Robert S. Babayi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/073,226 external-priority patent/US5297162A/en
Priority claimed from US08/071,878 external-priority patent/US5359624A/en
Priority claimed from US08/071,879 external-priority patent/US5353300A/en
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0701753A1 publication Critical patent/EP0701753A1/fr
Publication of EP0701753A4 publication Critical patent/EP0701753A4/fr
Application granted granted Critical
Publication of EP0701753B1 publication Critical patent/EP0701753B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Definitions

  • This invention relates in general to the field of communication methods and synchronization in data communication systems and more particularly to a direct sequence code division multiple access (DS-CDMA) communication system.
  • DS-CDMA direct sequence code division multiple access
  • CDMA communication systems are used extensively in satellite communications with military and commercial applications. These systems are also known as spread spectrum communication systems because the communicated information is spread over a wide allocated frequency spectrum. In CDMA communication systems the frequency spectrum can be reused multiple times.
  • CDMA modulation techniques are inherently more susceptible to fading conditions present at the terrestrial and land mobile environments, their application has been limited to satellite communications.
  • CDMA communication systems are becoming increasingly popular in terrestrial land mobile communication environments as well.
  • recent developments have allowed CDMA systems to be used in cellular telephone communications environments.
  • CDMA Code Division Multiple Access
  • DS-CDMA direct sequence CDMA communication system
  • PN pseudorandom noise
  • the spreading code comprises a predetermined sequence of binary states known as chips.
  • a DS-CDMA transmitter produces a direct sequence spread spectrum (DS-SS) communication signal by multiplying the user information bit sequences by the spreading chip sequence.
  • the DS-SS communication signal is decoded by multiplying the received signal by a despreading chip sequence having corresponding characteristics to the spreading chip sequence.
  • the receiver knows of the spreading chip sequence prior to start of a communication call. Thereafter, the receiver decodes the DS-SS communication signal based on the known spreading chip sequence.
  • PN codes are constructed such that they provide orthogonality between the user codes, thereby reducing mutual interference. This allows for higher capacity and better link performance. With orthogonal PN codes cross-correlation is zero over a predetermined time interval resulting in no interference between the orthogonal codes provided only that the code time frames are aligned with each other.
  • the spreading chip sequence is either assigned by a self controller or it is pre-stored within the receiving unit. As such, during despreading and demodulation process, the receiver knows of the spreading chip sequence.
  • a more recent approach for a CDMA receiver proposes an adaptive despreading or demodulating process.
  • the receiver is enabled to suppress multiple access interference by an adaptive equalization process.
  • a CDMA transmitter transmits a training bit sequence which is coded with the spreading chip sequence and the receiver adaptively determines, based on the training sequence, the despreading code using a tapped delay line equalizer. Adaptive determination of the despreading chip sequence and suppression of multiple access interference allows significant number of users to communicate with each other over an spread spectrum channel without requiring central control infrastructure, and as such paving the way for infrastructureless communication systems.
  • the determined despreading chip sequence is not time synchronized with the transmitter because of certain time delays within the communication path or simply because the receiver does not know when bit and chip timing of the transmitter starts.
  • Conventional methods of determining bit timing and chip timing offsets between the transmitter and receiver comprise performing correlation routines involving complex mathematical processing operations. These operations are time consuming and therefore delay establishment of communication link between transmitter and receiver. Therefore, there exists a need for a faster synchronization method which could be achieved in significantly shorter period of time than is achievable by conventional methods.
  • United States Patent 4550414 Guinon et al discloses a pseudo-noise code tracking spread spectrum receiver including an adaptive weighting system for correlation.
  • the communication system 100 includes a plurality of CDMA transmitters 10 and a plurality of CDMA receivers 20 which communicate direct sequence spread spectrum (DS-SS) communication signals 30.
  • the DS-SS communication signal 30 comprises a radio frequency communication signal modulated with binary bits coded with spreading chip sequence.
  • the communication system 100 is an adaptive CDMA communication system whereby the despreading chip sequence is adaptively determined after the CDMA receivers 20 demodulates the DS-SS communication signal 30.
  • the receiver includes a tapped delay line equalizer which adaptively determines the despreading chip sequence during a training interval.
  • the adaptive equalization is performed in presence of multiple access interfering signals, it adaptively produces the despreading chip sequence which suppresses the effects of the multiple access interference and decode the DS-SS communication signal 30.
  • CDMA receivers 20 determines the despreading chip sequence communication between the CDMA transmitter 10 may be carried on based on the determined despreading chip sequence provided the bit timing and chip timing are synchronized.
  • the adaptive equalization during training is performed without bit timing or chip timing synchronization of the receiver and the transmitter. This is because performing synchronization of any kind in presence of interfering signals is close to impossible. Thus, a redundant training bit sequence is transmitted to circumvent the need for synchronization while the despreading chip sequence is being determined during training interval.
  • the DS-SS communication signal 30 comprises string of bits which are coded with a spreading chip sequence.
  • the bits and the chips are binary signals assuming one of two states of +1 and -1 represented by voltage potentials of V +1 and V -1 respectively.
  • the V +1 and V -1 potentials are of equal magnitude but opposite polarity. In this description it is assumed that V +1 has a positive polarity and the V -1 has a negative polarity.
  • a training sequence 31 is transmitted which is used by the receiver 20 to adaptively determine despreading chip sequence using a tapped delay line equalizer based on the training bit sequence.
  • the training bit sequence comprises a predetermined redundant bit sequence having a non-alternating and continuous bit states, such as a sequence of consecutive +1 bit state.
  • the training sequence 31 is followed by a transmitter bit timing sequence 33 which is used to synchronize receiver and transmitter bit timing.
  • the transmitter bit timing sequence 33 is predetermined bit sequence having characteristics which gives the receiver information relating to the transmitter bit timing. As described later in detail, the transmitter bit timing sequence 33 comprises an alternating bit sequence having alternating bit states of both +1 and -1.
  • a user information sequence 35 comprising user generated data is transmitted.
  • the user generated data carries the actual data for communication of which the transmission was initiated.
  • the user generated data may for example be coded voice or raw binary data.
  • the CDMA transmitter 10 includes a central controller and signal processor block 220, which controls the entire operation of the transmitter 10 including signal processing necessary for modulating and generating the spreading chip sequence.
  • the transmitter 10 includes a training sequence block 201 which generates the predetermined training sequence.
  • the transmitter 10 also includes a transmitter bit timing sequence generator block 203 which generates the transmitter bit timing sequence following the training sequence.
  • a user information sequence block 205 provides user information in form of binary bit sequences.
  • the user information may be originated from a variety of sources, such as from a voice coder which receives voice information from a microphone or it may comprise raw data information generated from a computing device.
  • a selector block 207 under the control of the central controller and processor block 220 provides for selecting one of the training, bit timing or user information sequences in proper order and applies it to a multiplier 209.
  • a spreading chip sequence generator block 211 generates the spreading chip sequence to be combined with the bit sequence to be transmitted to the receiver.
  • the generated spreading chip sequence comprise well-known gold PN codes having desirable cross-correlation and auto-correlation properties.
  • the spreading chip sequence has a predetermined number of chips (n) for coding each bit of the transmission sequences.
  • the multiplier 209 multiplies one of the transmission sequences by the spreading chip sequence and applies it to a modulator 213.
  • Modulator 213 may comprise a number of well known binary signal modulators, such as binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulators. Output of the modulator 213 is applied to a power amplifier 215 which amplifies the modulated signal and applies it to an antennae 217 for transmission. It may be appreciated that the block 220 and some of the other blocks described in conjunction with transmitter 10 maybe implemented utilizing one or more of well known digital signal processors, such as DSP 56000 series manufactured by Motorola Inc.
  • DSP 56000 series manufactured by Motorola Inc.
  • the spread spectrum communication signal is received at the antennae 301 and is applied to a preselector filter 303 which provides the initial receiver selectivity.
  • the filtered signal is applied to a well known base band demodulator 305.
  • the base band demodulator 305 comprises a well-known demodulator that demodulates the communication signal in accordance with the modulation scheme used in the transmitter 10 to provide a baseband signal 306.
  • the base band signal 306 is applied to a well-known chip matched filter block 307.
  • the chip matched filter comprises a well-known integrate-and-dump or a low pass filter block where the received DS-SS communication signal 30 is sampled and integrated at chip rate and the result is dumped at the end of each chip interval.
  • the output of the chip matched filter is applied to a despreading equalizer 400 which, based on the training sequence adaptively determines a despreading chip sequence.
  • the despreading equalizer provides despreading chip sequence by adaptively equalizing the detected coded bits with an uncoded pre-stored signal corresponding to the training bit sequence.
  • a signal processor and controller block 320 performs all necessary signal processing requirements for the receiver 20.
  • the equalizer 400 despreads the DS-SS communication signal 30 and provides a decoded communication signal at its output (415).
  • the decoded communication signal is applied to a user interface block 313 which may comprise one of a number of user interface devices such as a speaker, a computing device, a data display or a fax or voice mail machine.
  • the equalizer 400 comprises an n-tap delay line equalizer where, as mentioned before, n is the number of chips per bit in the spreading chip sequence.
  • the tap delay line consists of a bank of n-1 serially coupled flip-flops 402 with their outputs coupled to a corresponding number of multipliers 404.
  • the bank of serially coupled flip-flops 402 operate as a shift register sequentially shifting, at the chip rate, sampled outputs of the chip matched filter 307, i.e., (r 1 -r n ) during each bit interval.
  • the multipliers 404 multiply the flip-flop outputs with tap coefficients C 1 -C n provided by a tap coefficient generator block 407.
  • a summer 405 sums the outputs of the multipliers 404 to provide the summer output 408.
  • the summer output 408 represents integration of the multiplier outputs over one bit interval.
  • the summer's output 408 is applied to a comparator 409 and a threshold decision block 410.
  • the threshold decision block 410 comprises a threshold comparator which after training interval provides the detected bits of the user bit sequence.
  • the threshold decision block 410 provides the equalizer output 415.
  • the threshold detector decision block 410 determines the decoded bit state by comparing the summer output 408 with a bit state threshold level. It may be appreciated that the equalizer output 415 and the summer output 408 are related by having a (1/n) ratio therebetween.
  • the comparator 409 compares the summer's output 408 with a pre-stored sequence as provided by a block 403.
  • the pre-stored training sequences is a pre-determined signal representing uncoded training sequence. Therefore, the training sequence comprises a signal simulating uncoded redundant consecutive and non-alternating training bits.
  • the comparator 409 compares the pre-stored training sequence with the summer output and provides an error signal 411 which is applied to a tap coefficient generator block 407.
  • the tap coefficient generator blocks uses either the Least Means Square (LMS) or Recursive Least Square (RLS) algorithm to update tap coefficients C 1 -C n once every bit interval in order to minimize the error signal 411.
  • LMS Least Means Square
  • RLS Recursive Least Square
  • the despreading equalizer 400 updates the tap coefficient C 1 -C n until the error signal between the detected bit sequence and the pre-stored training sequence is minimized. Hence, equalizing the summer output 408 with the output of the pre-store training sequence. As a result of equalizing the transmitted training bit sequence and the pre-stored sequence, the tap coefficients C 1 -C n become a representation of the despreading chip sequence which despread the DS-SS communication signal 30 and suppress multiple-access interfering signals without prior knowledge of the spreading chip sequence. As such, the tap coefficients C 1 -C n represent of the despreading chip sequence. These coefficients are used to despread the DS-SS communication signal 30 after the training interval has terminated.
  • the receiver upon commencement of a transmission the receiver receives the training sequence 31 of the DS-SS communication signal 30 of FIG. 2.
  • the training sequence comprises a bit sequence comprising non-alternating bit sequence, such as a bit sequence having continuous coded states of either +1 or -1.
  • the pre-stored sequence also presents continuous uncoded states of either +1 or -1 during the training interval.
  • the training sequence is sampled at chip rate via the chip matched filter 307.
  • the output of chip matched filter is applied to the tapped delay line equalizer 400 where through recursive iteration of updating the tap coefficients C 1 -C n the pre-stored training bit sequence and detected bit sequence are equalized.
  • the equalizer 400 produces tap coefficients C 1 -C n which are a representation of the despreading chip sequence. Accordingly, the DS-SS communication signal 30 is decoded by adaptively determining a representation of the despreading chip sequence based on the training bit sequence.
  • the resulting tap coefficients despread the received DS-SS communication signal while also eliminating the interfering signals.
  • the summer's output 408 at the end of each receiver bit interval represents integration of the decoded communication signal over that receiver bit interval.
  • the integration constitutes summation of multiplication result during discrete chip intervals.
  • the equalizing tap coefficients (C 1 -C n ) are determined after training, their multiplication by the chip matched filter outputs (r 1 -r n ) despreads or decodes the incoming DS-SS communication signal.
  • the summer's output 408 after each receiver bit interval is equal to the number of chips (n) multiplied by the bit potential of the decoded communication signal bit, i.e. +1 , or V -1 depending on the detected bit state, i.e., whether the detected bit comprises +1 or -1.
  • the tap delay line equalizer 400 could be implemented within the digital signal processor 320 of the receiver 20.
  • the digital signal processor includes despreading means, determination means, comparison means and any and all other means necessary for processing and controlling to effectuate the required functions of the present invention as outlined in this specification.
  • the equalizer 400 may be implemented utilizing conventional digital and logical discrete components as is well known in the art.
  • the despreading chip sequence as provided by the tap coefficients C 1 -C n may have to be synchronized for proper despreading of the DS-SS communication signal 30.
  • a chip timing offset estimation is made during a chip timing interval. This is because, as described hereinafter, the chip timing offset information could be extracted from the tap coefficients of the equalizer.
  • the voltage potential or the energy stored in the tap coefficients C 1 -C n includes chip timing information provided that the effects of the interfering multiple access signals are suppressed.
  • the despreading chip sequence is represented by the tap coefficients C 1 -C n and potentials thereof.
  • the interfering signals are eliminated after the training interval and upon determination of the despreading chip sequence. Therefore, chip timing offset determination is commenced following the training interval to align receiver and transmitter chip timing.
  • the chip timing offset determination process of the present invention could take place during one or more bit intervals after the final tap coefficients are determined.
  • the chip sequence comprises n chips which assume one of two states +1 and -1. Because the outputs of the chip matched filter 305 (r 1 -r n ) when sampled by the receiver contain information relating to the receiver and the transmitter chip timing offset and because the voltage potentials representing the tap coefficients are directly proportional to the energy of the received chips at the end of receiver chip intervals, the tap coefficient potentials are processed for determining the timing offset. Due to binary nature of the chip sequence, the ratio of the maximum potential of the outputs of the chip matched filter 307 to the minimum output potentials relates to the chip timing offset.
  • the tap coefficients potentials can be divided into two sets: one having maximum and another having minimum potentials.
  • a first set of coefficient potentials corresponds to those having maximum potentials (V max ) and a second set of coefficient potentials corresponding to those having minimum potentials (V min ).
  • V max voltage potential
  • V min voltage potential of tap coefficients in second set change with respect to the tap coefficients in the second set by a factor of (1-2 a ), where a represents the chip timing offset in terms of one chip interval.
  • a represents the chip timing offset in terms of one chip interval.
  • the maximum potentials and the minimum potentials are expressed in terms of absolute values. Therefore, their polarity is irrelevant for determination of chip timing offset.
  • the output of the chip matched filter at the end of each intervals 701-707 has one of two equal but opposite potentials V +1 and V -1.
  • the potentials correspond respectively to either of the +1 or -1 potential of the chip state.
  • is equal to the absolute value of the second set of potentials, i.e.
  • the timing offset may be determined by processing the tap coefficient potentials at the end of each bit interval.
  • V max (or V min for that matter) as referred herein could be considered as corresponding to either one of V +1 or V -1 since the absolute values of the V max or V min are of significance equation (1).
  • a receiver chip timing offset of 1/2 chip is assumed. That is, the chip interval 701 is half a chip off from the chip interval 801. As shown, the output of chip matched filter at the end of time interval 801 reaches V +1 . Then at the end of time interval 802 the chip matched filter output reaches a zero potential. At the end of chip interval 803, the output reaches V -1 . Again, at the end of chip intervals 804-806, the outputs are at zero. And finally at the end of interval 807 the output reaches V +1 .
  • a receiver chip timing offset of +1/4 is assumed.
  • the positive sign of the chip timing offset signifies that the transmitter chip timing leads the receiver chip timing. That is, the transmitter chip timing reference starts prior to the receiver chip timing reference.
  • V max is equal to V +1 (or V -1 ) and V min is equal to 1/2 of V +1 .
  • the timing offset determined based on Equation (1) does not provide information relating to whether the timing offset is positive or negative.
  • the sign of the timing offset indicates whether the receiver chip timing is leading or trailing the transmitter timing offset.
  • the sign of information can be determined by examining the polarity and magnitude of successive tap coefficient potentials during one bit interval or two successive bit intervals. Therefore, once the absolute value of the timing offset a is determined further processing of the tap value coefficients results in determination of the timing offset sign.
  • timing offset when the timing offset is equal to 1/2 chip interval the sign of the offset becomes irrelevant since the receiver chip timing could be adjusted by one half chip interval in positive or negative direction resulting in synchronization with transmitter chip timing.
  • positive chip timing offset of greater than 1/2 chip timing offset could be expressed in terms of a negative complementary offset.
  • a positive 3/4 timing offset could be expressed as a -1/4 timing offset and so on. Therefore, the timing offset a would be a value within the range of zero to 1/2 with the offset timing sign signifying the leading or trailing status of the receive chip timing offset.
  • FIG. 10 a receiver chip timing offset of -1/4 is shown.
  • the -1/4 timing offset of FIG. 10 will be compared with the +1/4 timing offset condition of FIG. 9.
  • the outputs of the chip matched consist of V +1 , 1/2 V +1 , and V -1 . Due to the fact that the timing offset is positive in FIG. 9, after completion of a positive to negative chip transition occurring during intervals 601 to 602 (shown in FIG.
  • the output of the chip matched filter reaches a positive polarity, i.e., 1/2 V +1 , at the end of interval 902.
  • a negative polarity i.e., 1/2 V -1
  • the sign of the timing offset could be determined based on the polarity of at least one of the tap coefficient potentials after one or more chip transitions. It may be appreciated that the same type of analysis is applicable to a negative to positive chip transition as well as other chip sequence arrangements.
  • the tap coefficient potential processing needed for determination of the chip timing offset a and its sign could all be accomplished by appropriately programming the digital signal processor 320 utilizing well known signal processing techniques.
  • the signal processor 320 includes means for determining chip timing offset based on the tap coefficient potentials as well as the means for determining sign of the chip timing offset based on the polarity of at least one of the tap coefficients after a chip transition.
  • the receiver chip timing Upon determination of the chip timing offset and sign thereof, the receiver chip timing could be adjusted to synchronize it with the transmitter chip timing. It should be noted that because of existence of multiple access interference the chip timing offset determination according to the present invention produces an estimate and not the precise chip timing offset. Therefore, there may still be a need to perform some minor correlation routines to complete chip synchronization. However, the amount of time needed to perform such routines is minimal.
  • the receiver 20 commences a bit timing synchronization process during a bit timing interval.
  • bit timing offset between the receiver and the transmitter during the training interval causes the resulting tap coefficients C 1 -C n , which represents the despreading chip sequence, to be cyclically shifted by a corresponding number of chips. Therefore, the receiver bit timing offset may be expressed, in terms of chip numbers.
  • the DS-SS communication signal 30 is despreaded, after the determination of tap coefficient C 1 -C n the resulting decoded DS-SS communication signal includes bit timing information which may be extracted in conjunction with the transmitter bit timing sequence 33 of FIG. 2.
  • the summer output 408 After the training interval, the summer output 408 provides a representation of the decoded DS-SS communication signal 30. Therefore, the summer output 408 is processed to determine the bit timing offset.
  • bit timing offset information may be extracted by processing the summer output 408 after an alternating transition from one bit state to another bit state has occurred.
  • the transmitter bit timing sequence 33 follows the training sequence.
  • the transmitter bit timing sequence when received, provides the receiver 20 with the capability of detecting start of the transmitter bit interval.
  • the transmitter bit timing sequence 33 comprises a sequence of alternating bit sequence with at least two consecutive bits having alternating states such that the state of one bit changes from one interval to the succeeding interval. In other words, a transition from +1 to -1, or vice versa, would exist between two consecutive bits from a first bit interval to the subsequent second bit interval.
  • the transitions occurring over the transmitter bit timing sequence are critical because they are indicative of transmitter bit timing which is used in the receiver to determine the bit timing offset according to equation 2.
  • an exemplary transmitter bit timing sequence may consist of the sequential bit states of +1, +1, -1, -1, +1, +1, -1 , -1 occurring respectively in transmitter bit intervals 111, 113, 115, 117. It may be appreciated that the transmitter bit timing sequence may be of other variety of sequences, such as alternating bit sequence of +1, +1, -1, +1, +1, -1 as long as the sequence consists of transitions conveying transmitter bit timing information.
  • the receiver bit timing offset is determined after the training interval by integrating, over a first receiver bit interval, non-alternating bits of the decoded communication signal to produce a first result, and integrating over, a second receiver bit interval, alternating consecutive bits of the decoded communication signal to produce a second result. Thereafter, the first result is compared with the second result to determine the bit timing offset.
  • the bit timing offset is determined by determining half the difference between the first result and the second result. It should be noted that the first result may be a prestored constant value representing the result of integration over non-alternating bits.
  • the above concept may be better understood by referring to FIG. 12, where the summer output in a situation where the bit timing offset is -m chips is shown.
  • the negative sign of the timing offset indicates that the transmitter bit interval occurs before the receiver bit interval.
  • the normalized summer output 408 at the end of the second receiver bit interval after integration during the alternating bit transition from +1 to -1 occurring on the transmitter bit interval 115 is equal to -(n-2m), i.e., second result is n-2m. Therefore, by determining half the difference between absolute values of the first result and the second result the absolute value of the bit timing offset m is determined.
  • the absolute value of the chip timing offset as determined above does not indicate sign of the receiver bit timing offset.
  • an exemplary situation where the receiver bit timing is equal to +m chips as shown in FIG. 13, is compared to the situation of FIG. 12 where the receiver bit timing is -m chips.
  • a negative bit timing offset produces a first result which has a positive polarity and a second result which has a negative polarity after the transition.
  • a positive bit timing offset produces a positive polarity first result and second result.
  • FIG. 13 during the same positive to negative transition.
  • bit timing offset 12th negative to positive transition from the transmitter bit interval 117 to 119, produces a negative polarity first result (the polarity of the summer output as a result of integration of two consecutive -1s of intervals 115 and 117), and a positive second result when the bit timing offset sign is negative.
  • a positive bit timing offset sign produces negative first and second results.
  • the sign of the bit timing offset may be determined by determining the type of transition, i.e. positive to negative or vice versa and comparing the polarities of the first result and the second result. Accordingly, of the bit timing offset is determined by comparing results of integration produced during consecutive non-alternating bits with that obtained during alternating bits.
  • the receiver bit timing could be adjusted to synchronize it with the transmitter bit timing. It should be noted that because of existence of multiple access interference the bit timing offset determination according to the present invention produces an estimate and not the precise bit timing offset. Therefore, there may still be a need to perform some minor correlation routines to complete bit synchronization. However, the amount of time needed to perform such routines is minimal.
  • the receiver 20 commences to decode user information sequence.
  • the adaptive communication system 100 uniquely communicates DS-SS communication signal 30 from the transmitter 10 to the receiver 20 in three sequential intervals: first the training interval, then the chip timing interval and finally the bit timing interval.
  • the unique communication sequence of the present invention greatly facilitates receiver and transmitter timing synchronization in an adaptive CDMA communication system which results in quick establishment of communication links between CDMA receivers 20 and the CDMA transmitters 10.
  • the despreading equalizer 400 decodes the DS-SS communication signal 30 which includes the training bit sequence.
  • the DS-SS communication signal 30 is decoded by adaptively determining, based on the training bit sequence, tap coefficients of the equalizer which represent the despreading chip sequence.
  • the effects of multiple access interfering signals are eliminated paving the way for chip timing and bit timing offset determination. Because the bit timing offset information can be easily extracted following the chip timing offset determination, therefore, after training interval the chip timing offset is determined during the chip timing interval. The chip timing offset is determined based on the potential of the representation of the despreading chip sequence. Finally, during the bit timing interval, the bit timing offset is determined based on the decoded DS-SS communication signal and the transmitter bit timing sequence which is transmitted following the training bit sequence.
  • the bit timing synchronization in the adaptive CDMA communication system 100 is achieved mainly by decoding and integrating the transmitter bit timing sequence of the DS-SS communication signal without performing complex correlation routines. Integration and the necessary processing of the decoded communication signal and derivation of the bit timing offset requires substantially less time than the more time consuming correlation processing proposed in the prior art. As a result, a quick communication link between the receiver and the transmitter is established.
  • the chip timing synchronization in the adaptive CDMA communication system 100 is achieved mainly based on information inherent in the tap coefficients C 1 -C n without performing complex correlation routines. Simple processing of the tap coefficient potentials and derivation of the chip timing offset based thereon requires substantially less time than the more time consuming correlation processing proposed in the prior art. As a result, a substantially quicker and more efficient communication link between the receiver and the transmitter is established.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Mobile Radio Communication Systems (AREA)

Claims (5)

  1. Procédé de synchronisation de bit permettant de synchroniser le rythme de bits de récepteur et le rythme de bits d'émetteur dans un système de communication par étalement du spectre CDMA à séquence directe (100) dans lequel les signaux de communication à spectre étalé (30) comprenant des bits codés avec des séquences d'éléments d'étalement sont mis en communication entre un émetteur (10) et un récepteur (20), le procédé comprenant les étapes consistant à :
    (a) transmettre un signal de communication à spectre étalé et à séquence directe (DS-SS) comportant une séquence de bits de conditionnement redondante suivie d'une séquence de rythme de bits d'émetteur codée avec une séquence d'éléments d'étalement ;
    (b) annulation de l'étalement du signal de communication DS-SS en fonction de ladite séquence de bits de conditionnement redondante afin de fournir un signal de communication décodé ; et
    (c) déterminer le décalage de rythme de bits de récepteur en fonction de la séquence de rythme de bits d'émetteur et du signal de communication décodé.
  2. Procédé selon la revendication 1, dans lequel l'étape consistant à annuler l'étalement du signal de communication DS-SS comporte l'étape consistant à :
       déterminer de façon adaptative une représentation de la séquence d'éléments d'annulation d'étalement en utilisant un égaliseur (400).
  3. Procédé selon la revendication 2, dans lequel le signal de communication DS-SS comporte des bits non alternants consécutifs et la séquence de rythme de bits d'émetteur comprend des bits alternants dans lequel l'état d'au moins un des deux bits consécutifs passe d'un intervalle binaire à un intervalle binaire suivant.
  4. Procédé selon la revendication 3, dans lequel ladite étape de détermination du décalage de rythme de bits comporte les étapes consistant à :
       intégrer le signal de communication décodé sur un intervalle binaire de récepteur pendant des bits alternants.
  5. Procédé selon la revendication 4, dans lequel ladite étape consistant à déterminer le décalage de rythme de bits comporte les étapes consistant à :
    produire l'intégration du signal de communication décodé sur un intervalle binaire de récepteur pendant les bits non alternants consécutifs ; et
    déterminer le signe du décalage de rythme de bits en comparant les résultats des intégrations produites pendant les bits non alternants consécutifs avec ceux obtenus pendant les bits alternants.
EP94921246A 1993-06-04 1994-06-03 Procede de communication pour systeme de communication amdc adaptatif en sequences directes Expired - Lifetime EP0701753B1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US08/073,226 US5297162A (en) 1993-06-04 1993-06-04 System and method for bit timing synchronization in an adaptive direct sequence CDMA communication system
US73226 1993-06-04
US71878 1993-06-07
US08/071,878 US5359624A (en) 1993-06-07 1993-06-07 System and method for chip timing synchronization in an adaptive direct sequence CDMA communication system
US08/071,879 US5353300A (en) 1993-06-07 1993-06-07 Communication method for an adaptive direct sequence CDMA communication system
PCT/US1994/006358 WO1994029985A1 (fr) 1993-06-04 1994-06-03 Procede de communication pour systeme de communication amdc adaptatif en sequences directes
US71879 1998-01-20

Publications (3)

Publication Number Publication Date
EP0701753A1 EP0701753A1 (fr) 1996-03-20
EP0701753A4 EP0701753A4 (fr) 1999-07-07
EP0701753B1 true EP0701753B1 (fr) 2001-09-26

Family

ID=27371982

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94921246A Expired - Lifetime EP0701753B1 (fr) 1993-06-04 1994-06-03 Procede de communication pour systeme de communication amdc adaptatif en sequences directes

Country Status (5)

Country Link
EP (1) EP0701753B1 (fr)
CN (1) CN1097901C (fr)
CA (1) CA2161258C (fr)
DE (1) DE69428440D1 (fr)
WO (1) WO1994029985A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI97581C (fi) * 1995-02-10 1997-01-10 Nokia Telecommunications Oy Vastaanotin ja menetelmä hajotuskoodien generoimiseksi vastaanottimessa
US6205132B1 (en) * 1996-02-22 2001-03-20 Korea Mobile Telecommunications Corp. Method for accessing a cell using two pilot channels in a CDMA communication system of an asynchronous or quasi-synchronous mode
FR2782215A1 (fr) * 1998-08-10 2000-02-11 Alsthom Cge Alcatel Intervalle de temps comprenant des symboles de reference utilise dans un reseau de transmission de type cdma
US6560273B1 (en) * 1998-10-07 2003-05-06 Ericsson Inc. Delay searcher and delay trackers interaction for new delays assignment to rake fingers
GB9904421D0 (en) * 1999-02-25 1999-04-21 Univ Edinburgh Telecommunications receiver
FR2792788B1 (fr) 1999-04-21 2001-07-13 Mitsubishi Electric France PROCEDE D'EQUILIBRAGE DU RAPPORT Eb/I DANS UN SYSTEME cdma A MULTIPLEXAGE DE SERVICE ET SYSTEME DE TELECOMMUNICATION L'UTILISANT
KR20010035967A (ko) 1999-10-05 2001-05-07 서평원 코드분할다중접속 시스템의 다중 사용자 신호 동기 획득 장치 및 그 방법
US10420132B2 (en) 2016-08-09 2019-09-17 Battelle Energy Alliance, Llc Devices, base stations, and methods for communicating scheduling requests via an underlay control channel in a wireless communication system
US10912059B2 (en) 2018-04-18 2021-02-02 Battelle Energy Alliance, Llc Systems, devices and methods for communicating data with unmanned aerial vehicles using underlay broadcast channel

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE32905F1 (en) * 1980-10-20 1992-11-10 Satellite communications system and apparatus
US4583090A (en) * 1981-10-16 1986-04-15 American Diversified Capital Corporation Data communication system
US4550414A (en) * 1983-04-12 1985-10-29 Charles Stark Draper Laboratory, Inc. Spread spectrum adaptive code tracker
US4617674A (en) * 1983-07-14 1986-10-14 Rca Corporation Synchronizing system for spread spectrum transmissions between small earth stations by satellite via an intermediate hop to a large earth station
US4901307A (en) * 1986-10-17 1990-02-13 Qualcomm, Inc. Spread spectrum multiple access communication system using satellite or terrestrial repeaters
US5109390A (en) * 1989-11-07 1992-04-28 Qualcomm Incorporated Diversity receiver in a cdma cellular telephone system
US5056109A (en) * 1989-11-07 1991-10-08 Qualcomm, Inc. Method and apparatus for controlling transmission power in a cdma cellular mobile telephone system

Also Published As

Publication number Publication date
CA2161258A1 (fr) 1994-12-22
WO1994029985A1 (fr) 1994-12-22
EP0701753A4 (fr) 1999-07-07
DE69428440D1 (de) 2001-10-31
CN1097901C (zh) 2003-01-01
CA2161258C (fr) 1996-10-01
EP0701753A1 (fr) 1996-03-20
CN1125026A (zh) 1996-06-19

Similar Documents

Publication Publication Date Title
US5297162A (en) System and method for bit timing synchronization in an adaptive direct sequence CDMA communication system
US5353300A (en) Communication method for an adaptive direct sequence CDMA communication system
US5359624A (en) System and method for chip timing synchronization in an adaptive direct sequence CDMA communication system
EP0712553B1 (fr) Procede et appareil permettant de recevoir et de decoder des signaux de communication avec un recepteur amdc
US5414699A (en) Method and apparatus for receiving and decoding communication signals in a CDMA receiver using partial de-correlation
EP0842568B1 (fr) Dispositif adaptatif de desetalement de spectre
US5452328A (en) Technique for generating sets of binary spreading-code sequences for a high data-rate spread-spectrum network
US5590160A (en) Symbol and frame synchronization in both a TDMA system and a CDMA
JP3091711B2 (ja) スペクトル拡散通信システムにおける復調および電力制御ビット検出のための方法
US5563906A (en) Method of geometric harmonic modulation (GHM)
US5267271A (en) Signal analysis technique for determining a subject of binary sequences most likely to have been transmitted in a multi-node communication network
US6522687B2 (en) Data transmitter and receiver of a DS-CDMA communication system
EP0807345B1 (fr) Procede de transmission de donnees amrc, emetteur et recepteur avec supersymbole pour eliminer les interferences
MXPA98000853A (en) Des-extendedor adapta
EP0758504A1 (fr) Detecteur coherent de liaison montante dans un systeme d'acces multiple par difference de code a sequence directe
EP0701753B1 (fr) Procede de communication pour systeme de communication amdc adaptatif en sequences directes
US6396869B1 (en) Modulation apparatus and method using zero-crossing detection
US5568507A (en) Geometric harmonic modulation (GHM) - analog implementation
JP2000091952A (ja) スペクトラム拡散通信方法及びスペクトラム拡散通信装置
KR20020089496A (ko) 이동 송수화기에서의 다수 채널 결합 디코딩
US7433385B1 (en) Code division multiple access communication
US20040057504A1 (en) CDMA receiving device and method
JPH11275061A (ja) 干渉除去受信機

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19960104

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

RIN1 Information on inventor provided before grant (corrected)

Inventor name: BABAYI, ROBERT, S.

Inventor name: FULGHUM, TRACY, L.

Inventor name: CADD, JIMMY

Inventor name: LEE, EDWARD, K., B.

A4 Supplementary search report drawn up and despatched

Effective date: 19990526

AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE FR GB IT

RIC1 Information provided on ipc code assigned before grant

Free format text: 6H 04L 9/00 A, 6H 04L 27/30 B, 6H 04B 1/66 B

17Q First examination report despatched

Effective date: 19991029

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

ITF It: translation for a ep patent filed

Owner name: BARZANO' E ZANARDO ROMA S.P.A.

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20010926

REF Corresponds to:

Ref document number: 69428440

Country of ref document: DE

Date of ref document: 20011031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20011228

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20020501

Year of fee payment: 9

EN Fr: translation not filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030603

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20030603

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20060630

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070603

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230520