EP0700584A1 - Electrical circuit using low volume multilayer transmission line devices - Google Patents
Electrical circuit using low volume multilayer transmission line devicesInfo
- Publication number
- EP0700584A1 EP0700584A1 EP95906635A EP95906635A EP0700584A1 EP 0700584 A1 EP0700584 A1 EP 0700584A1 EP 95906635 A EP95906635 A EP 95906635A EP 95906635 A EP95906635 A EP 95906635A EP 0700584 A1 EP0700584 A1 EP 0700584A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- dielectric substrate
- transmission line
- positioned substantially
- ground plane
- substantially adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 143
- 230000001131 transforming effect Effects 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 description 15
- 239000000919 ceramic Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000010420 art technique Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004814 ceramic processing Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/088—Stacked transmission lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/12—Coupling devices having more than two ports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/004—Printed inductances with the coil helically wound around an axis without a core
Definitions
- the present invention relates generally to electrical circuits, and in particular to such circuits that require low volume transmission line devices.
- Electrical transmission lines are used to transmit electric energy and signals from one point to another.
- the basic transmission line connects a source to a load—e.g. a transmitter to an antenna, an antenna to a receiver, or any other application that requires a signal to be passed from one point to another in a controlled manner.
- Electrical transmission " lines which can be described by their characteristic impedance and their electrical length, are an important electric component in radio frequency (RF) circuits.
- RF radio frequency
- transmission lines can be used for impedance matching— i.e., matching the output impedance of one circuit to the input impedance of another circuit.
- the electrical length of the transmission line typically expressed as a function of signal wavelength, represents another important characteristic of the transmission line device.
- Manipulation of the characteristic impedance and electrical length of the transmission line device is a well known technique to effect a particular electrical result.
- an output impedance, Zout can be matched to an input impedance, Zjn, according to a well known equation, as later described.
- the attenuation and phase shift of the transmission line device can be altered by changing the physical length of the conductor between the input and output ports of the transmission line device.
- a resonant circuit results when the physical length of the conductor approximates an even one-quarter wavelength of the signals nominal frequency.
- the wavelength is small and transmission line devices can be built using relatively short conductors in small packages.
- the physical length must necessarily increase to effect the desired transmission line characteristic. The physical length must correspondingly increase to accommodate such applications operating at lower frequencies.
- a helical structure disposed inside a grounding cylinder.
- Such helical coils are well known in the art, but these too are often inadequate for today's applications, where low volume and low cost are critical factors in the manufacture of portable electronic devices.
- the helical structures become very costly to manufacture. That is, the manufacturing variance that is inherent in the construction of such devices— e.g. conductor diameter, symmetry of windings, and effective number of turns— tends to make the helical structure a less desirable solution for tight tolerance transmission line devices.
- the cylindrical grounding portion which feature is required when building a transmission line device, results in a circuit having a relatively large volume, or poor form-factor, that is untenable for many of today's applications.
- a device having a substantially lower volume— or one having a better form-factor— than its predecessors would be an improvement over the prior art.
- Such a device that was also cost effective to manufacture, and could be used at lower operating frequencies, would further provide a distinct advantage over prior art transmission line devices.
- FIG. 1 shows a multilayer ceramic transmission device using vertically stacked half-ring conductors, in accordance with one embodiment of the present invention.
- FIG. 2 shows a multilayer ceramic transmission device using vertically stacked full-ring conductors, in accordance with a second embodiment of the present invention.
- FIG. 3 shows a multilayer ceramic transmission device using vertically stacked spiral- conductors, in accordance with a third embodiment of the present invention.
- FIG. 4 shows a multilayer ceramic transmission device using horizontally stacked strip conductors, in accordance with yet another embodiment of the present invention.
- FIG. 5 shows a multilayer ceramic power splitter/combiner, in accordance with the present invention.
- FIG. 6 shows a multiple transmission line device that advantageously employs a vertically stacked transmission line device and a horizontally stacked transmission line device.
- FIG. 7 shows a circuit that employs a plurality of transmission line devices, which circuit might advantageously employ embedded ground planes, in accordance with the present invention.
- a device having transmission line characteristics can be formed using a multilayer ceramic processing technique.
- the transmission line device includes at least a first ground plane located on a first dielectric substrate.
- a first and second conductive layer are disposed on additional dielectric substrates that are substantially adjacent to the first dielectric substrate.
- the first and second conductive layers each at least partially enclose a corresponding area on their respective dielectric substrates. Arranging the conductive layers and the substantially adjacent ground plane in this manner facilitates a design requiring increased electrical length and a more controllable characteristic impedance for the transmission line device. Further, this arrangement advantageously employs relatively inexpensive multilayer techniques, and therefore provides a low cost, low volume solution to the problems of the prior art.
- FIG. 1 shows a multilayer substrate arrangement 100 that, when assembled, provides a device having transmission line characteristics. That is, a transmission line device is formed between a signal input port 101 disposed on a top substrate 102 and a signal output port 103 disposed on a bottom substrate 104. Further, intermediate substrates 106-108 (three shown, but could be more or less, as necessary) provide support structure for conductive patterns, or layers 110-1 12, which layers at least partially enclose an area on their respective dielectric substrates 106-108. Though not shown, conductive patterns 1 10- 1 12 are connected by conductive vias at alternating ends of each half-ring to form a continuous conductive path.
- Another conductive layer 1 14 is disposed on a first major surface 1 16 of the bottom substrate 104, and connected to the others using a conductive via, not shown.
- the top substrate 102 further includes a metallized area 1 18 that serves as a ground plane for the transmission line device.
- the bottom substrate 104 preferably includes a second ground plane, disposed on a second major surface 120 thereof, which second ground plane generally insures a more stable circuit package due to the shielding, symmetry and boundary effects of the second ground plane.
- conductive vias 122, 124 are used to carry the input and output signals through the top substrate 102 and the bottom substrate 104, respectively. In this manner, a multiple-turn coil is provided that is substantially adjacent to one, or preferably two, ground plane(s) to effect a low-volume transmission line device.
- the dielectric substrates 102, 104, 106-108 are formed using ceramic materials that can be co-fired with a co-fireable metal composition.
- the conductive layers 1 10-1 12, 1 14 are preferably deposited on the dielectric substrates as provided by, for example, DuPont's Green TapeTM, Systems, thereby producing conductive layers having relatively high conductance values.
- the conductive vias 122, 124— as well as the vias formed on the intermediate substrates 106-108, not shown— are made by at least partially filling the volume of spatially arranged, pre-punched holes in the ceramic using the co- fireable metal composition.
- conductive layers 110-112 are shown in FIG.
- annulus 1 as being annulus structures in the form of a half-ring, other annulus structures can be readily employed depending on the application requirements, as next described.
- input / output terminals are shown here as being on opposite surfaces of the package, it is understood that they could easily be placed on the same surface. It is critical only that the transmission line device is electrically positioned between the input and output terminals.
- FIG. 2 shows a multilayer substrate arrangement 200 that employs full-ring annulus structures as the conductive layers, in accordance with an alternate embodiment of the invention. That is, annulus 210 comprises a nearly complete circular layer that substantially encloses an area 213 on dielectric substrate 206. Similarly, annuli 21 1 , 212 comprise near complete circular layers that substantially enclose areas on their dielectric substrates 207, 208, respectively, which areas correspond to the substantially enclosed area 213.
- Employing annulus structures 210-212 in this manner provides for increasing the physical length of the conductive layers— and hence the electrical length of the transmission line- using the same number of ceramic layers. Of course, this allows for reduced volume of dielectric material required and significantly lower manufacturing costs, as compared to transmission line designs of the prior art.
- FIG. 3 shows yet another multilayer substrate arrangement 300 that employs spiral structures as the conductive layers.
- spiral conductors 310-312 and 314 . are disposed on dielectric substrates 306-308 and 304, respectively, to effect a multilayer transmission line device in accordance with the present invention.
- the spiral structures advantageously provide increased physical— and electrical— length for those applications with such requirements.
- such applications include those circuits operating in the 100 MHz - 3 GHz- frequency range, which frequencies require longer conductive lengths than do high frequency applications.
- the present invention allows for the manufacture of a low-volume transmission line device that can be used at frequencies substantially lower than those frequencies attainable using prior art techniques.
- FIG.s 1 -3 illustrate the use of vertically stacked conductive layers on a plurality of vertically adjacent dielectric substrates
- the present invention further anticipates the use of conductive layers that are horizontally stacked on two or more substrates.
- FIG. 4 shows a multilayer substrate arrangement 400 that employs a plurality of conductive strips arranged on adjacent dielectric substrates to effect a device having transmission line characteristics.
- the horizontally stacked arrangement includes a top substrate 402 and a bottom substrate 404, as well as conductive vias— not shown— for carrying the input/output signals to/from the intermediate dielectric substrate.
- Dielectric substrate 403 includes the horizontally stacked conductive strips 406-408 (three shown, but could be more or less, as necessary) , and conductive vias— also not shown— for passing the electrical signal between the dielectric layers.
- Conductive strips 410, 41 1 are horizontally arranged on a first major surface 412 of dielectric substrate 404 and coordinate with conductive layers 406-408 to form a multiple- turn coil.
- the multilayer arrangement 400 further includes a metallized area 414 that serves as a ground plane for the transmission line device.
- a second major surface of dielectric substrate 404 preferably includes a metallized area 416 that serves as a second ground plane for the transmission line device.
- FIG. 4 illustrates a coil having only a few turns
- the dielectric substrates 403, 404 could have many conductive strips, horizontally arranged to provide the required number of turns (i.e., for increased electrical length).
- FIG. 5 shows an exploded view of a power splitter/combiner 500, in accordance with the present invention.
- Top substrate 502 includes an input/output terminal 503 for proving an input/output signal to/from a pair of transmission line devices 421 , 423.
- bottom substrate 504 includes output/input terminals for porting signals from/to the devices.
- top substrate 502 includes a metallized area 505 that serves as a ground plane for the transmission line devices, while the bottom substrate preferably includes a second ground plane 507.
- intermediate dielectric substrate 506 supports primary conductive layers 421-1 , 423-1 and node 425.
- a first major surface of the bottom substrate 504 supports secondary conductive layers 421 -2, 423-2, which are disposed substantially adjacent to the intermediate substrate 506 (and connected to primary conductive layers 421 -1 , 423-1 using conductive vias, not shown). Manufacturing a power splitter/combiner in this manner allows for increased design flexibility because a broader range of Zfj values can be attained in a smaller volume package.
- FIG. 6 shows an exploded view of a multiple transmission line device 600, designed in accordance with the present invention.
- Top substrate 602 and a second major surface of bottom substrate 604 are effectively identical to those embodiments already described.
- Intermediate substrate 603 is shown to support the primary coil structure for both a horizontally stacked conductor 606 and a vertically stacked conductor 608.
- the vertically stacked conductor 606 is produced in substantially the same way as earlier described.
- the horizontally stacked conductor 606 is produced as follows: a plurality of conductive strips 606-1 are disposed on the intermediate dielectric.
- a second plurality of conductive strips 606-2 are arranged on a first major surface of the bottom substrate 604.
- Conductive strips 606-2 are arranged- in such a manner as to, when connected to the conductive strips 606-1 by conductive vias (not shown), produce a horizontally oriented coil. Orienting a second of two required transmission line devices in this manner helps to avoid the problems of undesired electromagnetic coupling that would otherwise be present if the coils were substantially parallel to each other, as is common in prior art circuits.
- FIG. 7 shows a preferred embodiment for a phase inverting, impedance transforming circuit, as it might be constructed according to the invention.
- Electrical nodes 621-624 are shown on a top substrate 702 as input/output pads electrically coupled to conductive vias. These conductive vias, as well as others that are appropriately placed throughout the nine substrate layers, are used to pass signals from one layer to another, in a well known manner.
- the circuit arrangement 700 comprises one, three-quarter wave transmission line device 707 and three, one-quarter wave transmission line devices 715-717.
- the longer coil structure 707 is embodied using sections 707-1 disposed on substrate 703 and coil section 707-2 disposed on dielectric substrate 704.
- a metallized area 71 1 is selectively deposited on substrate 712 and serves as an embedded ground plane for coil structure 707, in accordance with the present invention.
- Conductive via 714 is used to pass the electrical signal from the first coil section 707-1 to the second coil section 707-2. In this manner, a relatively long conductor can be confined to a small area by taking advantage of the available space in the z-direction (i.e., height) available, while not suffering from the inter-coil problems seen in the prior art.
- the three, one-quarter wave transmission line devices 715- 717 are similarly disposed on layers 6, 7, and 8.
- substrate 718 supports first coil sections 715-1 , 716-1 , 717-1
- substrate 720 supports secondary coil sections 715-2, 716-2 and 717-2.
- an embedded ground plane 719 is deposited between the first and second coil stages for each of the one-quarter wave transmission line devices, in accordance with the present invention.
- an optional ground plane 721 is deposited on a dielectric substrate 722 (i.e., bottom substrate), to provide an improved capacitance rating for each of the transmission line devices disposed between the top substrate 702 and the bottom substrate 722.
- the present invention ensures a low cost, low volume solution for those electrical circuits employing a plurality of transmission line devices, even those required to operate at relatively low frequencies.
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Waveguides (AREA)
Abstract
Description
Claims
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/187,967 US5467064A (en) | 1994-01-28 | 1994-01-28 | Embedded ground plane for providing shielded layers in low volume multilayer transmission line devices |
US08/189,030 US5426404A (en) | 1994-01-28 | 1994-01-28 | Electrical circuit using low volume multilayer transmission line devices |
US187967 | 1994-01-28 | ||
US189030 | 1994-01-28 | ||
US08/187,951 US5499005A (en) | 1994-01-28 | 1994-01-28 | Transmission line device using stacked conductive layers |
US187951 | 1994-01-28 | ||
PCT/US1994/014377 WO1995020829A1 (en) | 1994-01-28 | 1994-12-12 | Electrical circuit using low volume multilayer transmission line devices |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0700584A1 true EP0700584A1 (en) | 1996-03-13 |
EP0700584A4 EP0700584A4 (en) | 1996-05-15 |
Family
ID=27392327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95906635A Withdrawn EP0700584A4 (en) | 1994-01-28 | 1994-12-12 | Electrical circuit using low volume multilayer transmission line devices |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0700584A4 (en) |
JP (1) | JPH08508615A (en) |
AU (1) | AU1513795A (en) |
WO (1) | WO1995020829A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6556099B2 (en) * | 2001-01-25 | 2003-04-29 | Motorola, Inc. | Multilayered tapered transmission line, device and method for making the same |
CN103117440B (en) * | 2013-02-07 | 2015-05-27 | 上海安费诺永亿通讯电子有限公司 | Low-loss flat transmission line |
JP6327639B2 (en) * | 2014-04-18 | 2018-05-23 | 日本電信電話株式会社 | Right angle solenoid inductor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3164790A (en) * | 1963-02-12 | 1965-01-05 | Boeing Co | Sinuously folded quarter wave stripline directional coupler |
DE4239990A1 (en) * | 1991-11-27 | 1993-06-03 | Murata Manufacturing Co | Chip type directional coupler - has number of substrates with electrode films stacked together and produced of sintered ceramic |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE426894B (en) * | 1981-06-30 | 1983-02-14 | Ericsson Telefon Ab L M | IMPEDANCY COAXIAL TRANSFER FOR MICROVAG SIGNALS |
US4701727A (en) * | 1984-11-28 | 1987-10-20 | General Dynamics, Pomona Division | Stripline tapped-line hairpin filter |
JPH0446405A (en) * | 1990-06-13 | 1992-02-17 | Murata Mfg Co Ltd | Delay line and its manufacture |
JP2817487B2 (en) * | 1991-12-09 | 1998-10-30 | 株式会社村田製作所 | Chip type directional coupler |
-
1994
- 1994-12-12 EP EP95906635A patent/EP0700584A4/en not_active Withdrawn
- 1994-12-12 AU AU15137/95A patent/AU1513795A/en not_active Abandoned
- 1994-12-12 JP JP7520038A patent/JPH08508615A/en active Pending
- 1994-12-12 WO PCT/US1994/014377 patent/WO1995020829A1/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3164790A (en) * | 1963-02-12 | 1965-01-05 | Boeing Co | Sinuously folded quarter wave stripline directional coupler |
DE4239990A1 (en) * | 1991-11-27 | 1993-06-03 | Murata Manufacturing Co | Chip type directional coupler - has number of substrates with electrode films stacked together and produced of sintered ceramic |
Non-Patent Citations (1)
Title |
---|
See also references of WO9520829A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU1513795A (en) | 1995-08-15 |
EP0700584A4 (en) | 1996-05-15 |
JPH08508615A (en) | 1996-09-10 |
WO1995020829A1 (en) | 1995-08-03 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: HUANG, RONG-FONG Inventor name: KOMMRUSCH, RICHARD, S. Inventor name: GU, WANG-CHANG, A. |
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A4 | Supplementary search report drawn up and despatched | ||
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18D | Application deemed to be withdrawn |
Effective date: 19990605 |