EP0691049A1

EP0691049A1 - Circuit for deriving a quality signal dependent on the quality of a received multiplex signal

Info

Publication number: EP0691049A1
Application number: EP94911061A
Authority: EP
Inventors: Djahanyar Chahabadi; Matthias Hermann; Lothar Vogt; Juergen Kaesser
Original assignee: Blaupunkt Werke GmbH
Current assignee: Blaupunkt Werke GmbH
Priority date: 1993-03-24
Filing date: 1994-03-22
Publication date: 1996-01-10
Anticipated expiration: 2014-03-22
Also published as: US5696830A; DE59403123D1; JPH08508142A; EP0691049B1; JP3640669B2; WO1994022228A1

Abstract

In a circuit for deriving a quality signal dependent on the quality of a received multiplex signal in a stereo radio receiver. The multiplex signal contains a sum signal (L+R) in the base band, an auxiliary carrier modulated with a difference signal (L-R) and a pilot signal at half the frequency of the auxiliary carrier, the multiplex signal in digital form is multiplied by a reference carrier obtained from a scanning pulse generated in the radio receiver in two phase positions mutually offset by 90°. The mixed signals obtained by the multiplication are multiplied by a correction signal to form corrected mixed signals which are added and taken together with the sum signal to a matrix circuit to form stereo audio signals (L, R). The mixed signals are also multiplied by the other correction signal. The products of these multiplications are subtracted from each other and low-pass-filtered.

Description

Circuit arrangement for deriving a quality signal which is dependent on the quality of a received multiplex signal

The invention relates to a circuit arrangement for deriving a quality signal dependent on the quality of a received multiplex signal in a stereo radio receiver, the multiplex signal being a sum signal (L + R) in baseband, a subcarrier modulated with a difference signal (LR) and a pilot signal with half Frequency of the subcarrier contains.

In the case of car radios in particular, the reception quality can fluctuate greatly - for example due to drops in the received field strength, through multi-path reception or through the reception of interference signals. In order to keep the resulting interference as low as possible, various measures for masking these interference in the LF signal are known. For example, if reception is poor, it is possible to temporarily attenuate the LF signal or the

Reduce stereo channel separation. However, these known measures require that the signal quality can be determined correctly.

The object of the present invention is to provide a circuit arrangement for deriving at least one quality signal which is dependent on the quality of a received signal. This object is achieved in that the multiplex signal is multiplied in digital form with a reference carrier obtained from a sampling clock generated in the radio receiver in two phase positions shifted by 90 ° with respect to one another in that the mixed signals resulting from the multiplication each have a correction signal to form corrected mixed signals are multiplied, that the corrected mixed signals are added and fed together with the sum signal to a matrix circuit to form stereo audio signals (L, R), that the mixed signals are further multiplied by the other correction signal and that the products of these multiplications are subtracted from one another and low-pass filtered become.

The circuit arrangement according to the invention enables the detection of audible interference and is based on the evaluation of the symmetry of the auxiliary carrier-frequency stereo difference signal. It is essential in this procedure that an undisturbed signal due to the

Two-sideband amplitude modulation must be symmetrical to the carrier. In the circuit arrangement according to the invention, this symmetry is ensured in the case of an undisturbed signal by feeding the side bands to be compared in the correct phase. An asymmetry therefore leads to the conclusion that there is an audible disturbance in the LF signal.

A further development of the invention contributes to symmetry in the undisturbed case in an advantageous manner in that, in order to form the correction signals, the multiplex signal is multiplied by a reference pilot signal phase-coupled with the reference carrier in two phase positions shifted by 90 ° with respect to one another, in that the resulting further mixed signals are low-pass filtered and that the low-pass filtered further mixed signals for Formation of the first correction signal are squared and subtracted from one another and are multiplied with one another and with two to form the second correction signal.

The effect of a fluctuation in the amplitude of the pilot signal which is not relevant for the purposes of the circuit arrangement according to the invention can be suppressed by squaring and adding the low-pass filtered further mixed signals to form a signal representing the amplitude of the pilot signal and by the correction signals using the amplitude of the pilot signal representing signal can be controlled in the sense of normalizing their amplitude.

In general, the direction of the asymmetry of the sidebands is not important, so that an amount is provided after the low-pass filter. This is preferably done by squaring.

The quality signal derived with the circuit arrangement may well be an analog signal which can assume intermediate values between two limit values. However, a binary signal can be used for many purposes. One embodiment of the invention therefore provides that the amount formed is compared with a threshold value and the comparison result is output as a quality signal.

An embodiment of the invention is shown in the drawing using several figures and explained in more detail in the following description. It shows:

1 is a block diagram of the circuit arrangement according to the invention, FIG. 2 shows a block diagram of a part of a circuit arrangement for deriving the correction signals and which is only shown schematically in FIG. 1

Fig. 3 is a block diagram of one in the

Circuit arrangement according to Fig. 2 filter used.

Identical parts are provided with the same reference symbols in the figures. The exemplary embodiment and parts thereof are shown as block diagrams. However, this does not mean that the circuit arrangement according to the invention is limited to implementation using individual circuits corresponding to the blocks. Rather, the circuit arrangement according to the invention can be implemented in a particularly advantageous manner with the aid of highly integrated circuits. In this case, digital signal processors can be used which, with suitable programming, carry out the processing steps shown in the block diagrams. The circuit arrangement according to the invention, together with further circuit arrangements within an integrated circuit, can form essential parts of a radio receiver.

1, a digital multiplex signal MPX is supplied via an input 1, which contains a sum signal L + R, a subcarrier modulated with a difference signal L-R and a pilot signal in a manner known per se. With the introduced

VHF stereo broadcasting has a frequency of 38 kHz, while the pilot signal has a frequency of 19 kHz. The angular frequency of the pilot signal is referred to below as w.

^' P For the demodulation of the carrier-frequency signal, multipliers 2, 3, 4, 5 and an adder 6 are provided in the stereo decoder according to FIG. 1, from whose output the demodulated difference signal LR together with the multiplex signal one of two further adders via a further multiplier 7 8, 9 existing matrix circuit is supplied. The decoded digital stereo audio signals L and R reach outputs 12, 13 via two low-pass filters 10, 11.

With the aid of multipliers 2, 3, the multiplex signal is first multiplied by a reference carrier, the multiplication in 3 being carried out with a reference carrier which is phase-shifted by 90 ° compared to the multiplication in 2. The samples of the reference carriers are read from a table 14, the frequency of the reference carriers being an integer fraction of the sampling frequency on which the multiplex signal is based. The sampling frequency is generated in a manner known per se in the radio receiver.

With an advantageous sampling frequency of 228 kHz, there are six sampling values per period of the reference carriers. The sampling values of the multiplex signal MPX result in MPX: = MPX (n «T), where n, like the variables listed below, is an integer which denotes the individual sampling values.

The multiplex signal has the following form:

MPXn = ( ^v Ln + Rn) + (Ln-Rn) ' ^« sin (2wpn * T + 2α) + VÄ ^« sin (wpn ^« T + α).

The following mixed signals result from multiplication with the values of the reference carrier sin (2w t) or cos (2w t) read from table 14:

Imr1 = MPXn «sin (2wpnT) = ) ^« Cos 2α + ... or (1)

Imr2 = MPXn • cos (2wpnT) = i (Ln-Rn) -sin 2α + ... (2) Α is the phase difference between the received pilot signal and a reference pilot signal generated from the sampling clock within the receiver. Elements with a higher frequency are not shown in equations (1) and (2), since they are later filtered out by the low-pass filters 10, 11.

The signals Imr1 and Imr2 are fed to further multipliers 4, 5, the output signals of which - hereinafter referred to as further mixed signals - can be described as follows:

Ims1 = Imr1 ^« G38c = - C n-Rn) • cos2α * G38cn

Ims2 = Imr2-G38s = - (Ln-Rn) • sin2α «G38sn.

As will be described later, the signals G38s = sin2α and G38c = cos2α. This results in the following mixed signals:

Ims1 = ^ - (Ln-Rn) • cos2cccos2α.

Ims2 = -i (Ln-Rn) • sin2ccsin2α

So that the output signal of the adder 6 ^ (L -R).

Through a suitable standardization with an added value

D = 2 with the help of Multip ^r lizierers 7 is formed then (Ln-Rn).

D can also be used to smoothly switch the channel separation from mono to stereo reception. With mono operation D = 0.

The subsequent matrix circuit from the adders 8, 9 and the low-pass filters 10, 11 then generate the digital output signals L and R. In an advantageous manner, the low-pass filters can also be designed such that in addition to the suppression of the frequencies above the useful signal, the de-emphasis is carried out.

The generation of the correction signals G38c and G38s supplied to the multipliers 4 and 5 is first explained below with reference to FIG. 1. The multiplex signal MPX First multiplied by two reference pilot signals sin (wt) and cos (wt), which are phase-shifted by 90 ° with respect to one another and are read from a table 16. The output signals of the multipliers 14, 15 are passed via low-pass filters 17, 18, which emit signals SPC1 = VA ^« COS α and SPC2 = JA ^« sin α. Because of the much lower frequency of these signals compared to the pilot signal, the sampling rate is reduced at 19, 20. This saves considerable effort in the network 21. The output signals of these circuits are fed to the network 21, with the aid of which the correction signals G38s and G38c are derived. Before a description of the other parts of FIG. 1, the network 21 is described in more detail with reference to FIGS.

The signals SPC1 and SPC2 supplied via the inputs 23, 24 are squared at 25, 26 and multiplied at 27. The squared signals SPC1 and SPC2 are subtracted from each other at 28 and added at 29. The product of the two signals is multiplied by "2 ¹ at 30, so that the following signals are generated:

A = (SPC1) ² + (SPC2) ² F38c = (SPC1) ² - (SPC2) ² = A-cos 2α F38s = 2 ^« (SPC1 • SPC2) = A ^« sin 2α

The quantity A characterizes the amplitude of the received pilot signal and is converted with the aid of a subtractor 31 and a threshold value circuit 32 into a switching signal STI which can be taken from an output 33 and used to indicate stereo reception.

The signals F38c and F38s are freed from the component A with the aid of filters 34, 35, to which the signal A is also supplied, so that the influence of fluctuations in the amplitude of the pilot signal on the stereo decoding is eliminated. The signals G38c and G38s freed from component A can Outputs 36, 37 are removed and fed to the multipliers 4, 5 (FIG. 1).

An embodiment of the filters 34, 35 is shown in FIG. 3. It consists of two adders 41, 42, two

Multipliers 43, 44 and a delay element 45.

Inputs 46, 47, 48 are fed signals F38c and A and a real number μ, with which the step size can be controlled. The signal at the output 49 of the filter according to FIG. 3 then results

G38cn - A ^« G38cn-_1,) or

G38sn = G38sn-_1. + μ (F38sn - A ^« G38sn- .1).

After a settling time, G38cn = cos 2α or, in the case of filter 35 (FIG. 2), G38s = sin 2α. The number μ can be fixed. However, it is also possible to vary the number μ and thus the settling time, for example to implement a short settling time corresponding to a high bandwidth of the filter immediately after a transmitter has been reset, which is then reduced to a smaller bandwidth for the purpose of improving the signal-to-noise ratio.

The parts 50 to 59 of the circuit arrangement according to FIG. 1 represent a symmetry detector, the function of which is based on the fact that when the

Stereo multiplex signal with a reference carrier, which is in quadrature with the carrier of the stereo difference signal, in the case of sidebands with the same high amplitude, no output signal is produced. Such a signal is generated in any case in stereo decoders with quadrature demodulation of the carrier-frequency stereo difference signal, in which multiplication is carried out with two reference carriers which are phase-shifted by 90 ° and the phase position relative to the carrier is determined by a PLL circuit. When using such stereo decoders, the signal obtained from the demodulation of the quadrature component can be fed directly to a low-pass filter 53, which is followed by a sampling rate conversion 54 around the divider 24. An amount is then formed at 55, whereupon the resulting signal SD1 is compared with a threshold value SDS at 56 and 57. At 58 the comparison result is evaluated in such a way that the signal ASD at the output 59 has the value 1 if the signal SD1 is greater than the threshold value SDS.

For a stereo decoder, in which the subcarrier-frequency stereo difference signal is multiplied by two reference carriers which are phase-shifted by 90 ° relative to one another and whose phase position is not fixed to the carrier, the signal processing described below is required before the low-pass filtering at 53. The signal Imr1 is multiplied by the correction signal G38s. The signal Imr2 is multiplied at 51 by the correction signal G38c. The output signals of the multipliers 50, 51 are subtracted from one another at 52 and fed to the low-pass filter 53.

The signal ASD representing the reception quality can be used to switch from stereo to mono reception and can be supplied to the multiplier 7 instead of the signal D, for example. However, in addition to the symmetry of the sidebands of the subcarrier-frequency difference signal, other quantities can be used to form the signal D, such as the received field strength via the amplitude of the IF signal or spectral components in the multiplex signal above 60 kHz. These criteria can also be combined in a suitable manner, which is indicated in FIG. 1 in the form of a circuit 22.

Claims

Expectations

1. Circuit arrangement for deriving a quality signal dependent on the quality of a received multiplex signal in a stereo radio receiver, the multiplex signal being a sum signal (L + R) in baseband, a subcarrier modulated with a difference signal (LR) and a pilot signal with half the frequency of the Subcarrier contains, characterized,

that the multiplex signal is multiplied in digital form with a reference carrier obtained from a sampling clock generated in the radio receiver in two phase positions shifted by 90 ° relative to one another,

that the mixed signals resulting from the multiplication are multiplied by a correction signal to form corrected mixed signals,

- That the corrected mixed signals are added and supplied together with the sum signal to a matrix circuit to form stereo audio signals (L, R), that the mixed signals are further multiplied by the other correction signal and

- That the products of these multiplications are subtracted from one another and low-pass filtered.

2. Circuit arrangement according to claim 1, characterized in that, in order to form the correction signals, the multiplex signal is multiplied by a reference pilot signal which is phase-locked to the reference carrier in two phase positions shifted by 90 ° relative to one another, that the resulting further mixed signals are low-pass filtered and that the low-pass filtered further mixed signals are squared and subtracted from one another to form the first correction signal and are multiplied with one another and with two to form the second correction signal.

3. Circuit arrangement according to claim 2, characterized in that the low-pass filtered further mixed signals to form a signal representing the amplitude of the pilot signal are squared and added.

4. Circuit arrangement according to claim 3, characterized in that the correction signals are controlled with the aid of the signal representing the amplitude of the pilot signal in the sense of normalizing its amplitude.

5. Circuit arrangement according to one of the preceding claims, characterized in that an amount formation is provided after the low-pass filter.

6. Circuit arrangement according to claim 5, characterized in that the amount is formed by squaring.

7. Circuit arrangement according to one of claims 5 or 6, characterized in that the amount formed is compared with a threshold value and the comparison result is output as a quality signal.