EP0671073A1

EP0671073A1 - Fm threshold expansion detector circuit

Info

Publication number: EP0671073A1
Application number: EP93921883A
Authority: EP
Inventors: Kenji Yokoyama
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-09-29
Filing date: 1993-09-29
Publication date: 1995-09-13
Also published as: WO1995009480A1; JPH08503836A

Abstract

An FM detector circuit can simultaneously reduce noise in the bandwidth ratio, clip noise produced by reduction of the bandwidth and noise produced by tracking errors resulting from changes in the signal level. The FM detector circuit contains an AVR circuit (2) for making the input signal level constant, a tracking band pass filter (5) with a multilevel RF amplifier circuit (4) linked with the AGC circuit (2) for producing a requisite level of input signal, a variable capacitance diode linked with the amplifier circuit (4), where the filter has a variable central frequency and follows the FM signal from the amplifier circuit (4) for enlarging the apparent bandwidth of the input signal, and a PLL detector circuit (14) linked with the band pass filter (5). The detector circuit also contains a loop for amplification and feedback of the output signal from the PLL detector circuit (14) to the tracking band pass filter (5).

Description

FM-SCH ELLENER LEITER DETECTOR CIRCUIT

The invention relates to an improved detector circuit for detecting a frequency-modulated signal, and in particular to a detector circuit which exerts its influence when used to demodulate a signal at a weak level, in particular to a detector circuit for use in signal demodulation via a satellite.

PRIOR ART A conventional PLL detector circuit has a configuration such that a frequency-modulated signal FM-s with the waveform, for example according to FIG. 3, and a signal from a VCO (Voltage Control Oscillator) 24 into the phase comparator 21 2 are input, and a voltage in the phase difference ratio between the two signals is output by the phase comparator 21, amplified in a DC voltage amplifier circuit 23 and then fed back to the VCO 24. In the conventional circuit of Fig. 2, a low-pass filter (hereinafter referred to as LPF) 22 is incorporated between the phase comparator 21 and the DC amplifier circuit 23, and the voltage returned to the VCO 24 via the LPF 22 is obtained as a PLL detector output voltage. It is therefore known that the PLL circuit 26 according to FIG. 2 works as an improved FM detector circuit.

However, since the level of a signal, for example a signal transmitted via a satellite, is lower than that above ground

ORIGINAL DOCUMENTS transmission level, a further improved FM detector circuit is required. In this context, it is already generally known that noise power Pn is expressed using the equation Pn = kTB (k = Boltzmann constant, T = absolute temperature, B = bandwidth) and is proportional to the bandwidth. One method of realizing a drop in noise power is to increase the C / N ratio (carrier / noise) by reducing the pass band of the frequency modulated signal before the signal is input to the PLL detector circuit.

However, if the bandwidth is reduced,

Portions of the frequency-modulated signal FM-s, which is deeply modulated (the hatched portions according to Fig. 4), are cut off and the signal is incorrectly modulated, which causes the disadvantage of generating new noise (hereinafter referred to as "break-off noise").

Especially since the required bandwidth (BW) is expressed with the following equation:

BW = deviation of frequency modulation + (bandwidth of the video signal x2) + energy diffusion, it is considered to use this equation in satellite radio, using an ASTRA satellite, which is used very frequently in Europe. Since the deviation is 13.5 MHz, the video signal bandwidth is 5.5 MHz and the energy diffusion is 2 MHz, the required bandwidth BW is given with the following equation: BW = 13.5 MHz + 5.5 x 2 MHz + 2 MHz = 26 MHz.

In other words, a bandwidth of 26 MHz is required. If the bandwidth BW is halved to 13 MHz for the sake of simplicity, an increase in the C / N is given using the following equation: Increase in the C / N (dB) = -10 log (current bandwidth / required bandwidth) = -10 log (13/26) = 3 (αB). So the C / N ratio is increased by 3 dB.

If, however, an attempt is made to reduce the noise power Pn using the method described above, the drop in the noise power Pn and the blanking of the breaking noise have a smear ratio, since the breaking noise increases. In the case of a weak signal, it sometimes happens at a certain point in time that the phase comparator does insufficient work because the level of the frequency-modulated signal FM-s input into the phase comparator 21 changes briefly. In such a case, there is a disadvantage that noises occur due to tracking errors of the PLL detector circuit 26.

SUMMARY OF THE INVENTION It is an object of the invention to provide an FM detector circuit of the type mentioned at the outset which simultaneously reduces noise in the bandwidth ratio as described above, break-off noise generated by bandwidth reduction and noise generated by tracking errors due to changes in a signal level.

Since an FM signal contains a single spectrum at all times, a bandpass filter (BPF) with a very narrow band is sufficient to acquire each of the individual spectra. So if a narrow bandpass filter follows the short-term single spectrum of the FM signal, a signal can be correctly demodulated without cutting off a modulated signal component, even if the bandwidth of the bandpass filter is reduced.

Therefore, in this invention, a narrow bandpass filter (hereinafter referred to as "tracking BPF") with a capacitance diode with narrowband characteristics of a PLL detector circuit is direct upstream, so that signals from this BPF and from the PLL detector circuit are amplified and fed back to the capacitance diode of the track tracking BPF in order to increase the apparent bandwidth of the BPF and to reduce noise in the bandwidth ratio and break-off noise, and an AVR circuit ( AVR (Automatic Gain Control; AGC = Automatic Gain Control) is placed behind an amplifier to amplify the signal sufficiently to keep the level of a weak signal constant and to reduce the noise generated by tracking errors.

Thus, the present invention provides an improved PLL detector circuit which includes a phase detector circuit having a phase comparator circuit for detecting a phase difference between an FM signal and an output signal of the VCO with a capacitance diode, a filter and a DC differential amplifier Feedback of the output voltage of the phase detector circuit after the VCO, an AVR

Circuitry for holding the FM input signal at a constant level and including a tracking BPF with a capacitance diode that runs in synchronism with and follows the FM input signal. The two output signals of the differential amplifier circuit of the PLL detector circuit are applied simultaneously to the VCO and to the tracking BPF so that the VCO can follow the FM input signal and at the same time the tracking BPF can follow the FM input signal by changing its central frequency. The

Mock tape is thus expanded.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention are explained below with reference to the drawing. Show it : 1 is a block diagram with an FM threshold expansion detector circuit according to the invention,

2 is a block diagram with a known PLL detector circuit,

3 is a schematic illustration of an example of the waveforms of FM input signals.

4 shows a schematic representation of a waveform to explain the phenomenon that portions of a deeply modulated FM signal are cut off when detecting,

Fig. 5 is a schematic representation for explaining a track tracking BPF with a narrow band and its dummy band, Fig. 6 is a schematic representation of a

Relationship between a transit time and the tracking BFP band, and

Fig. 7 is a block diagram with a main part of a detector circuit according to the invention. PREFERRED EMBODIMENT OF THE INVENTION

In Fig. 1, an FM input signal FM-s according to Fig. 3 is applied to an input terminal 1. The

Input signal is amplified in the AVR circuit 2 and set to a constant level. In Fig. 1, reference numeral 3 denotes an AVR terminal.

The input signal set to a constant signal in the AVR circuit 2 is amplified to a required level in an RF amplifier circuit 4 and input to the tracking follower BPF 5. In this invention, it is particularly important that the tracking BPF is included in a stage behind the AGC circuit 2. Because if the tracking BPF 5 is included in a stage in front of the AGC circuit 2, a phase comparator sometimes does not work when a low level signal is applied because the input signal level changes briefly. In In such a case, the object of the invention cannot be achieved since the input signal is not reproduced and appears as noise. Therefore, according to the invention, the tracking BPF 5 is included in the stage after the AVR circuit 2 and the problem just mentioned does not occur. In this sense, the sequences are a characteristic of the invention.

The signal arriving via the tracking BPF 5 goes to one side of a phase comparator 12 and the output signal of a VCO 13 in a PLL detector circuit 14 reaches the other side of the phase comparator 12. When the frequency of the signal from the tracking BPF 5 from that of the signal from the VCO 13 deviates, the phase comparator 12 supplies a voltage in the phase difference ratio between the two input frequencies and reaches the DC differential amplifier 10 via the LPF 11 via an amplifier 6 and an LPF 7 to the track following BPF 5. The voltage is supplied until the frequencies of the input signals have equalized. The phase comparator 12, the LPF 11, the DC voltage differential amplifier circuit 10, the amplifier 9 and the VCO 13 form the PLL detector circuit 14, and the amplifier 6 with the LPF 7 forms the phase control circuit 8.

In the aforementioned PLL detector circuit 14, for example, when the frequency of the VCO 13 is lower than the input frequency, the voltage of the VCO 13 rises continuously until the frequency of the VCO 13 has adjusted to the input signal frequency, and the voltage is maintained when both frequencies are the same (PLL operation). At this time the output signal of the phase comparator 12 delayed in phase by 90 ° against the input signal.

It is also important for the invention that the number of stages of each of the amplifiers 9 and 6 is as small as possible. So generates the frequency of the VCO

13 unchangeable a running time without brief synchronous running with the frequency of the input signal. If the transit time is long, it is impossible to follow the FM signal at a frequency that changes briefly. If the runtime becomes longer, the bandwidth must be increased. However, increasing the bandwidth precludes the attempt to reduce noise, which is the object of the invention and thus the solution to this object. According to the invention, the number of stages of each amplifier 6 or 9 is therefore set to the minimum value one in order to shorten the running time. If the output signal of the DC voltage differential amplifier 10 is sufficient, the amplifiers 6 and 9 need not be used. The relationship between the term and the

Bandwidth is explained in more detail below with reference to FIGS. 6 and 7. The output signal of the PLL detector circuit generally produces a phase delay of 90 ° with respect to the input signal. Even if the frequency of the signal in the phase comparator 12 from the tracking BPF is 5 f, the frequency of the VCO 13 changes only after f ₂ (f.,> F ₂ ). Since a signal with the frequency f ₂ with a phase delay time of 90 ° and a signal with the frequency f. Are simultaneously applied to the track tracking BPF, both signals have a central frequency of f ₂ and run at a frequency below f. synchronous. The input signal with the frequency f. Is thus deflected by the tracking BPF 5 (see FIG. 6). In order to correct this deflection, the bandwidth of the tracking BPF 5 must be increased at all times (the band shown in broken lines in FIG. 6). Therefore, the reinforcement level preferably has the minimum number one in order to shorten the term as much as possible. This point also represents a characteristic of the invention. According to the invention, an increase in the apparent bandwidth of the FM input signal in the tracking tracking BPF with a narrow band is permissible (see FIG. 5).

In the above-described embodiment according to the invention, for example, one end of the DC differential amplifier circuit 10 is connected to the OSC (oscillator) of the VCO 13 and the other end to the tracking follower BPF 5. However, if sufficient amplification is obtained by differential amplification of the circuit 10, or if the capacitance diode is sensitive enough, even if the output signal of the OSC terminal returns with the same phase after the tracking tracking BPF 5, the same effect can of course be obtained.

According to the above description, since the track tracking BPF 5 is forced to follow and synchronize with the FM input signal, demodulation according to the invention can be carried out correctly without cutting off a signal component. According to the invention, the two noises can thus be reduced or blanked out at the same time, this object is based on the invention, and reducing or blanking out the noise caused by tracking errors is therefore advantageous for the FM demodulation detector circuit.

Claims

PATENT CLAIMS

1. FM threshold extension detector circuit with an AVR circuit (2) for making the input signal level constant, with a tracking bandpass filter (5) with a multi-stage RF amplifier circuit (4) in connection with the AVR circuit (2) to obtain a required level of the input signal, and with a variable capacitance diode in connection with the amplifier circuit (4), the filter (5) having a variable central frequency and the FM signal from the amplifier circuit (4) to increase the apparent bandwidth of the Input signal follows, and with a PLL detector circuit (14) in connection with the bandpass filter (5), characterized by a loop for amplifying and returning the signal from the PLL detector circuit (14) after the tracking bandpass filter (5).

2. FM threshold expansion detector circuit according to claim 1, wherein the

Spachachlauf bandpass filter (5) is connected to a stage downstream of the AVR circuit (2).

3. FM welding extension detector circuit according to claim 1, wherein a low-pass filter for phase correction is arranged between the PLL detector output and the track tracking bandpass filter (5).

4. FM welding extension detector circuit according to claim 1, wherein the detector output signals of the PLL detector circuit (14)

Are differential output signals, one of which is applied to the VCO (13) after amplification in the same phase or directly, and the other output is supplied directly or to the VCO (13) after the amplification in the reverse phase or directly to the variable capacitance diode of the tracking bandpass filter (5), and that the The number of stages for amplifying each differential output signal is as small as possible.

5. FM threshold extension detector circuit according to claim 1 and 2, wherein the AVR circuit (2) operates at an input level (input level as a group) of -60 dBm or less.