EP0660044B1 - Control device for controlling switching devices - Google Patents

Description

The invention relates to a control device of the type mentioned in the preamble of claim 1.

Devices of this type are used, for example, for controlling and monitoring the burner and the ignition device for oil and gas fires and for monitoring switches for actuators such as fuel valves and ventilation flaps, with the microprocessor evaluating the information supplied via line voltage-carrying signal lines and issuing corresponding control commands. In particular because of the safety required when switching on and when operating oil and gas burners, the switch-off capability of the switching devices that switch safety-critical loads such as a fuel valve must be checked frequently in order to be able to detect a malfunction of the switching device before a dangerous situation arises.

A control device according to the preamble of claim 1 is known from US Pat. No. 4,974,179. Voltages of a burner or boiler to be monitored at relay contacts are transmitted to the inputs of multiplexers via signal lines and optocouplers. The optocouplers are used for electrical isolation and for digitizing the voltage signals into binary values "0" or "1". The binary values are transmitted serially from the multiplexers to a microprocessor. An optocoupler is required for each voltage to be monitored.

From DE-PS 30 44 047 C2 and the older priority DE-PS 30 41 521 C2 a control device for oil burners is known, in which information about the switching states of relay and sensor contacts is transferred to a microprocessor by means of an amplifier. The switching states of the relay contacts are fed via signaling lines carrying line voltage to an amplifier which is connected on the output side to an input of the microprocessor, so that the microprocessor must have a number of inputs corresponding to the number of amplifiers. Isolators such as e.g. are used for the electrical isolation of the signal lines and the microprocessor. Optocoupler or transmitter used. There is one isolator per signal voltage. The microprocessor is programmed to perform a number of tests to determine whether a system with switched consumers is actually going through a switch-on phase in the correct way. For this purpose, signals are read in by the microprocessor and compared with setpoints. In the event of a faulty consumer status, the microprocessor switches the consumers off.

Furthermore, in an arrangement known from DE-OS 41 37 204 for monitoring AC switches, mains voltage-carrying signal lines are connected via optocouplers to an interrogation unit of an AC voltage detector. The reporting lines are each connected to the optocoupler via a low-pass filter, which consists of a resistor and a capacitor connected in series with it. The switching states of the AC switches are queried and saved via the signal lines. In an evaluation unit connected downstream of the interrogation unit, the switching states are compared with a target state - open or closed - and then a switch state signal is formed, which contains at least one piece of information - error or no error - in total for all AC switches that occur. It cannot be determined from the switch status signal which AC switch can no longer be switched off, so that a simple display for diagnosis is not possible.

From DE-OS 38 01 952 a device for monitoring a reference voltage is known, in which several analog signals are fed to a microprocessor via a multiplexer and an A / D converter. Electrical isolation is not provided.

Optocouplers, for example, are used as isolators for the electrical isolation of the monitored system from the microprocessor. However, the optocouplers have the disadvantage that they are not fail-safe and have a higher failure rate compared to other electronic components, so that they have to be checked for a signal pretense even in an active operating state in safety-critical applications. Furthermore, the electromagnetic compatibility and thus the reliability of the control device decrease with an increasing number of optocouplers. Systems with many signal lines carrying mains voltage can incur high costs as long as an expensive isolating element such as an optocoupler or transmitter and an input pin on the microprocessor must be available per signal line.

The invention has for its object to design a control device with a control logic device according to the preamble of claim 1 such that it detects the information in the form of low-voltage signals about the state of switching devices that switch loads on or off in a simple and reliable manner , processed and transmitted to the control logic device.

According to the invention, the stated object is achieved by the features of claim 1.

An exemplary embodiment of the invention is explained in more detail below with reference to the drawing.

Fig. 1

eine Steuereinrichtung zur Betätigung mehrerer Schalteinrichtungen,

Fig. 2

eine Steuereinrichtung mit Schieberegistern und einer

Fig. 3

Spannungsdiagramme und

Fig. 4

eine Steuereinrichtung mit einem Testbaustein.

Show it:

Fig. 1

a control device for actuating a plurality of switching devices,

Fig. 2

a control device with shift registers and one

Fig. 3

Voltage diagrams and

Fig. 4

a control device with a test module.

1 shows a control device with a timer and control logic device 1 in the form of a microprocessor. It also contains two switching devices 2.1 and 2.2, two coupling elements 3.1 and 3.2 and a circuit block 4. The output of the first switching device 2.1, which switches a load L1 to a mains voltage U _PG lying between a phase P and a zero point G, is at the input of the first coupling element 3.1 connected, while the output of the second switching device 2.2, via which a further load L2 is fed by the mains voltage U _PG , is connected to the input of the second coupling element 3.2. The outputs of the coupling elements 3.1 and 3.2 are connected to inputs 4.1 and 4.2 of the circuit block 4 arranged in parallel, so that the low-voltage signals V 1 and V 2, which are applied to the taps between the switching devices 2.1 and 2.2 and the loads L1 and L2, respectively the coupling elements 3.1 or 3.2, which represent a signal line ML1 or ML2, are transmitted to the circuit block 4 for processing. The circuit block 4 is connected to the zero point line G via a line 4a. Next, the circuit block 4 is connected to the microprocessor 1 via two control lines 5a and 5b and a serial output DA and a serial data line 6 for transmitting the voltage levels U 1 and U 2 at the inputs 4.1 and 4.2. The control device can also be designed to control more than two loads, for example for n = 32 loads. It may also be that additional loads are controlled by the microprocessor 1 without the status of the associated switching devices being monitored, which is why they are not connected to the circuit block 4 like the loads L1 and L2 described.

The microprocessor 1 is programmed by a time program to switch the loads L1 and L2 on and off in a specific sequence during the switch-on phase, for example of a gas burner, by means of the switching devices 2.1 and 2.2 and to carry out various processes such as e.g. monitor the formation of a flame and, if necessary, switch off the entire system so that the gas burner is never in a potentially explosive situation. In continuous operation, the microprocessor 1 also executes a monitoring program for the detection of faulty states of the system to be controlled. In order to determine the state of one of the switching devices 2.1 or 2.2 - open or closed - the microprocessor 1 executes a test cycle which will be explained later. The frequency of the test cycles depends on the intended use of the control device and the corresponding legal regulations or standards. Automatic burner controls that comply with the EN 298 standard must detect a fault within three seconds of their occurrence. A test cycle is therefore typically every 200 milliseconds. In this way it is possible to reliably detect the state of each of the switching devices 2.1 and 2.2 within the prescribed three seconds even if the state of one of the switching devices 2.1 or 2.2 is currently changing during a test cycle.

When the switching device 2.1 is closed, as shown in FIG. 1, a current flows through this switching device 2.1 and the associated load L1. At the input of the coupling element 3.1 there is therefore an AC voltage as the low voltage signal V 1, which essentially corresponds to the mains voltage U _PG . When open the switching device 2.2, as shown in FIG. 1, is at the input of the coupling member 3.2 as a low voltage signal V₂ a DC voltage corresponding to the zero point G. The coupling elements 3.1 and 3.2 are used in a manner known per se to rectify and limit the low-voltage signals V 1 and V 2 to the processable input level of the circuit block 4 and to derive overvoltages to the zero point potential G to prevent the circuit block 4 from being destroyed by voltage or current pulses, for which they are connected to the zero point line G in a manner not shown. A signal voltage U 1 is thus present at the input 4.1, the shape and / or level of which differ significantly from the DC voltage U 2 present at the input 4.2 with the zero point level G.

The test cycle for determining the state of the switching devices 2.1 and 2.2 now consists in that the microprocessor 1 at a suitable point in time the signal voltages U 1 and U 2 at the inputs 4.1 and 4.2 of the circuit block 4 corresponding to a predetermined voltage level as binary numbers "0" or "1 "Capture in parallel and then transmitted via the serial output DA of the circuit block 4 and the serial data line 6 itself. A number "0" corresponds to an open state, a number "1" corresponds to a closed state.

The control device described enables the use of a control logic device 1, in particular a microprocessor, with a number of inputs which can be substantially smaller than the number m of loads L1 to Lm, the associated switching devices 2.1 to 2.m of which must be monitored for their contact position. In the case of control devices in which the control logic device 1 must be galvanically separated from the mains voltage U _PG for reasons of safety, there are further advantages with regard to reliability, electromagnetic compatibility and costs in that the control logic device 1 with only a few galvanic isolating elements from the circuit block 4 and can thus also be separated from the mains voltage U _PG , so that the number of galvanic isolators can also be significantly smaller than the number m. If one of the switching devices 2.1 to 2.m malfunctions, a simple display is possible, since the information about the state of each of the switching devices 2.1 to 2.m is present in the control logic device 1 and by simple means, for example with light-emitting diodes or with an LCD display, can be displayed.

Such a device can also be used as a signaling device for querying the position of switch contacts and displaying them in process systems.

Instead of the microprocessor 1, a microcontroller, a customer-specific circuit (application-specific integrated circuit, ASIC) or a programmable logic (programmable area logic, PAL) can also be used as the control logic device. The control device is suitable for operation in a DC voltage as well as in a AC network, whereby the mains voltage U _{PG can} also be in the low voltage range with a typical value of 24 V.

When operating the control device in a DC voltage network, synchronization for data acquisition is not necessary, but it is required when operating in an AC network. 2 and 3 show a control device for operation in an AC network with n = 16 switching devices 2.1 to 2.16 or timing diagrams of the voltages U _PG , U 1, U 2, U _R and U _{SH / LD, which will be} explained in more detail later. The control device has a circuit block 4, which consists of two shift registers 7.1 and 7.2 and a synchronization device 8. For the sake of clarity, only the switching devices 2.1 and 2.2 and the coupling elements 3.1, 3.2, 3.8, 3.9 and 3.16 are drawn. The shift registers 7.1 and 7.2 have eight parallel inputs 4.1 to 4.8 or 4.9 to 4.16 as well as a serial data input DE and a serial data output DA. In the control lines 5a and 5b and in the data line 6, optocouplers 9, 10 and 11 are arranged, which serve for the galvanic isolation between the microprocessor 1 and the circuit block 4 which is subject to mains voltage. The optocouplers 9 and 10 are followed by a NAND gate 9a and 10a for level reversal.

National Semiconductor's MM74HC165 modules can be used as shift registers 7.1 and 7.2, which have a clock input CL, a clock inhibit input INH and a shift / load input SH / LD to control data acquisition and data output. The procedure is described in "MM74HC / 74HC High-Speed CMOS Family Databooklet, National Semiconductor Corporation, 1981".

The synchronization device 8 has two inputs 8a and 8b and one output 8c. The input 8a is connected to the output of the NAND gate 9a and the control input INH of the shift registers 7.1 and 7.2. The mains voltage U _{PG is present} at input 8b. The output 8c is connected to the input SH / LD of the two shift registers 7.1 and 7.2. The control line 5b is connected to the input CL of the shift register 7.1 and 7.2. The serial output DA of the second shift register 7.2 is connected to the serial input DE of the first shift register 7.1, so that a cascade connection results.

The switching device 2.1 is in the closed state, so that a sinusoidal AC voltage is present at the input of the coupling element 3.1 as a low-voltage signal V 1. The coupling elements 3.1 to 3.16 are designed in a manner known per se as a network of resistors, capacitors, diodes and a Z-diode such that a one-way rectified square wave voltage U 1 appears at the output of the coupling element 3.1 with a level with respect to the zero point G of a few volts, eg 5.7 V. The switching device 2.2 is in the open state, so that a DC voltage is present at the input of the coupling element 3.2 as a low-voltage signal V₂ its output appears as DC voltage U₂ with the zero point level G.

The synchronizing device 8 has behind its input 8b a coupling element 8d, which is constructed similarly to the coupling elements 3.1 to 3.16, so that a pulsating square-wave voltage U _R appears at the output of the coupling element 8d, the phase of which coincides with the square-wave voltage U 1 at the input 4.1 of the shift register 7.1 is coordinated. The output of the coupling element 8d is connected to one input of a NAND element 8e, the control line 5a via the input 8a to the other input of the NAND element 8e. The output of the NAND element 8e forms the output 8c of the synchronization device 8. The inputs of the NAND elements 9a, 10a and 8e are advantageously provided with Schmitt trigger stages in order to obtain a well-defined switching behavior.

In the normal operating state of the control device, the control lines 5a and 5b at the output of the microprocessor 1 are at a low potential, so that the optocouplers 9 and 10 are in the dark state, while the control lines 5a and 5b after the NAND elements 9a and 10a due to the Level reversal has a high potential. A state is thus high at the INH input, while a pulsating square-wave voltage U _{SH / LD} appears at the input SH / LD, which is complementary to the square-wave voltage U _R. Each time the square-wave voltage U _{SH / LD changes} from high to low potential, the voltage levels U₁ to U₁liegenden applied to the inputs 4.1 to 4.16 of the shift registers 7.1 and 7.2 are detected as logic status values "0" or "1" and stored in the registers. The phase of the square-wave voltage U _{SH / LD} with respect to the square-wave voltage U 1 is coordinated by means of the coupling element 8 d so that the change in the square-wave voltage U _{SH / LD} takes place from high to low each time the voltage U 1 is already high, so that the state value is Switching device 2.1, which is in the closed state, a value "1" is read in according to a logically high potential. Since the switching device 2.2 is open, the voltage U₂ is detected according to a logic low potential as a state value "0". In this way, the parallel loading of the shift registers 7.1 and 7.2 always takes place at a point in time when a voltage level of a few volts when one of the switching devices is closed and a voltage level of zero volts with respect to the zero point level G at the inputs 4.1 to when the switching device is open 4.16 concerns. The constant data acquisition has the advantage that the current states of the switching devices 2.1 to 2.16 are present at all times in the shift registers 7.1 and 7.2. To read out the status values from the shift registers 7.1 and 7.2, the microprocessor 1 sets the control line 5a to a high potential, which means that a high potential is also present at the SH / LD inputs. The data acquisition of shift registers 7.1 and 7.2 is thus blocked. With each shift pulse subsequently sent by the microprocessor 1 via the control line 5b, the detected state values are shifted by one place in the direction of the output DA of the shift registers 7.1 and 7.2. One at the DA output second shift register 7.2 appearing value is thus transmitted via the connecting line to the serial input DE of the first shift register 7.1, a value appearing at the output DA of the first shift register 7.1 is transmitted to the microprocessor 1 via the serial data line 6 and the optocoupler 11. At the input of the microprocessor 1, the state value of the switching device 2.1 arrives after the first shift command, after the second shift command the state value of the switching device 2.2, etc., until after the 16th shift command, the state value of the switching device 2.16 arrives. The test cycle to be carried out by the microprocessor 1 to detect the state of the switching devices 2.1 to 2.16 thus consists of the control commands required to block the data acquisition and to read out the shift registers 7.1 and 7.2.

The circuit structure with the shift register 7.1 and 7.2 offers the advantage that commercially available standard elements are used, with which the control device can be easily expanded to a cascaded circuit for any number of switching devices. The use of the synchronizing device 8 allows a simple design of the coupling elements 3.1 to 3.16, which only have to supply a one-way rectified square wave voltage at their output. The memory requirement for programming the test cycle is low, since the test cycle mainly consists of shift commands.

The synchronization device 8 is a hardware means to ensure that the information contained in the signal voltages U₁ to U₁₆ about the state of the switching devices 2.1 to 2.16 is correctly detected. This information could also be obtained in software by multiple queries within a period of one to two network half-waves and an analysis of the values recorded one after the other, so that a synchronization device 8 would not be required. Such exemplary embodiments are described in the patent application EP 660 043, which was filed in parallel with the European Patent Office, "Control device for actuating switching devices according to a time program", the text of which is an integral part of this application.

FIG. 4 shows a further development of a device for controlling up to n = 8 switching devices 2.1 to 2.8, which is expanded by a test module 12 for detecting input coupling errors or hardware errors of the shift register 7. An input coupling error occurs, for example, when the at the input 4.2 read state value not only from the voltage level at input 4.2, but also from that at another input, e.g. 4.5, the applied voltage level depends. One speaks of a hardware error if the read-in status value of an input always appears as logic "0" (stack at zero) or logic "1" (stack at one) regardless of the voltage level present.

The test module 12 has a serial data input, a clock input and one the state of its outputs 12.1 to 12.8 controlling input, which are connected via lines 13, 14 and 15 to the microprocessor 1. Parallel outputs 12.1 to 12.8 are connected via lines 16.1 to 16.8 to the corresponding inputs 4.1 to 4.8 of the shift register 7. The outputs 12.1 to 12.8 can be switched into a state known to the specialist under the term tristate, in which they are high-resistance and do not influence the state of the lines 16.1 to 16.8 (e.g. U. Tietze and Ch. Schenk, semiconductor circuit technology, 5th edition, Springer Verlag Berlin Heidelberg New York, ISBN 3-540-09848-8). The inputs 4.1 to 4.8 of the shift register 7 are also connected to the outputs of the coupling elements 3.1 to 3.8, only the coupling element 3.1 being drawn for the sake of clarity. Both the test module 12 and the shift register 7 are connected to the zero point line G.

The described device works as follows:

In normal operation, the outputs 12.1 to 12.8 of the test module 12 are in the tristate state and do not influence the voltages U₁ to U₈ at the inputs 4.1 to 4.8. In order to check the reliability of the data acquisition by means of the circuit block 4, the microprocessor 1 carries out a test cycle at certain times. The test cycle consists in the microprocessor 1 sending a test pattern, which consists of eight binary values "0" or "1", to the test module 12 via the serial line 13. After transmission, these values are available as high or low potentials at the outputs 12.1 to 12.8 as soon as the microprocessor 1 sets the outputs 12.1 to 12.8 in the conductive state via the control line 15, so that voltage levels U 1 to U 4 with potential values high or low according to the previously sent test pattern at inputs 4.1 to 4.8 of shift register 7. The microprocessor 1 now sends further commands to the shift register 7 for detecting the voltage levels U 1 to U 4 present at its inputs 4.1 to 4.8 as binary values and for transmission to it, whereupon it compares the reported binary values with the sent test pattern. The microprocessor 1 is programmed to send a number of selected test patterns to the test module 12 and to read them in again via the shift register 7, so that both input coupling errors and hardware errors can be identified. If necessary, the control lines 13, 14 and 15 can be provided with galvanic isolators.

Claims (9)

1. A control apparatus which has a timer and control logic device (1) for the actuation of a plurality of switch devices (2.1; 2.2), wherein the switch devices (2.1; 2.2) control the supply of current to loads (L1; L2) which can be connected in a low-voltage system between a phase (P) and a neutral point (G) in series with the switch devices (2.1; 2.2), and which has a circuit block (4) which is connected on the input side by way of signalling lines (ML1; ML2) arranged in parallel and serving to detect the state of the switch devices (2.1; 2.2) - open or closed - to tappings arranged in the current path between the switch devices (2.1; 2.2) and the associated loads (L1; L2) and on the output side to the control logic device (1), wherein at predetermined moments in time the control logic device (1) detects the voltages (U₁; U₂) at the parallel inputs (4.1; 4.2) of the circuit block (4) and determines the state of the switch devices (2.1; 2.2), characterised in that the signalling lines (ML1; ML2) contain coupling members (3.1; 3.2) for level limiting purposes, that the voltages (U₁; U₂) which are transmitted by way of the coupling members (3.1; 3.2), at the inputs (4.1; 4.2) of the circuit block (4), assume a potential at the level of the neutral point (G) in the open state of one of the switch devices (2.1; 2.2) and in the closed state in accordance with the voltage variation in respect of time of the phase (P) with respect to the neutral point (G) they assume a potential of a fluctuating or uniform configuration and at a level which is different from the neutral point (G), that the circuit block (4) has one or more cascade-connected shift registers (7), wherein the shift registers (7) detect in parallel the voltages (U₁; U₂) applied to the inputs (4.1; 4.2) as binary values '0' or '1' in accordance with a predetermined voltage level, and that the binary values '0' or '1' are transmitted to the control logic device (1) by way of a serial output (DA) of the shift register (7) and a serial data line (6).
2. A control apparatus according to claim 1 characterised in that the circuit block (4) and the control logic device (1) are galvanically separated by means of separating members (9; 10; 11).
3. A control apparatus according to claim 1 or claim 2 characterised in that there is provided a synchronising device (8) which synchronises the detection of the voltage levels (U₁ to U₁₆) at the inputs (4.1 to 4.16) of the shift registers (7) with the system voltage (U_PG).
4. A control apparatus according to claim 1 or claim 2 characterised in that the state of the switch devices (2.1; 2.2) is determined from the state values which are obtained by multiple interrogation during a period of one to two system half-waves.
5. A control apparatus according to one of claims 1 to 4 characterised in that for fault detection in continuous operation of the installation controlled by the control apparatus the control logic device (1) performs a test cycle for detecting the state of the switch devices (2.1; 2.2) at given moments in time.
6. A control apparatus according to one of claims 1 to 5 characterised in that the control logic device (1) is connected to a test component (12) which has a serial data input and a plurality of parallel outputs (12.1 to 12.8), that the parallel outputs (12.1 to 12.8) of the test component (12) are connected to the parallel inputs (4.1 to 4.8) of the shift registers (7) and that the parallel outputs (12.1 to 12.8) are switchable either into a conducting or a high-resistance tristate condition.
7. A control apparatus according to claim 6 characterised in that the test component (12) comprises one or more cascade-connected shift registers.
8. A control apparatus according to claim 6 or claim 7 characterised in that for detecting input coupling faults or hardware faults in the circuit block (4) the control logic device (1) performs a test cycle at predetermined moments in time by a procedure whereby it writes a test pattern comprising binary values into the test component (12) by way of a serial line (13), it puts the test component (12) into the conducting state, it provides for detection and transmission to itself of the voltage levels (U₁ to U₈) at the inputs (4.1 to 4.8) of the shift registers (7), it compares the test pattern which has been signalled back to the despatched test pattern, and it puts the test component (12) into the tristate condition again.
9. A control apparatus according to one of claim 1 to 8 characterised in that the control logic device (1) is a microprocessor.

Images