EP0650257A3 - - Google Patents

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Publication number
EP0650257A3
EP0650257A3 EP95200071A EP95200071A EP0650257A3 EP 0650257 A3 EP0650257 A3 EP 0650257A3 EP 95200071 A EP95200071 A EP 95200071A EP 95200071 A EP95200071 A EP 95200071A EP 0650257 A3 EP0650257 A3 EP 0650257A3
Authority
EP
European Patent Office
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP95200071A
Other versions
EP0650257A2 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/285,721 external-priority patent/US4914322A/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0650257A2 publication Critical patent/EP0650257A2/en
Publication of EP0650257A3 publication Critical patent/EP0650257A3/xx
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
EP95200071A 1988-12-16 1989-12-08 Initialization circuit Ceased EP0650257A2 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US28549688A 1988-12-16 1988-12-16
US28631088A 1988-12-16 1988-12-16
US07/285,721 US4914322A (en) 1988-12-16 1988-12-16 Polarity option control logic for use with a register of a programmable logic array macrocell
US286310 1988-12-16
US285496 1988-12-16
EP19890312801 EP0373831A3 (en) 1988-12-16 1989-12-08 Self latching logic gate
US285721 1994-08-04

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP89312801.7 Division 1989-12-08
EP19890312801 Division EP0373831A3 (en) 1988-12-16 1989-12-08 Self latching logic gate

Publications (2)

Publication Number Publication Date
EP0650257A2 EP0650257A2 (en) 1995-04-26
EP0650257A3 true EP0650257A3 (en) 1995-05-31

Family

ID=27403531

Family Applications (3)

Application Number Title Priority Date Filing Date
EP95200072A Ceased EP0653842A3 (en) 1988-12-16 1989-12-08 Polarity option control logic
EP95200071A Ceased EP0650257A2 (en) 1988-12-16 1989-12-08 Initialization circuit
EP19890312801 Ceased EP0373831A3 (en) 1988-12-16 1989-12-08 Self latching logic gate

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP95200072A Ceased EP0653842A3 (en) 1988-12-16 1989-12-08 Polarity option control logic

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP19890312801 Ceased EP0373831A3 (en) 1988-12-16 1989-12-08 Self latching logic gate

Country Status (2)

Country Link
EP (3) EP0653842A3 (en)
JP (1) JPH02215226A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69123077D1 (en) * 1990-04-30 1996-12-19 Advanced Micro Devices Inc Programmable logic device
US5111086A (en) * 1990-11-19 1992-05-05 Wang Laboratories, Inc. Adjusting delay circuitry
EP0756379B1 (en) * 1995-07-28 2003-09-24 STMicroelectronics S.r.l. Unbalanced latch and fuse circuit including the same
JP3630847B2 (en) * 1996-05-16 2005-03-23 株式会社ルネサステクノロジ Latch circuit
JP3705880B2 (en) * 1996-11-28 2005-10-12 富士通株式会社 Level converter and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157633A (en) * 1981-03-23 1982-09-29 Nec Corp Electric power making detecting circuit
EP0150480A2 (en) * 1984-01-16 1985-08-07 Itt Industries, Inc. Power-on reset pulse generator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4289982A (en) * 1979-06-28 1981-09-15 Motorola, Inc. Apparatus for programming a dynamic EPROM
JPS60227511A (en) * 1984-04-25 1985-11-12 Nec Corp Integrated circuit
US4713792A (en) * 1985-06-06 1987-12-15 Altera Corporation Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits
US4609986A (en) * 1984-06-14 1986-09-02 Altera Corporation Programmable logic array device using EPROM technology
US4661930A (en) * 1984-08-02 1987-04-28 Texas Instruments Incorporated High speed testing of integrated circuit
US4783606A (en) * 1987-04-14 1988-11-08 Erich Goetting Programming circuit for programmable logic array I/O cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157633A (en) * 1981-03-23 1982-09-29 Nec Corp Electric power making detecting circuit
EP0150480A2 (en) * 1984-01-16 1985-08-07 Itt Industries, Inc. Power-on reset pulse generator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 6, no. 259 (E - 149)<1137> 17 December 1982 (1982-12-17) *

Also Published As

Publication number Publication date
EP0373831A2 (en) 1990-06-20
JPH02215226A (en) 1990-08-28
EP0373831A3 (en) 1991-09-04
EP0650257A2 (en) 1995-04-26
EP0653842A2 (en) 1995-05-17
EP0653842A3 (en) 1995-05-31

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