JPS60227511A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a complementary type device and highten the logic gate density as high as a single polarity device, by connecting a power cut-off switch to one of the two sets of inverters of an integrated circuit using a complementary MOS device. CONSTITUTION:When the multi-input logic circuit network 4 and N type MOS transistors (TR) QN9 and QN10 of an integrated circuit are not conducted, an FF circuit 1 holds ''1'' or ''0'' at a low power consumption. When a set signal S and input signals (a) and (b) are ''1'', the circuit network 4 and TRQN9 are conducted and a P type MOSTRQP9 is not conducted and, as a result, the circuit 1 is inverted and sets its output Q to ''0''. On the otherhand, when a reset signal (r) is ''1'', the TRQN10 is conducted and a circuit current is instantaneously made to flow through the conducted P type TR of the circuit 1. By setting the mutual conductance gm of the TRQN10 sufficiently large to the mutual conductance gm of the P type TR and holding the output after the circuit is inverted and the circuit current is cut off at ''0'', the power consumption of this integrated circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an integrated circuit constructed using complementary MOB devices.

(Prior Art) Conventionally, a complementary fiMO8 logic circuit composed of an N-channel MO8 device and a P-channel MO8 device generally has extremely low power consumption in a standby state, and has a μW-class L
It has the advantage that an SI circuit can be realized. In addition, in the complementary MO8 logic circuit, as the operating frequency increases, the circuit current consumed during the transient state increases, but since all the circuits in the LSI circuit do not switch at the highest frequency, other Compared to LSI circuits based on a single channel MO8 process, the overall power consumption is generally an order of magnitude lower.

FIG. 1 is a circuit diagram of an example of a conventional MO8 logic circuit.

In FIG. 1, 1 is a flip-flop circuit composed of two sets of complementary MOS inverters, 2°2', 3,
3' is a multi-input logic network each composed of single-polarity devices. That is, 2 and 3 are each N channel MO
8) Consisting only of transistors, 2/, a/
are each composed of only P-channel MOIL) transistors.

This logic circuit is always configured with N-channel and P-channel devices in pairs. In flip-flop circuit 1, P-channel MO8) transistor Qp+ + Q
pt and N-channel MOS transistor QNI r Q
N2 is a pair, and in a multi-input logic network, 2 and 2
The transistors in ', 3 and 3' are used as pair K1.

A logic circuit constructed in this way has nearly twice as many elements as a circuit constructed using a single-polarity (i.e., single channel) MO8 device; LSI circuits based on this process have the disadvantage that the density of integrated logic gates is nearly half that of LSI circuits made up of only single-polar devices.

FIG. 2 is a circuit diagram of another example of the conventional M'O8q logic circuit.

In FIG. 1, reference numeral 1 denotes a flip-flop circuit 2'' consisting of two sets of complementary MOS inverters.

3” is a unipolar device (in this example, an N-channel MOS
This is a multi-input logic circuit network' composed of transistors QN3 to QN-). And the multi-input network 2':3'' is 7
It is connected between the output terminal of the flip-flop circuit 1 and one end of the reference power supply (ground in this example).

This logic circuit is constructed with a reduced number of elements compared to the logic circuit shown in FIG. 1, increasing the logic gate density and reducing the chip area.

However, in this logic circuit, the mutual conductance (pm>) of the I'viOS device that makes up the multi-input logic network must be set larger than the mutual conductance (11m) of the MOS device that makes up the flip-flop circuit. Although the number of elements is necessarily reduced compared to FIG. 1, there is a drawback that the area density of the mounted elements is not so high.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks, maintain the advantage of low power consumption of complementary MO8 devices, and yet allow logic gate density to be as high as unipolar devices. Its purpose is to provide integrated circuits.

(Structure of the Invention) In the integrated circuit of the present invention, input terminals and output terminals of two sets of complementary MOS inverters are connected to each other, and a power cutoff switch is connected to at least one of the two sets of inverters. A multi-input logic network comprising a plurality of monolithic devices connected between the output terminal of the flip-flop circuit and a reference power supply.

(Example) Next, an example of the present invention will be described using the financial aspect.

FIG. 3 is a circuit diagram of the first embodiment of the present invention.

This first embodiment is an example in which a power cutoff switch is connected to one of two sets of inverters.

P-channel MO8) Transistor Qp+ and N-channel MO
8) A set of complementary MMU S inverters is configured with transistor QNI, and P-channel Most transistor QP
t and N-channel MO8) transistor QN.

Yet another set of complementary mMOs inverters is constructed. The input terminals and output terminals of these two sets of complementary MOS inverters are connected together, and a P-channel MOS transistor Qpo is connected as a power cutoff switch between one end of the power supply (1V) and the P-channel MO8) transistor QP+. A flip-flop circuit 1 is constructed. The multi-input logic network 4 is composed of a single-polarity (N-channel in this example) MOS) transistor QNsr QN4, and is connected to the output terminal of the 7-lip-flop circuit 1 and the reference power supply (ground in this example).
connected between. N channel MO8) transistor Q
N9 + QNIO are transistors for setting and resetting, respectively.

Next, the operation of this embodiment will be explained.

First, the multi-input logic circuit network 4 and M for setting and resetting.
OS) When transistor QN9 + QNto is not conductive, flip-flop circuit 1 becomes 1'' or ''0.
``Output can be maintained with low power consumption.

Next, when the set signal S and the input signals a and b are both "1n," the N-channel multi-input logic network 4 and the N-channel MO8) transistor QN11 become conductive, and the P-channel M,
08 transistor Qps becomes non-conductive, the flip-flop circuit 1 is inverted, and the output Q becomes '0'.

On the other hand, when the reset signal γ is 1'', the N channel M
O8) The transistor QN+o becomes conductive and becomes conductive with the conductive P-channel Δ'+08 transistor of the flip-flop circuit 1, so that the circuit current momentarily increases to 0+'G. Said P
Channel MO8) Transistor transconductance 1m
For N-channel MO8) transistor QNI. gm
If is designed to be sufficiently large, the flip-flop circuit 1 will be reversed, the circuit current will be cut off, and the subsequent output state will also be '0°.
′ is maintained.

In the conventional circuit shown in FIG. 2, there was a limit to the mutual conductance of 1 m for the multi-input logic network 2, but in the circuit of the present invention, the mutual conductance for the N-channel MO8 transistor QNo + logic network 4 was limited to 9 m. Since there are no limitations on design, circuit design can be simplified and implementation efficiency can be improved.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

This second embodiment consists of two sets of complementary MOS inverters (Q
A P channel M is connected between each of p= , QNI) and (Qp2.QN-) and the power supply 'r■ as a power cutoff switch.
O8) Transistor Qp* + Qpl. This is an example of connecting. A single-polarity (N channel in this example) multi-input logic circuit network 4 is connected between the two output terminals of the 7-lip-flop circuit 1 and a reference power source (ground), respectively.

The operation and effects are similar to the first embodiment.

Incidentally, in the above two embodiments, the multi-input logic circuit was constructed of N-channel MO8) transistors, but P-channel MO8)
) It is needless to explain that the same configuration can be achieved using transistors.

(Effects of the Invention) As described above in detail, according to the present invention, an integrated circuit with low power consumption and high logic gate density can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an example of a conventional MO8 type logic circuit;
This figure is a circuit diagram of another example of a conventional MO8 type logic circuit, FIG. 3 is a circuit diagram of a first embodiment of the present invention, and FIG. 4 is a circuit diagram of a second embodiment of the present invention. 1...Flip-flop circuit, 2, 2', 2"
, 3゜3', 3", 4, 4'...Multi-input logic network, Q, Q...Output, QNI~QN8・
...N channel MO8) resistor, Qp1 to Q
ps...P channel MO8) transistor, QN
O... MO8) transistor for setting. QNIO・・・・・・MO8) transistor for reset,
Qpo + Qp+o... MO8 for switch)
Transistor, a, b, c, d, e, f...input signal, γ...reset signal, S...set signal. Figure 1

Claims (1)

[Claims] A flip-flop circuit comprising two sets of complementary MO8 inverters whose long terminals and output terminals are connected to each other and a power cutoff switch connected to at least one of the two sets of inverters; An integrated circuit comprising: a multi-input logic network comprising a plurality of unipolarity devices connected between an output terminal of the circuit and a reference power supply.