EP0639038B1 - Circuit for converting a stereo signal - Google Patents

Description

The invention relates to a circuit arrangement for converting a center signal and a stereo signal comprising a side signal in each case an output signal for two audio signal channels with a matching arrangement to minimize crosstalk between the output signals.

In such circuit arrangements, the output signals for the audio signal channels generated by dematricing the center signal and the side signal. It contains in the usual stereo systems, the center signal sound information over both sound signal channels, whereas the side signal prefers either audio information via one of the audio channels or for example a difference between the sound information of the two Contains audio signal channels. For dematriculation, which is preferred through additive or Subtractive superimposition of the center signal and the side signal takes place then certain amplitude ratios are adhered to in order to dematriculate a to obtain crosstalk-free division of the sound information into the two sound signal channels. These predetermined amplitude ratios can, for example, by Circuit tolerances or transmission errors may be disturbed, so that there is between the two Audio signal channels to crosstalk.

From DE 41 02 834 A 1 an arrangement for adjusting a stereo decoder is minimal Crosstalk known. In the stereo decoder described there, in which means a bandpass filter is filtered out of the subcarrier of the stereo multiplex signal the pilot tone and so that a local oscillator is phase-synchronized, is used for adjustment to the minimum Crosstalk between the left and right output channels using an electronically adjustable Phase setting device in the pilot tone filter branch automatically sets the phase.

• durch Einspeisen eines Kalibriersignals mit der Frequenz des Pilottons unmittelbar am Eingang des Pilotton-Bandpaßfilters und Abgleich des Phasenfehlers zwischen Eingang und Ausgang des Pilotton-Filterzweiges auf Null oder
• durch Einspeisen eines Stereo-Multiplex-Kalibriersignals am Eingang des Decoders und Abgleich der dabei gemessenen Übersprechdämpfung auf ein Maximum oder
• bei Verwendung eines Pilotton-Bandpaßfilters, dessen Durchlaßkurve bei der Mittenfrequenz ein lokales Minimum und einen Phasenfehler von M*90° (M=0, 1, 2, 3...) zwischen Ein- und Ausgang aufweist, durch Einspeisen eines beliebigen Stereo-Multiplexsignals am Eingang des Decoders und Abgleich der Mittenfrequenz des Bandpaßfilters auf das lokale Minimum.

According to the teaching of the document mentioned, this is done either

• by feeding a calibration signal with the frequency of the pilot tone directly at the input of the pilot tone bandpass filter and adjusting the phase error between the input and output of the pilot tone filter branch to zero or
• by feeding a stereo multiplex calibration signal at the input of the decoder and adjusting the measured crosstalk attenuation to a maximum or
• when using a pilot tone bandpass filter, the transmission curve of which has a local minimum at the center frequency and a phase error of M * 90 ° (M = 0, 1, 2, 3 ...) between input and output, by feeding in any stereo Multiplex signal at the input of the decoder and adjustment of the center frequency of the bandpass filter to the local minimum.

The object of the invention is to design a circuit arrangement of the type mentioned at the beginning, that during their manufacture, commissioning or during their operation, a quick, there is a simple and precise possibility of adjustment by means of which the crosstalk during operation can be effectively eliminated.

This object is achieved in a circuit arrangement for converting a center signal and a stereo signal comprising a side signal in each case an output signal for two audio signal channels with a matching arrangement to minimize crosstalk between the Output signals solved according to the invention by a limiter circuit, the first of the Output signals can be fed and from which this into an at least almost rectangular, amplitude-limited signal of the same frequency can be converted, a mixer circuit for Obtaining a DC signal by multiplicatively combining the amplitude-limited Signal with a second of the output signals, a control circuit for winning a Control signal from the DC signal, an adjustment circuit for influencing the amplitudes the center signal and / or the side signal with the aid of the control signal, a storage device for storing the control signal and a switching device by which in a first Operating state of the circuit arrangement, the control signal of both the storage device for storing and the setting circuit can be fed and in a second operating state the circuit arrangement, the control signal stored in the memory device Setting circuit can be fed.

The adjustment made possible by the circuit arrangement according to the invention is in the carried out first operating state, in which the adjustment arrangement a control loop forms, which can be used to minimize a signal which is formed in this way is that it only occurs when there is crosstalk between the audio signal channels. After adjustment has taken place once, the circuit arrangement according to the invention can then be used in their second operating state for processing, for example, by a broadcaster or a stereo signal received on a recording medium. In this The second operating state is the storage of the control signal in the storage device maintain the recorded alignment state of the circuit arrangement.

In an advantageous method for operating a circuit arrangement according to the invention the center signal and the side signal of the stereo signal are correct in the first operating state match, and the control signal is regulated to a value at which the second output signal disappears. This method is used especially in the stereo systems, which as the center signal the sum and as the side signal the difference of the sound signals of the transmit both audio signal channels; in particular, the second output signal is the assigned to the right audio signal channel. In another method according to the invention for Operating the circuit arrangement according to the invention corresponds to the center signal of the stereo signal in the first operating state half the side signal and also the control signal regulated to a value at which the second output signal disappears. This method is preferably used when the center signal is the sum of the sound signals of the two sound signal channels and the side signal double the sound signal for the right Sound signal channel corresponds. While the first-mentioned method is therefore especially for the European stereo broadcasting as well as the television sound according to Korean standard use the second method can be found, in particular, for the television sound of European television apply. For these different transmission standards of the sound signals can always use a matching arrangement of the same structure.

With the circuit arrangement according to the invention and using the above methods According to the invention, the circuit arrangement can be compared, for example, directly after their manufacture, in the manufacture of a device for stereo sound signal reproduction, in which the circuit arrangement according to the invention is used, or in a first or each time the circuit arrangement according to the invention is started up. The one for the adjustment value of the control signal is then stored in the memory device filed and can be called up during operation. For this purpose, the invention includes Circuitry prefers a conversion circuit that converts into signal paths for that Control signal between the control circuit, the setting circuit and the memory device is inserted and through which the control signal emitted by the control circuit into a form is convertible, in which it can be stored in the storage device, and by which stored control signal can be converted into a form to be supplied to the setting circuit. A particularly simple and precise storage is achieved in that the Control signal can be stored in the memory device in digital form and the Conversion circuit each an arrangement for converting the control signal into this digital Form or from this digital form.

For realizing the above-described variations in the application of the invention The adjustment signal to be stored in digital form can be a method for adjustment for example, in one of the circuit arrangements according to the invention Read memory must be stored. The storage device can also be of the circuit arrangement to convert the stereo signal spatially separated within a control system, For example, a bus system can be arranged in which other control and Adjustment data are stored. Thus, the invention can also be carried out in a simple manner carry out an automatically controlled adjustment, for example, each time it is started up of a device in which the circuit arrangement according to the invention is used. On in this way, for example, aging effects of components and others Eliminate time-variable interferences effectively.

A preferred embodiment of the circuit arrangement according to the invention is distinguished characterized in that the arrangement for converting the control signal into digital form a Comparator stage, which can be supplied with the control signal from the control circuit at a first input is, and comprises a counter stage, the counting direction by an output signal of the comparator stage determinable and their counter reading as a control signal in digital form in the storage device is storable, and that the arrangement for converting the control signal from the digital form includes a digital-to-analog converter stage for converting the actuating signal the digital in the form that can be fed to the setting circuit, in which it continues to be second input of the comparator stage for comparison with that which can be supplied by the control circuit Control signal can be fed.

Such an arrangement for converting the control signal provides a very simple structure on the one hand a very precise control signal and on the other hand it is used both for the output of a control signal in digital form as well as for taking over such an actuating signal from the storage device simple and easy to use. This is preferably done in the storage device Stored control signal of the counter stage for presetting to an appropriate counter reading forwarded.

In a circuit arrangement of the type described above, one is used to adjust the counter stage to be used on the counter reading corresponding to the required value for the control signal Clock signal advantageously derived from the amplitude-limited signal and the Counter stage supplied as a count signal. In this way, a quick adjustment of the alignment arrangement achieved with simple means, especially avoiding a separate one Clock signal generation.

The control circuit preferably includes an integration stage for obtaining the control signal as well as a low pass level. The low-pass level serves to suppress all alternating components of the mixed products of the mixer circuit, since only their DC components are used for the control signal are. However, since a control error remains with a low-pass stage alone, so that crosstalk the integration level is still provided, that cancels this control error. This is a complete elimination of crosstalk guaranteed.

Another embodiment of the circuit arrangement according to the invention is characterized by this from that the trimming arrangement a second limiter circuit which the second output signal can be fed and from which this into an at least almost rectangular, second amplitude-limited signal of the same frequency is deformable, a second mixer circuit to obtain a second DC signal by multiplying the second amplitude-limited signal with the first output signal, a second control circuit to obtain a second actuating signal from the second direct signal, a second Storage device for storing the second control signal and a second switching device comprises, by the in a first operating state of the circuit arrangement second control signal of both the second storage device for storing and the setting circuit can be supplied and in a second operating state of the circuit arrangement the second control signal of the setting circuit stored in the second memory device can be supplied, and that in the setting circuit, the amplitudes of the center signal and / or the side signal in mutually different frequency ranges using the two control signals can be influenced.

This embodiment of the invention is particularly applicable to circuit arrangements for converting a stereo signal, in which the side signal before dematricating a Noise reduction should be subjected. Such noise suppression is special then advantageous if the side signal is modulated to a higher frequency than has the center signal and thus higher noise components. Because of the special, spectral Distribution of this noise can then be beneficial in matching the crosstalk also to be made frequency-dependent. For the different frequency components to be adjusted of the side signal, the two control signals can then be used. In the embodiment of the circuit arrangement according to the invention mentioned above the individual signal processing stages that are in the adjustment arrangement from each other form independent control loops; for example The first and the second limiter circuit can have an identical structure, accordingly the first and second mixer circuits, and so on.

In a preferred method of performing given by the present invention the comparison of the crosstalk with a circuit arrangement according to the invention The type described above with two independent control loops is advantageous in this way Procedure that a test signal is supplied as a stereo signal in the first operating state, at which the center signal an additive and the side signal a subtractive superimposition of a low-frequency first test oscillation and a high-frequency second test oscillation and the second test signal in the side signal to the second test signal in Center signal occurs in phase opposition, and the frequency of the second test oscillation is a non-integer multiple of the frequency of the first test oscillation, and that the first Control signal is regulated to a value in which parts of the first test vibration in the second Output signal disappear, and the second control signal is regulated to a value, where the proportions of the second test oscillation disappear in the first output signal.

Fig. 1

ein Prinzipschaltbild einer erfindungsgemäßen Schaltungsanordnung und zur Erläuterung eines erfindungsgemäßen Verfahrens zum Durchführen eines Abgleichs dieser Schaltungsanordnung,

Fig. 2

einige beispielhafte Signalverläufe der Schaltungsanordnung nach Fig. 1,

Fig. 3

eine detailliertere Ausgestaltung einer Schaltungsanordnung gemäß Fig. 1 und

Fig. 4

ein Ausführungsbeispiel einer für einen frequenzabhängigen Abgleich eingerichteten, erfindungsgemäßen Schaltungsanordnung.

Exemplary embodiments of the circuit arrangement according to the invention are shown in the drawing and are described in more detail below. Show it:

Fig. 1

2 shows a basic circuit diagram of a circuit arrangement according to the invention and to explain a method according to the invention for carrying out an adjustment of this circuit arrangement,

Fig. 2

some exemplary signal profiles of the circuit arrangement according to FIG. 1,

Fig. 3

a more detailed embodiment of a circuit arrangement according to FIGS. 1 and

Fig. 4

an embodiment of a circuit arrangement according to the invention set up for a frequency-dependent adjustment.

In Fig. 1, the reference numeral 1 denotes a stereo demodulator, the one at an input 2 a stereo signal is supplied, which in the usual manner according to one of the known Transmission standards include a center signal and a side signal. From the stereo demodulator 1 becomes the center signal at a first output 3 and the side signal at a second Output 4 delivered. The side signal at the second output 4 contains depending on the applied Transmission standard of the stereo signal preferably either a difference signal between the Sound signals for the two sound signal channels "left" and "right", or only the sound signal for the right audio signal channel.

From the first output 3 of the stereo demodulator 1, the center signal becomes a first input 5 fed to a dematricating circuit 6. Accordingly, the side signal comes from second output 4 of the stereo demodulator 1 to a second input 7 of the dematricating circuit 6, but in the example according to FIG. 1 via a setting circuit 8, the input 9 with the second output 4 of the stereo demodulator 1 and its output 10 with the second Input 7 of the dematricating circuit 6 is connected. This way the side signal the amplitude of the stereo demodulator 1 is set by the setting circuit 8, before it reaches the dematricating circuit 6. This can reduce the amplitude ratio between the center signal supplied to the dematricating circuit 6 and the side signal the value required for crosstalk-free dematriculation.

The dematricating circuit 6 also has two outputs 11, 12 at which the sound signals for the two audio signal channels and assigned output connections 13 or 14 of the circuit arrangement for example for playback. Even though The circuit arrangement should also be readily usable for other transmission standards 1 further described by way of example for processing a stereo signal where the center signal is the sum and the side signal is the difference which represents audio signals for the two audio signal channels. At the first output 11 of the dematricating circuit 6 then becomes the sound signal for the left sound signal channel, on the second Output 12 of the dematricating circuit 6 the sound signal for the right sound signal channel submitted. It should also be mentioned that the setting circuit 8 in a modification of the 1 also between the first output 3 of the stereo demodulator 1 and the first input 5 of the dematricating circuit 6 and then be used accordingly to adjust the amplitude of the center signal can.

The first output 11 of the dematricating circuit 6, which in the present example according to FIG. 1 represents the left audio signal channel, is also with an input 15 of a limiter circuit 16 connected, the output 17 with a first input 18 of a mixer circuit 19 is connected, the second input 20 to the second output 12 of the dematricating circuit 6, which represents the right audio signal channel. Through the limiter circuit 16 that occurs at the first output 11 of the dematricating circuit 6 Output signal - i.e. a tone signal assigned to the left tone signal channel - into a rectangular, amplitude-limited signal transformed, the frequency of the output signal from the first output 11 of the dematricating circuit 6 remains unchanged. The limiter circuit 16 preferably comprises an amplifier for this, which is determined by the output signal on Input 15 is heavily overdriven. In Fig. 2a this rectangular signal is for the simple one Case shown that a vibration constant as a sound signal for the left sound signal channel Frequency, preferably sinusoidal, is used.

If the stereo signal, which is fed to the stereo demodulator 1 at input 2, is such that, when correctly converted, it is only for the left audio signal channel provides a sound signal in the event that the side signal is the difference and the center signal represents the sum of the audio signals for the left and right audio signal channels, which Match the center signal with the side signal of the stereo signal at input 2. Corresponding is in the event that the side signal is twice the sound signal for the right Sound signal channel corresponds to form the stereo signal at input 2 such that the center signal corresponds to half the side signal. In the first case, which is also the embodiment 1 and 2, this is the sound signal for the right in this case Sound signal channel forming second output signal disappear, in the second case disappears the second output signal which then forms the audio signal for the left audio signal channel; correct amplitude setting of side signal and center signal at the outputs 3, 4 of the stereo demodulator 1 provided.

Let us now assume that the side signal is negative compared to the center signal Has amplitude errors, i.e. from the stereo demodulator 1 at the second output 4 is given with too low an amplitude. Without correcting this too small amplitude arises during the de-registration in the de-registration circuit 6 at its second output 12 a vibration, the course of which is plotted over time t in Fig. 2b). This vibration is fed to the second input 20 of the mixer circuit 19 and in it with the rectangular Signal from the first input 18 multiplied. This causes rectification the result of which is shown in Fig. 2c), the resulting DC signal at the output 21 of the mixer circuit 19.

To compare the crosstalk, which is represented by the signals in Fig. 2b) now influence the amplitude of the side signal in the setting circuit 8 until the in the aforementioned amplitude deviation between the center signal and the side signal is balanced. Then the second output signal disappears at the second output 12 of the dematricating circuit 6 and thus also the direct signal at the output 21 of the mixer circuit 19th

To carry out this adjustment, i.e. this comparison includes the embodiment 1, a control circuit 22, the input 23 of the DC signal from the output 21 of the Mixer circuit 19 is supplied. The control circuit 22 wins from the DC signal an actuating signal and outputs this at an output 24. The control circuit 22 includes preferably a low pass level and an integration level; through the integration level essentially a continuously increasing one from the direct component of the direct signal according to FIG. 2c) Control signal generated, whereas the alternating component of the direct signal (its superimposed Ripple) is suppressed by the low-pass stage. The control signal formed in this way is available at the output 24 of the control circuit 22.

1 also shows a switching device 25 with a first input 26 and a second input 27 and an output 28. The switching device 25 is of simplicity for the sake of schematic representation as a mechanical switch, through which the first one can be selected Input 26 in a switch position "1" or the second input 27 in a second Switch position "2" can be connected to output 28. In practice, the Switching device 25 are preferably constructed with electronic switching means. Of the output 28 of the switching device 25 with an adjustment input 29 is also the Setting circuit 8 connected to supply the control signal. The connection of the exit 24 with the first input 26 is also with a control signal output 30, the second Input 27 connected to a control signal input 31. The control signal output 30 can preferably with the input of a memory device for storing the control signal be connected, the output of which in turn can be connected to the control signal input 31. As a result, a value of the control signal can be stored in this storage device, not shown saved and retrieved when needed.

In a first operating state of the circuit arrangement according to FIG. 1, in which the above described stereo signal with in this standard example matching center and Side signals is supplied, the switching device 25 takes its first switch position "1" a. As a result, the control signal of both the storage device, not shown, over the control signal output 30 for storing and the setting circuit 8 via the setting input 29 fed. The circuit arrangement thus forms a control loop for adjustment of crosstalk. The control signal is changed until the second output signal at the second output 12 and thus the DC signal according to FIG. 2c) disappear. The Control signal at the output 24 of the control circuit 22 is then constant and can be constant with this Value can be stored in the storage device.

In a second operating state, the switching device 25 is in its second switch position "2" transferred. The control loop described above is then interrupted. Rather, the storage device now uses the control signal input 31 and the setting input 29 of the setting circuit 8, the stored, constant control signal. In In this second operating state, the stereo signal at the input 2 can take any form assume, always ensuring crosstalk-free operation of the circuit arrangement is. The first operating state of the circuit arrangement thus serves to balance it second operating state use for (intended) conversion, for example stereo signals to be reproduced.

In Fig. 2d) and e) corresponding to Fig. 2b) and c) the case is shown that in the first Operating state of the circuit arrangement for the side signal a positive amplitude deviation compared to the center signal. That at the second output 12 of the dematricating circuit 6 resulting in FIG. 2d) is then compared to the signal in FIG. 2b) represented case negative; there is a negative DC signal at the output 21 of the mixer circuit 19. An actuating signal is formed from this, which via the setting circuit 8 a reduction in the amplitude of the side signal and thus an adjustment of the crosstalk causes.

3 shows a further exemplary embodiment of the circuit arrangement according to the invention with a conversion circuit 32, which into the signal paths for the control signal between the Control circuit 22, the setting circuit 8 and the storage device (not shown) is inserted. Otherwise, the circuit elements already described for FIG. 1 are again provided with the same reference numerals.

The conversion circuit 32 in particular enables the actuating signal in the memory device can be saved in digital form. For this purpose, the conversion circuit 32 comprises an arrangement for converting the control signal from the output 24 of the control circuit 22 in the digital form. In the exemplary embodiment according to FIG. 3, this arrangement comprises a comparator stage 33, whose first, non-inverting input forms the control signal output 30 and whose second, inverting input 34 is connected to the control signal input 31. On Output 35 of the comparator stage 33 has a counting direction input 36 of a counter stage 37 connected, the counting direction of the output signal of the comparator 33 Output 35 can be determined. The count of the counter 37 is at an output 38 of the Counter stage 37 as a control signal in digital form. As such, it can have a digital signal output 39 of the storage device, not shown, and stored there become.

During the arrangement for converting the control signal into digital form the comparator stage 33 and the counter stage 37 includes the arrangement for converting the control signal from this digital form a digital-to-analog converter stage 40, whose digital input 41 connected to the output 38 of the counter 37 and the digital signal output 39 and whose analog output 42 with the control signal input 31 and the second inverting input 34 of the comparator stage 33 is linked. The digital-to-analog converter stage 40 sets this Control signal from the digital form in which it can also be stored in the storage device is into the form which can be supplied to the setting circuit 8 via its setting input 29. By connecting the analog output 42 to the second inverting input 34 the comparator stage 33 is supplied with a reference signal for the latter, with which the control signal can be compared from the output 24 of the control circuit 22. Depending on the outcome of this In comparison, the control stage 37 is switched in the up or down count direction. By The count becomes a counting pulse of a clock signal that can be supplied via a counting input 43 the counting stage 37 corresponding to the counting direction specified by the comparator stage 33 changed until it corresponds to the digital form of the control signal at output 24. This The counter reading is adjusted in the first operating state in which the switching device 25 is in the switch position "1". Accordingly, the control loop then available of FIG. 3 be unchanged from that of FIG. 1 and thus one by Processes in the conversion circuit 32 unaffected regulation of crosstalk signals, i.e. an unaffected comparison of this crosstalk take place. The conversion circuit 32 only settles to the final value of the control signal and feeds it to the storage device.

The clock signal is the counter input 43 of the counter 37 via a switch 44 from the output 17 supplied to the limiter circuit 16 and thus from the amplitude-limited signal derived. For the adjustment, the switch 44 is located in the one labeled "1" Switch position. Of course, the one in Fig. 3 can be simpler than mechanical Switch 44 shown switch preferably also carried out with electronic components become.

In the second operating state of the circuit arrangement according to the invention and its exemplary embodiment 3, the switching device 25 and the switch 44 in their Switch positions "2" transferred. This takes place after the adjustment has been carried out and for an intended use Processing a stereo signal to be reproduced, for example. The counting entrance 43 then no more counting pulses are supplied, so that the count of the counter stage 37 remains unchanged and thus a constant as a control signal from the analog output 42 Value for the control signal is given. This passes through the switching device 25 to the setting circuit 8; the control loop is interrupted, as described in FIG. 1.

For example, to avoid repeating the adjustment process every time Commissioning of the circuit arrangement for converting the stereo signal can be the setting the counter 37 to the control signal corresponding to a correct adjustment The counter reading also takes place in that the counter 37 at a preset input 45 the correct control signal is supplied in digital form from the storage device. Thereby when the circuit arrangement is put into operation again, the counter stage 37 opens immediately set a correct counter reading, and the circuit arrangement can directly from the start up again in their second operating state. This is particularly so advantageous when connecting the circuit arrangement according to the invention - if appropriate together with other stages for signal processing - to a bus system Control of the operational processes, via which the correct control signal in digital form Form can be provided from the storage device.

4 shows a further exemplary embodiment of the circuit arrangement according to the invention, which has two control loops for preferably frequency-selective adjustment of crosstalk between the two audio signal channels and in the rest with parts of the elements described above match elements again matching reference numerals are provided.

4 comprises a second limiter circuit 46, the input of which 47 with the second output 12 of the dematricating circuit 6 for the second output signal connected is. This second output signal is from the second limiter circuit 46 into an at least almost rectangular, second amplitude-limited signal of the same type Frequency deformable, which can be output at an output 48 of the second limiter circuit 46 is.

4 further comprises a second mixer circuit 49, the first input 50 is connected to the output 48 of the second limiter circuit 46. A second input 51 of the second mixer circuit 49 is connected to the first output 11 Dematricator 6 connected. In this way, the second mixer circuit 49 is in the Able to output a second DC signal at its output 52, which by multiplicative Linking the second amplitude limited signal from the output 48 of the second limiter circuit 46 with the first output signal from the first output 11 of the dematricating circuit 6 can be won. The second DC signal from the output 52 of the second mixer circuit 49 is a second control circuit 53 connected to its output 52 Input 54 can be fed. The second control circuit 53 also has an output 55 on which a signal which can be obtained in the second control circuit 53 from the second direct signal, second control signal can be issued.

In the adjustment arrangement according to the exemplary embodiment according to FIG. 4 there is also one second conversion circuit 56 is provided which corresponds to the first conversion circuit 32 is constructed and thus a second comparator stage 57, a second counter stage 58 and a second digital-to-analog converter stage 59. The second comparator stage 57 and the second counter 58 form a second arrangement for converting the second control signal in a digital, in a second storage device, not shown storable form. For this there is a first, non-inverting input of the second comparator stage 57, which forms a second control signal output 60, with the output 55 of the second Control circuit 53 connected. An output 61 of the second comparator stage 57 leads to one Counting direction input 62 of the second counter stage 58, of which an output 63 at which the counter reading the second counter stage 58 can be output as a second actuating signal in digital form with a digital input 64 of the second digital-to-analog converter stage 59 is connected. Moreover is the output 63 of the second counter stage 58 with a second digital signal output 65 connected via which the second control signal in digital form of the second storage device is feedable. An analog output 66 of the second digital-to-analog converter stage 59 is on the one hand connected to a second, inverting input 67 of the second comparator stage 57, around the second control signal after conversion into the analog form as a reference signal to provide the second comparator stage 57. On the other hand is the analog output 66 of the second digital / analog converter stage 59 with a second actuating signal input 68 connected.

Corresponding to the first counter stage 37, the second counter stage 58 has a preset input 69, via which the second counter stage 58 can be set to a predeterminable counter reading. In addition, a counting input 70 is provided for supplying counting pulses to the second Counting stage 58. In the arrangement according to FIG. 4, the counting inputs 43, 70 are both counting stages 37, 58 connected via the switch 44 to the output 48 of the second limiter circuit 46, in order to derive the clock signal from the second amplitude-limited signal which can be tapped there.

The second control signal output 60 is in FIG. 4 with a first input 71 of a second switching device 72 connected, the second input 73 to the second actuating signal input 68 is performed. An output 74 of the second switching device 72 is connected to a second one Setting input 292 connected to a setting circuit 80, the first setting input 291 is connected to the output 28 of the first switching device 25 and which is the location of the Adjustment circuit 8 takes in the embodiments of FIGS. 1 and 3. Preferably is the setting circuit 80 designed such that the first and the second control signal at the setting inputs 291, 292 the side signal from the second output 4 of the stereo demodulator 1 can be influenced in amplitude in different parts of its frequency spectrum is. For example, within the setting circuit 80 via the first setting input 291 a depth adjuster, but a height adjuster via the second setting input 292 be operated. Other spectral setting options can also be implemented. In any case, these settings are made by two independent control loops performed.

A bus circuit 75 is provided in the circuit arrangement according to FIG Data line 76 data and commands can be fed or the data via this data line 76 and can issue orders. Via this bus circuit 75 and the data line 76, which with the Presetting inputs 45, 69 and the digital signal outputs 39, 65 are connected the illustrated alignment arrangement with the storage devices for storing the Control signals must be connected. In addition, can not be connected by the Bus circuit 75 to the switching devices 25, 72 and to the switch 44, through which these can be switched according to the first or second operating state.

In a method for operating the circuit arrangement according to the exemplary embodiment 4 is the stereo demodulator 1 in the first operating state as the input 2 Stereo signal fed a test signal in which the center signal is an additive and the side signal a subtractive superposition of a low-frequency first test vibration and one high-frequency second test vibration. In particular, the second test vibration occurs in the side signal and in the middle signal in opposite phase, the first test oscillation in contrast in Center signal and in phase in the side signal. The frequencies of the test vibrations are selected in accordance with the spectral setting options of the setting circuit 80 and should be non-integer multiples of each other. For example, the first test vibration a frequency of 300 Hz and the second test oscillation a frequency of approximately 3.1 kHz.

With correct amplitude setting of the center signal and the side signal at the outputs 3 or 4 of the stereo demodulator is created during the dematrification in the dematricating circuit 6 at its first output 11 a first output signal for the left audio signal channel, which only has parts of the first test vibration (e.g. 300 Hz), whereas the second output signal at the second output 12 for the right audio signal channel only Contains components of the second test oscillation (e.g. 3.1 kHz). However, is the amplitude ratio between the center signal and the side signal not set correctly what can also occur due to an incorrect setting on the setting circuit 80, the first contains Output signal at the first output 11 due to crosstalk residues of the second test oscillation (e.g. 3.1 kHz), whereas at the second output 12 in the second output signal emitted there Remains of the first test vibration (e.g. 300 Hz) can be found. At exit 17 the first limiter circuit 16 is then a first amplitude-limited, at least almost rectangular signal with the frequency of the first test oscillation (e.g. 300 Hz) emitted, whereas the second limiter circuit 46 has a second one at its output 48 amplitude-limited, at least almost rectangular signal with the frequency of second test vibration (e.g. 3.1 kHz).

From the outputs 17 and 48 of the first and second limiter circuits 16 and 46 on the one hand and by the crosstalk at the outputs 11 and 12 of the dematricating circuit 6 remaining portions of the test vibrations of the same frequency are identified by Mixing in the mixer circuits 19 and 49 at their outputs 21 and 52 a first or second DC signal with DC components generated. It thus arises from the first Test vibration generated, rectangular signal at the output 17 and through Crosstalk at the output 12 remains of the first test oscillation in the first Mixer circuit 19 a DC component of the DC signal output at its output 21. Accordingly, the DC component results from the higher-frequency, rectangular signal at output 48 and the remnants of the second test oscillation at first output 11. All remaining signal components fed to the mixer circuits 19 and 49 lead through the mixing to alternating components in the DC signals at the outputs 21 and 52, since the Test vibration frequencies form a non-integer ratio. These alternating shares are screened out in the following control circuits 22 and 53, respectively. So that will via the first switching device 25 to the first setting input 291 of the setting circuit 80 a setting signal is supplied, which is exclusively from the crosstalk of the first test signal depends on the second output 12 of the dematricating circuit 6 and this by adjusting the amplitude of the side signal in the frequency range of the first test oscillation Adjusted zero. Accordingly, crosstalk becomes via the second switching device 72 the second test oscillation to the first output 11 of the dematricating circuit 6 Zero regulating, second control signal is supplied, as this is via the second setting input 292 only the frequency range of the second test oscillation regardless of the first setting input 291 influenced.

However, even if the amplitude of the first is influenced, possibly slightly Test vibration by the second control signal at the second setting input 292 and vice versa the second test oscillation by the first control signal at the first setting input 291 occurs, the simultaneous effectiveness of the two control loops results in a complete Adjustment of crosstalk, i.e. a correct adjustment of the circuit arrangement. On time-consuming, iterative adjustment procedure alternating with a multiple Adjustment by the first and the second control signal is therefore not necessary. In the embodiment 4 is the clock signal for the counter inputs 43 and 70 of the counter stages 37 and 58 derived from the second test oscillation, since this is due to its higher frequency enables faster setting of the counter stages 37, 58. The matching process in this The first operating state is preferably controlled by the bus circuit 75. After that The switching devices 25, 72 and the switch 44 are adjusted to their switch positions "2" transferred, whereupon the setting circuit 80 with constant values for the first and the second control signal is operated.

Claims (11)

1. A circuit arrangement for converting a stereo signal comprising a mid-plane signal and a side signal into an output signal for each of two audio signal channels, which arrangement comprises an adjustment circuit for minimizing crosstalk between the output signals (at 11, 12),
   characterized by

   a limiter circuit (16) adapted to receive a first one of the output signals (from 11) and to transform this into an at least substantially rectangular amplitude-limited signal of the same frequency,

   a mixer circuit (19) for deriving a rectified signal by multiplying the amplitude-limited signal by a second one of the output signals (at 12),

   a control circuit (22) for deriving a correction signal from the rectified signal,

   an adjustment circuit (8) for influencing the amplitude of the mid-plane signal and/or the side signal by means of the correction signal (from 24),

   a storage device for storing the correction signal (from 24), and

   a switching device (25) by means of which in a first mode of the circuit arrangement the correction signal (from 24) can be applied both to the storage device in order to be stored and to the adjustment circuit (8), and by means of which in a second mode of the circuit arrangement the correction signal stored in the storage device can be applied to the adjustment circuit (8).
2. A circuit arrangement as claimed in Claim 1,
   characterized by a conversion circuit (32) arranged in signal paths for the correction signal between the control circuit (22), the adjustment circuit (8) and the storage device, and enabling the correction signal supplied by the control circuit (22) to be converted into a form in which it can be stored in the storage device, and enabling the stored correction signal to be converted into a form required for application to the adjustment circuit (8).
3. A circuit arrangement as claimed in Claim 2,
   characterized in that the correction signal can be stored in the storage device in digital form and the conversion circuit (32) comprises a device for converting the correction signal into this digital form and one for re-converting it from this digital form.
4. A circuit arrangement as claimed in Claim 3,
   characterized in that the device for converting the correction signal into digital form includes

   a comparator stage (33) for receiving at a first input (30) the correction signal from the control circuit (22), and

   a counter stage (37), whose counting direction can be defined by an output signal (at 35) of the comparator stage (33) and whose count (from 38) can be stored in digital form in the storage device as the correction signal,

   and in that the device for re-converting the correction signal from the digital form includes a digital-to-analog converter stage (40) for converting the correction signal from the digital form into a form in which it can be applied to the adjustment circuit (8) and in which it can also be applied to a second input (34) of the comparator stage (33) for comparison with the correction signal (from 24) which can be applied by the control circuit (22).
5. A circuit arrangement as claimed in Claim 4,
   characterized in that the correction signal stored in the storage device can be applied to the counter stage (37) for presetting (at 45) to a corresponding count.
6. A circuit arrangement as claimed in Claim 4 or 5,
   characterized in that a clock signal derived from the amplitude-limited signal (at 17) can be applied to the counter stage (37) as a counting signal (at 43).
7. A circuit arrangement as claimed in any one of the preceding Claims,
   characterized in that the control circuit (22) includes an integrator stage and a low-pass stage.
8. A circuit arrangement as claimed in any one of the preceding Claims,
   characterized in that the adjustment circuit includes

   a second limiter circuit (46) adapted to receive the second output signal (from 12) and to transform this into an at least substantially rectangular second amplitude-limited signal of the same frequency (at 48),

   a second mixer circuit (49) for deriving a second rectified signal (at 52) by multiplying the second amplitude-limited signal by the first output signal (from 11),

   a second control circuit (53) for deriving a second correction signal (at 55) from the second rectified signal (at 52),

   a second storage device for storing the second correction signal (at 55), as well as

   a second switching device (72) by means of which in a first mode of the circuit arrangement the second correction signal (from 55) can be applied both to the second storage device in order to be stored and to the adjustment circuit (80; Fig. 4), and by means of which in a second mode of the circuit arrangement the second correction signal stored in the second storage device can be applied to the adjustment circuit (80), and

   in that in the adjustment circuit (80) the amplitude of the mid-plane signal (at 3) and/or the side signal (at 4) can be influenced in mutually different frequency ranges by means of the two correction signals (at 291, 292).
9. A method of operating a circuit arrangement for converting a stereo signal comprising a mid-plane signal and a side signal into an output signal for each of two audio signal channels,
   characterized in that in an adjustment circuit for minimizing crosstalk between the output signals (at 11, 12)

   a first one of the output signals (from 11) is applied to a limiter circuit (16) and is transformed by this circuit into an at least substantially rectangular amplitude-limited signal of the same frequency,

   in a mixer circuit (19) a rectified signal is derived by multiplying the amplitude-limited signal by a second one of the output signals (at 12),

   a correction signal is derived from the rectified signal in a control circuit (22),

   in an adjustment circuit (8) the amplitudes of the mid-plane signal and/or the side signal are influenced by means of the correction signal (from 24),

   the correction signal (from 24) is stored in a storage device,

   by means of a switching device (25) in a first mode of the circuit arrangement the correction signal (from 24) is applied both to the storage device in order to be stored and to the adjustment circuit (8), and in a second mode of the circuit arrangement the correction signal stored in the storage device is applied to the adjustment circuit (8), and in that

   in the first mode the mid-plane signal (at 3) and the side signal (at 4) of the stereo signal correspond and the correction signal (at 24) is adjusted to a value at which the second output signal (at 12) disappears.
10. A method of operating a circuit arrangement for converting a stereo signal comprising a mid-plane signal and a side signal into an output signal for each of two audio signal channels,
    characterized in that in an adjustment circuit for minimizing crosstalk between the output signals (at 11, 12)

    a first one of the output signals (from 11) is applied to a limiter circuit (16) and is transformed by this limiter circuit into an at least substantially rectangular amplitude-limited signal of the same frequency,

    in a mixer circuit (19) a rectified signal is derived by multiplying the amplitude-limited signal by a second one of the output signals (at 12),

    a correction signal is derived from the rectified signal in a control circuit (22),

    in an adjustment circuit (8) the amplitudes of the mid-plane signal and/or the side signal are influenced by means of the correction signal (from 24),

    the correction signal (from 24) is stored in a storage device,

    by means of a switching device (25) in a first mode of the circuit arrangement the correction signal (from 24) is applied both to the storage device in order to be stored and to the adjustment circuit (8), and in a second mode of the circuit arrangement the correction signal stored in the storage device is applied to the adjustment circuit (8), and in that

    in the first mode the mid-plane signal (at 3) of the stereo signal corresponds to half the side signal (at 4) and the correction signal (at 24) is adjusted to a value at which the second output signal (at 12) disappears.
11. A method as claimed in Claim 9 or 10, of operating a circuit arrangement for converting a stereo signal comprising a mid-plane signal and a side signal into an output signal for each of two audio signal channels,
    characterized in that in the adjustment circuit

    the second output signals (from 12) is applied to a second limiter circuit (46) and is transformed by this limiter circuit into an at least substantially rectangular second amplitude-limited signal of the same frequency (at 48),

    in a second mixer circuit (49) a second rectified signal is derived by multiplying the second amplitude-limited signal by the first output signal (at 11),

    a second correction signal (at 55) is derived from the second rectified signal (at 52) in a second control circuit (53),

    the second correction signal (from 24) is stored in a second storage device,

    by means of a second switching device (72) in a first mode of the circuit arrangement the second correction signal (from 55) is applied both to the second storage device in order to be stored and to the adjustment circuit (80; Fig. 4), and in a second mode of the circuit arrangement the second correction signal stored in the storage device is applied to the adjustment circuit (80),

    in the adjustment circuit (80) the amplitudes of the mid-plane signal (at 3) and/or the side signal (at 4) are influenced in mutually different frequency ranges by means of the two correction signals (at 291, 292),

    and in that a test signal is applied as stereo signal in the first mode, in which test signal the mid-plane signal (at 3) is formed by additive mixing and the side signal (at 4) by subtractive mixing of a low-frequency first test wave and a high-frequency second test wave, and the second test wave appears in the side signal (at 4) in phase opposition to the second test wave in the mid-plane signal (at 3), the frequency of the second test wave being a non-integral multiple of the frequency of the first test wave, and in that the first correction signal (at 291) is adjusted to a value at which components of the first test wave in the second output signal (at 12) disappear, and the second correction signal (at 292) is adjusted to a value at which components of the second test wave in the first output signal (at 11) disappear.

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