EP0627124A1 - Fet chip with heat-extracting bridge - Google Patents

Fet chip with heat-extracting bridge

Info

Publication number
EP0627124A1
EP0627124A1 EP94905947A EP94905947A EP0627124A1 EP 0627124 A1 EP0627124 A1 EP 0627124A1 EP 94905947 A EP94905947 A EP 94905947A EP 94905947 A EP94905947 A EP 94905947A EP 0627124 A1 EP0627124 A1 EP 0627124A1
Authority
EP
European Patent Office
Prior art keywords
bridge
chip
semiconductor chip
source
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP94905947A
Other languages
German (de)
French (fr)
Inventor
John J. Wooldridge
Allen F. Podell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0627124A1 publication Critical patent/EP0627124A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention is directed to a semiconductor having field effect transistors thereon with a bridge joining the sources of adjacent transistors being substantial with the bridge mounted against a heat- extracting surface so that heat from the transistor is extracted at the source.
  • Coplanar field effect transistors (FET) and particularly gallium arsenide semiconductor FETs are conventionally equipped with a plated air bridge which joins the sources of adjacent FETs.
  • the semiconductor chip is mounted on a support base, and heat is extracted from the FET junctions down through the semiconductor chip and the support base.
  • the semiconductor chip material is a poor heat conductor and, as a consequence, the transistors are heat-limited.
  • the air bridges from source to source are not structurally sufficient to remove significant heat and are used only to ground the sources. With the poor heat conductivity of the semicon ⁇ ductor chip material, especially gallium arsenide, the chip material is sometimes ground down, thinner than possible with slicing, in order to reduce the thermal path.
  • FIG. 1 is an isometric view of a semiconductor chip having a coplanar FET thereon mounted face down on a support base with the heat-extracting bridge of this invention engaged therebetween.
  • FIG. 2 is an enlarged section taken generally along line 2-2 of FIG. 1.
  • FIG. 3 is an view of the chip, as seen generally from the line 3-3 of FIG. 1, removed from the substrate and turned over.
  • FIGS. 1, 2 and 3 show a semiconductor chip 10.
  • the semiconductor chip material is of gallium arsenide, although the heat-extracting structure of this invention is also applicable to other semiconductor materials.
  • the active face of the semiconductor is downwardly directed.
  • the semiconductor chip is upwardly directed, having been turned over as compared to the structure shown in FIGS. 1 and 2.
  • the underside of the semiconductor chip 10, as seen in FIGS. 1 and 2 is the active side.
  • three FET semiconductor devices are shown with three drain connec ⁇ tions 12, 14 and 16. These drain connections are positioned over implanted areas of the semiconductor chip.
  • the semiconductor chip 10 is conventionally about 25 mils thick (0.025 inch), and the active doped areas are close to the lower surface.
  • the drain connections extend toward the edge of the chip 10 at which are located three corresponding pads 18, 20 and 22, respectively. These pads are for connection to external circuitry, as is described below.
  • a pair of gate connections is positioned one on each side of each drain connection.
  • Gate connections 24 and 26 are positioned adjacent drain connection 12; gate connections 28 and 30 are positioned adjacent drain connection 14; and gate connections 32 and 34 are positioned adjacent drain connection 16.
  • these drain connections are carried on the under surface of the semiconductor chip 10. They terminate in pads like the pads 18-22, but in this case, the pads are beyond the broken-away portion of the chip 10, as seen in FIG. 3.
  • Bridge 36 is metallic and may be made of any convenient platable or depositable metal. It has two principal functions. The first is to electrically connect the sources of the several field effect transis ⁇ tors. The second is to carry away heat from the sources. Accordingly, the bridge is preferably about 3 mils thick to prevent the electric field at the FET from penetrating into the mounting substrate material. Silver-plated layers to three mils are suitable. On the other hand, multiple plated layers such as titanium, tungsten, copper and lead-tin are suitable, as is a plating series of titanium, gold, and silver with PbSn or Pbln solder.
  • the bridge 36 has openings 38, 40 and 42 where the bridge passes over the gates and drains to prevent short circuit thereof.
  • the bridge 38 has a flat top 44 by which the chip and bridge are supported from base 46.
  • the base may be any convenient preferably dielectric support, such as ceramic.
  • the dielectric support may be in the ceramic class, such as alumina, beryllia, aluminum nitride or silicon carbide.
  • the substrate may be a thermally conducting organic dielect ⁇ ric material.
  • the top surface of the substrate carries printed wiring which connects to ' -the pads and bridge on the semiconductor chip.
  • printed wiring lines 48, 50 and 52 may carry on the near end thereof (see FIG. 1) underneath the semiconductor chip 10 pads which are respectively in contact with the pads 18, 20 and 22 so that drain connections are made thereto.
  • pads on the gate connection lines may contact pads on the base 46 to carry printed wiring connections to the gates out on the substrate where connections can be made.
  • the height of the bridge above the semiconductor chip and the height of the pads above the semiconductor chip, as seen in FIG. 3, are the same height so that all make contact with pads on the top of the base 46, as seen in FIG. 1. In this way, electrical connections and heat extraction connections are made simultaneously.
  • the chip does not have to be thinned to extract the heat because the heat is extracted from the face at which it is generated.
  • larger chip wafers in the conventional 25 mil thickness can be handled.
  • Heat extraction from the bridge 36 is easily achieved because the substrate 46 can be chosen to have high thermal conductivity, and can be configured to be close to a heat extraction point. By this construction, a higher power integrated circuit chip FET amplifier is achieved by more efficient geometry for the transfer of heat to a heat sink.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention se rapporte à une puce de semiconducteur dans laquelle sont incorporés des transistors à effet de champ et qui comprend un pont de source essentiellement en métal reliant les sources de transistors à effet de champ adjacentes. Le pont de source est monté contre un support d'extraction de chaleur, qui sert à la fois à soutenir les transistors à effet de champ et à les refroidir.The invention relates to a semiconductor chip in which field effect transistors are incorporated and which comprises a source bridge essentially of metal connecting the sources of adjacent field effect transistors. The source bridge is mounted against a heat extraction support, which serves both to support the field effect transistors and to cool them.

Description

FET CHIP WITH HEAT-EXTRACTING BRIDGE
FIELD OF THE INVENTION This invention is directed to a semiconductor having field effect transistors thereon with a bridge joining the sources of adjacent transistors being substantial with the bridge mounted against a heat- extracting surface so that heat from the transistor is extracted at the source.
BACKGROUND OF THE INVENTION Coplanar field effect transistors (FET) and particularly gallium arsenide semiconductor FETs are conventionally equipped with a plated air bridge which joins the sources of adjacent FETs. The semiconductor chip is mounted on a support base, and heat is extracted from the FET junctions down through the semiconductor chip and the support base. The semiconductor chip material is a poor heat conductor and, as a consequence, the transistors are heat-limited. The air bridges from source to source are not structurally sufficient to remove significant heat and are used only to ground the sources. With the poor heat conductivity of the semicon¬ ductor chip material, especially gallium arsenide, the chip material is sometimes ground down, thinner than possible with slicing, in order to reduce the thermal path. However, such thin chips are more subject to cracking from external forces. Turning the chip over with the coplanar FET structures toward the supporting substrate is known and is described in an IEEE paper "A Flip-Chip Gallium Arsenide FET with Gate and Drain Via Connections," by R. L. Camisa, etal, IEEE Electron Device Letters, Volume EDL-5, No. 4, April 1984. However, the structure in that paper does not lend itself to improved removal of heat to facilitate high power FET devices, particularly fabricated with gallium arsenide.
SUMMARY OF THE INVENTION
In order to aid in the understanding of this invention, it can be stated in essentially summary form that it is directed to a FET chip with a heat-extracting bridge with the bridge being made of metal to provide electrical connections and heat extraction. The bridge is mounted against the substrate, which provides physical support and thermal extraction.
It is thus a purpose and advantage of this invention to provide a FET chip which has a substantial heat-extracting bridge mounted from source to source with a heat-extracting device mounted against the bridge to extract heat directly from the surface of the chip at its transistor source.
It is another purpose and advantage of this invention to provide a high-power FET gallium arsenide chip which has heat extracted from the transistors by means of a bridge joining the transistor sources with the bridge also acting as a heat-extracting path.
Other purposes and advantages of this invention will become apparent from a study of the following portion of this specification, the claims and the attached drawings wherein:
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an isometric view of a semiconductor chip having a coplanar FET thereon mounted face down on a support base with the heat-extracting bridge of this invention engaged therebetween. FIG. 2 is an enlarged section taken generally along line 2-2 of FIG. 1.
FIG. 3 is an view of the chip, as seen generally from the line 3-3 of FIG. 1, removed from the substrate and turned over.
DESCRIPTION OF THE PREFERRED EMBODIMENT FIGS. 1, 2 and 3 show a semiconductor chip 10. With respect to the present preferred embodiment, the semiconductor chip material is of gallium arsenide, although the heat-extracting structure of this invention is also applicable to other semiconductor materials. In FIGS. 1 and 2, the active face of the semiconductor is downwardly directed. In FIG. 3, the semiconductor chip is upwardly directed, having been turned over as compared to the structure shown in FIGS. 1 and 2. The underside of the semiconductor chip 10, as seen in FIGS. 1 and 2, is the active side. In the example given, three FET semiconductor devices are shown with three drain connec¬ tions 12, 14 and 16. These drain connections are positioned over implanted areas of the semiconductor chip. The semiconductor chip 10 is conventionally about 25 mils thick (0.025 inch), and the active doped areas are close to the lower surface. As is seen in FIG. 3, the drain connections extend toward the edge of the chip 10 at which are located three corresponding pads 18, 20 and 22, respectively. These pads are for connection to external circuitry, as is described below. A pair of gate connections is positioned one on each side of each drain connection. Gate connections 24 and 26 are positioned adjacent drain connection 12; gate connections 28 and 30 are positioned adjacent drain connection 14; and gate connections 32 and 34 are positioned adjacent drain connection 16. As seen in FIG. 3, these drain connections are carried on the under surface of the semiconductor chip 10. They terminate in pads like the pads 18-22, but in this case, the pads are beyond the broken-away portion of the chip 10, as seen in FIG. 3.
Bridge 36 is metallic and may be made of any convenient platable or depositable metal. It has two principal functions. The first is to electrically connect the sources of the several field effect transis¬ tors. The second is to carry away heat from the sources. Accordingly, the bridge is preferably about 3 mils thick to prevent the electric field at the FET from penetrating into the mounting substrate material. Silver-plated layers to three mils are suitable. On the other hand, multiple plated layers such as titanium, tungsten, copper and lead-tin are suitable, as is a plating series of titanium, gold, and silver with PbSn or Pbln solder. The bridge 36 has openings 38, 40 and 42 where the bridge passes over the gates and drains to prevent short circuit thereof. On the other hand, the bridge 38 has a flat top 44 by which the chip and bridge are supported from base 46. The base may be any convenient preferably dielectric support, such as ceramic. The dielectric support may be in the ceramic class, such as alumina, beryllia, aluminum nitride or silicon carbide. On the other hand, the substrate may be a thermally conducting organic dielect¬ ric material. The top surface of the substrate carries printed wiring which connects to'-the pads and bridge on the semiconductor chip. For example, printed wiring lines 48, 50 and 52 (see FIG. 1) may carry on the near end thereof (see FIG. 1) underneath the semiconductor chip 10 pads which are respectively in contact with the pads 18, 20 and 22 so that drain connections are made thereto. Similarly, pads on the gate connection lines may contact pads on the base 46 to carry printed wiring connections to the gates out on the substrate where connections can be made. The height of the bridge above the semiconductor chip and the height of the pads above the semiconductor chip, as seen in FIG. 3, are the same height so that all make contact with pads on the top of the base 46, as seen in FIG. 1. In this way, electrical connections and heat extraction connections are made simultaneously. With this construction, the chip does not have to be thinned to extract the heat because the heat is extracted from the face at which it is generated. Thus, larger chip wafers in the conventional 25 mil thickness can be handled. Heat extraction from the bridge 36 is easily achieved because the substrate 46 can be chosen to have high thermal conductivity, and can be configured to be close to a heat extraction point. By this construction, a higher power integrated circuit chip FET amplifier is achieved by more efficient geometry for the transfer of heat to a heat sink.
This invention, having been described in its presently contemplated best mode, is susceptible to numerous modifications, modes and embodiments within the ability of those skilled in the art and without the exercise of the inventive faculty. Accordingly, the scope of this invention is defined by the scope of the following claims.

Claims

CLAIMS What is Claimed is:
1. A semiconductor device comprising: a chip of semiconductor material, said chip having an active face with semiconductor features at said active face; and first electrically conductive connections on said active face for connecting to some of said semicon¬ ductor features at said active face, an electrically conductive bridge spanning said first electrically conductive connections, said electrically conductive bridge being made of metal for both electrical connection and thermal connection to said active face so that said bridge can be mounted on a base for support of said semiconductor chip and for the extraction of heat from said semiconductor chip.
2. The device of Claim 1 wherein there are connector pads on said active face of said semiconductor chip, said connector pads being mounted on said first electrically conductive connectors and said pads being substantially the same height from said active face as said bridge so that both said pads and said bridge can be mounted against a base for supporting said chip and extracting heat from said chip. -
3. The device of Claim 2 wherein said semicon¬ ductor features comprise a plurality of field effect transistors and said bridge has a plurality of openings with each of said openings spanning a field effect transistor.
4. The device of Claim 3 wherein said semicon¬ ductor chip is made of gallium arsenide.
5. The device of Claim 1 wherein said semicon¬ ductor chip is made of gallium arsenide.
6. The device of Claim 3 wherein each said bridge controls the electric field of the field effect transistor which it spans to maximize frequency response of the field effect transistor.
7. An electronic device comprising: a semiconductor chip having an active face, an active electronic device comprising a field effect transistor in said active face; an electrically conductive drain connection on said active face and an electrically conductive gate connection on said active face; a metallic bridge extending over said gate and drain connections, said metallic bridge being a source bridge connected to the source of said field effect transistor, said source bridge having a top; a base for supporting said semiconductor chip and extracting heat therefrom, said top of said source bridge lying against said base to extract heat from said semiconductor chip and support said semiconductor chip.
8. The device of Claim 7 wherein at least some of said connections have connector pads thereon, said connector pads having a top in the same plane as said flat top of said bridge so that said pads also support said semiconductor chip with respect to said base.
9. The device of Claim 8 wherein there is a plurality of field effect transistors on said active face and said bridge has a plurality of openings each spanning a field effect transistor.
10. The device of Claim 9 wherein said bridge is metallic.
11. The device of Claim 10 wherein said base is dielectric.
12. The device of Claim 8 wherein said base is of high thermal conductivity material.
13. The device of Claim 9 wherein said bridge is sufficiently thick so as to increase the strength of the device to reduce chip cracking during manufacture and assembly.
14. The method of extracting heat from a semicon¬ ductor chip having a field effect transistor on the active face thereof comprising the steps of: spanning the gate and drain of the field effect transistor with a source bridge which is of suffi¬ cient mass to support the semiconductor chip and extract heat from the sources thereon; and mounting the semiconductor chip with its source bridge against a heat-extracting and chip-support- ing base to both support the chip and extract heat from the source thereon.
15. The method of Claim 14 wherein the step of spanning the gate and the drain of the field effect transistor with the source bridge includes forming a source bridge of sufficient strength to increase the robustness of the semiconductor chip with its source bridge thereon so as to reduce damage to the chip during the manufacturing and assembly steps.
16. The method of Claim 14 further including the steps of making drain and gate connections on the active surface of the semiconductor chip to the gate and drain therein; forming connecting pads on the source and drain connections to be of the same height as the source bridge; and mounting both the source bridge and pads against a supporting and heat-extracting base.
17. The method of Claim 16 wherein the step of spanning the gate and the drain of the FET transistor with the source bridge includes forming a source bridge of sufficient strength to increase the robustness of the semiconductor chip with its source bridge thereon so as to reduce damage to the chip during the manufacturing and assembly steps.
EP94905947A 1992-12-22 1993-12-21 Fet chip with heat-extracting bridge Ceased EP0627124A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US99482292A 1992-12-22 1992-12-22
US994822 1992-12-22
PCT/US1993/012495 WO1994015361A1 (en) 1992-12-22 1993-12-21 Fet chip with heat-extracting bridge

Publications (1)

Publication Number Publication Date
EP0627124A1 true EP0627124A1 (en) 1994-12-07

Family

ID=25541099

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94905947A Ceased EP0627124A1 (en) 1992-12-22 1993-12-21 Fet chip with heat-extracting bridge

Country Status (6)

Country Link
EP (1) EP0627124A1 (en)
JP (1) JPH07505016A (en)
AU (1) AU668463B2 (en)
CA (1) CA2117460A1 (en)
IL (1) IL108151A0 (en)
WO (1) WO1994015361A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2737342B1 (en) * 1995-07-25 1997-08-22 Thomson Csf SEMICONDUCTOR COMPONENT WITH INTEGRATED THERMAL DISSIPATOR

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183041A (en) * 1978-06-26 1980-01-08 Rca Corporation Self biasing of a field effect transistor mounted in a flip-chip carrier
CA1200326A (en) * 1982-11-26 1986-02-04 Franco N. Sechi High-power dual-gate field-effect transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9415361A1 *

Also Published As

Publication number Publication date
AU5985694A (en) 1994-07-19
AU668463B2 (en) 1996-05-02
JPH07505016A (en) 1995-06-01
WO1994015361A1 (en) 1994-07-07
IL108151A0 (en) 1994-04-12
CA2117460A1 (en) 1994-07-07

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