EP0616743A1 - Combinaison de deux signaux, le deuxieme apparaissant en tant que bruit pour le premier - Google Patents

Combinaison de deux signaux, le deuxieme apparaissant en tant que bruit pour le premier

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Publication number
EP0616743A1
EP0616743A1 EP92924829A EP92924829A EP0616743A1 EP 0616743 A1 EP0616743 A1 EP 0616743A1 EP 92924829 A EP92924829 A EP 92924829A EP 92924829 A EP92924829 A EP 92924829A EP 0616743 A1 EP0616743 A1 EP 0616743A1
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EP
European Patent Office
Prior art keywords
signal
values
information
code
modified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92924829A
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German (de)
English (en)
Inventor
Anthony Lawrence Mcfarthing
Peter Martin Terrell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signal Processors Ltd
Original Assignee
Signal Processors Ltd
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Filing date
Publication date
Application filed by Signal Processors Ltd filed Critical Signal Processors Ltd
Publication of EP0616743A1 publication Critical patent/EP0616743A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18513—Transmission in a satellite or space-based system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system

Definitions

  • This invention relates to a method and apparatus for combining signals for transmission and reception 5 and/or recording, and to a signal itself.
  • the invention is primarily, but not exclusively, concerned with the combination of communication signals transmitted and received via a satellite.
  • a frequency division multiplex (FDM) technique may be employed, in which the transmission channel bandwidth is divided into frequency bands. Signals may then be transmitted in parallel using different frequency
  • the document teaches a method of combining and transmitting signals whereby the parity bit in each block of information is modified by combining it with a bit from a second signal by modulo-2 addition.
  • the parity bit from each block is stripped off and the second signal is reconstructed using a majority decision technique. That is, each bit in the second signal is transmitted an odd number of times, for example 9 times, and the value on receipt is determined on the basis of whether a 0 or 1 is received the most (eg a value 1 is assigned if out of the 9 transmissions five Is are received and 4 0s).
  • the parity bits are then returned to their original values so that the first signal may be recovered. This technique suffers from three disadvantages.
  • the ability of the code to detect when errors have occured is reduced since if there is an error using the majority decision technique the parity bit may not be returned to its original value.
  • each bit in the second signal has to be transmitted many times.
  • the technique requires that the sources of the first signal and the second signal be co-located in order that the signals can be combined.
  • a method and apparatus for combining signals in which a first signal is combined with a second signal by introducing systematic errors into the second signal.
  • the systematic errors are treated as errors due to noise and corrected when the combined signal is passed through a decoder.
  • the timing of the systematic errors is identified and the values of the combined signal at such times are determined.
  • a signal which is generated using the method previously described.
  • Figure 1 shows a communications network in which users transmit signals to and receive signals from other users via a satellite
  • Figure 2 is a block diagram of the components used in a first embodiment to transmit and receive signals in the network illustrated in Figure 1;
  • Figure 3 is a truth table for an exclusive OR (XOR) gate used in an embodiment
  • FIG. 4 illustrates quaternary phase-shift keying (QPSK)
  • Figure 5 shows a signal decoder used in an embodiment
  • Figure 6 illustrates the effect of noise on a QPSK signal
  • Figure 7 is a block diagram of the components used in a further embodiment to transmit and receive signals in the network shown in Figure 1;
  • Figure 8 illustrates the relative timing of first and second signals in an embodiment
  • Figure 9 shows the effect of combining first and second signals at the satellite in an embodiment
  • Figure 10 illustrates signal levels before and after combination of first and second signals at the satellite in an embodiment
  • Figure 11 shows a signal decoder in an embodiment.
  • a satellite communications network comprises a number of very small aperture terminals (VSATs) 1 which transmit signals to and receive signals from a satellite 2.
  • VSATs very small aperture terminals
  • Each VSAT 1 comprises an antenna 3 and a processor 4 connected to the antenna 3 via a waveguide 5.
  • Each processor 4 comprises a transmission channel 10 and a receive channel 11. These channels are shown for separate
  • VSATs (VSAT 1 and VSAT 2) in Figure 2.
  • a first signal which is defined as a
  • control signal is applied to a control signal FEC encoder 13.
  • the control signal comprises a number of words represented by bits. These bits will be systematically introduced into the user signal one at a time, as will now be described.
  • the encoders 12 and 13 are controlled by a microprocessor 14, and encode the user signal and control signal by computing redundant bits which are added to the transmitted data to allow the receiving VSAT (VSAT 2) to detect and correct errors in the data.
  • the user signal FEC encoder 12 encodes the user signal so as to be decodable according to a standard Viterbi algorithm as disclosed for example in J J Spilker, "Digital Communications by Satellite", Prentice-Hall 1977, and the control signal FEC encoder 13 encodes the control signal according to a standard Trellis algorithm as disclosed for example in G Ungerboek, "Trellis-Coded Modulation with Redundant Signal Sets," IEEE Communications Magazine, Vol 25 No 2, February 1987, pp 5-21.
  • the outputs from the encoders 12 and 13, each of which is a binary signal representing bits, are applied to the inputs of an XOR gate 15 which has a truth table as shown in Figure 3.
  • the XOR gate 15 performs modulo-2 addition of the input bits.
  • the microprocessor 14 ensures that for every bit output by the user signal FEC encoder 12, there is a bit output from the control signal FEC encoder 13 such that the two bits form simultaneous inputs to the XOR gate 15.
  • the microprocessor 14 controls the control signal FEC encoder 13 such that a bit having a value 0 is output for every bit output by the user signal FEC encoder 12.
  • the bits output from the user signal FEC encoder 12 pass through the XOR gate 15 unchanged.
  • the microprocessor 14 controls the control signal FEC encoder 13 so that control signal bits are output at the correct frequency and have the correct value.
  • the freqency of transmission of control signal values is determined on the basis of the frequency at which errors are likely to occur due to noise during transmission and reception of the user signal alone. In a typical network, as illustrated in Figure 1, noise causes, on average, one error in every one hundred bits that are transmitted. Control signal bits are therefore combined with the user signal bits at a frequency which is less than the frequency of errors introduced by noise.
  • the microprocessor 14 combines one control signal bit with every one thousandth user signal bit.
  • the microprocessor 14 monitors the bits to be output by the user signal FEC encoder 12.
  • the microprocessor 14 drives the control signal FEC encoder 13 such that a signal is output having the correct bit value for the control signal. That is, the microprocessor 14 drives the control signal FEC encoder 13 such that:
  • the microprocessor 14 ensures that a value 0 is output by the control signal FEC encoder 13 to the XOR gate 15. In this way, the user signal bit value retains its value.
  • the microprocessor 14 drives the control signal FEC encoder 13 such that a value 1 is output to the XOR gate 15. In this way, the value of the user signal bit is changed.
  • Bits output from the XOR gate 15 are passed to a modulator 16.
  • the modulator 16 performs quaternary phase shift keying (QPSK) signal processing in a conventional manner. This is illustrated in Figure 4.
  • QPSK quaternary phase shift keying
  • the modulator 16 modulates the bit-stream input from the XOR gate 15 onto a sinusoidal carrier of a constant frequency by changing the phase of the carrier.
  • the phase is modulated such that the output signal may take one of four possible states 19, 20, 21 or 22 depending upon the values of the last two input bits.
  • the four possible states are
  • the output of the modulator 16 is amplified by an amplifier 17 and passed to the antenna 3 via an output filter 18 and a waveguide 5.
  • the output filter 18 is a conventional band-pass filter which rejects unwanted frequencies that may have been produced during amplification, harmonics and other spurious signals.
  • the antenna 3 transmits the carrier signal to the satellite 2 which relays it to the antenna 3 of a different VSAT (VSAT 2). Upon reception, the carrier signal is passed to the receive channel 11 within the processor 4 of VSAT 2 via a waveguide 5.
  • the carrier signal is first passed through an input filter 25 which is a conventional band-pass filter which removes noise and spurious signals which occur at unwanted frequencies.
  • the carrier signal is then passed through a signal-level detector 26 which determines the amplitude of the signal and drives an amplifier 27 in accordance with the detected level such that the carrier signal is amplified so as to lie within the input range required by a demodulator 28.
  • the demodulator 28 demodulates the QPSK signal in a conventional manner. This involves determining the phase of the carrier signal and outputting a signal which represents these values. This signal is then passed to a decoder 29.
  • Figure 5 shows the decoder 29.
  • the signal output by the demodulator 28 is input to a processor 35.
  • the processor 35 uses the signal, which represents the phase of the carrier signal, to assign bit values (0 or 1) based on the determined carrier phase with respect to the allowed states 19, 20, 21 and 22 shown in Figure 4 (that is,
  • the processor 35 also assigns, in a conventional manner, a probability value for each bit, which represents the probability that it has assigned the value correctly.
  • the probability value is determined in accordance with the difference between the phase of the carrier signal measured by the demodulator 28 and the four standard phases 19,
  • the first bit is the assigned signal bit value 0 or 1 and the second and third bits represent the assigned probability value.
  • the processor 35 provides two outputs, which are shown passing along connections A and B in Figure 5. As will now be described, these signals are: along A : (ENC.USER ENC.CONTROL) + NOISE + PROBABILITY INFORMATION.
  • the output comprises three bit words as previously described and is an encoded user signal combined with an encoded control signal together with noise and probability information.
  • This output is passed to a user signal FEC decoder 36 which decodes the signal according to the conventional Viterbi algorithm used by the user signal FEC encoder 12 in VSAT 1.
  • the user signal FEC decoder 36 removes errors due to noise and due to the control signal, and outputs a user signal which is essentially error free.
  • This signal is then passed through a user signal FEC encoder 12 which re-encodes the signal according to the standard Viterbi algorithm used by the user signal FEC encoder 12 in VSAT 1.
  • the output from the user signal FEC encoder 12 is an encoded user signal which is shown travelling along connection C in Figure 5.
  • This signal is then applied to one input of an XOR gate 15 and the output from the processor 35 which travels along connection B is applied to the other input.
  • the signal travelling along connection B is the same as that travelling along connection A but has had the probability information removed by the processor 35, that is it consists of a stream of single bits, with each bit representing the value assigned to the signal from the demodulator 28 by the processor 35.
  • the processor 35 outputs the bits along connection B at the correct timing to ensure that the inputs to the XOR gate 15 are synchronised, that is, a bit which has travelled along connection B is input at the same time as the bit which was output by the processor 35 in response to the same input signal value from the demodulator 28 along connection A which has subsequently been modified by the user signal FEC decoder 26 and encoder 12 before being applied as an input to the XOR gate 15 via connection C.
  • the operation of the XOR gate 15 will now be described.
  • the XOR gate 15 has the truth table shown in Figure 3 and outputs a signal along connection D which comprises: (ENC.USER ( ⁇ ) ENC.USER ⁇ ENC.CONTROL) + (ENC.USER ⁇ NOISE) as will now be described.
  • bits input via connections B and C to the XOR gate 15 are the same and hence the bit output along connection D is 0.
  • the inputs to the XOR gate 15 are different and the bit output along D takes a value 1. As described previously, such an error occurs on average every 100 user signal bits.
  • the input bits to the XOR gate 15 depend upon whether the value of the control signal bit is the same as the user signal bit. If they are the same, the inputs are the same and the output of the XOR gate 15 is a 0. If they are different, the output of the XOR gate 15 is a 1.
  • the output from the XOR gate 15 is passed along connection D to a processor 37. If there were no corruption due to noise, the signal passing along D would comprise a stream of 0s when there was no control signal present, and a stream of 0s modified in that every one thousandth bit may be a 1 or 0 depending upon the value of the control signal when such a signal is present. However, in practice noise means that there will be Is in the stream of Os even when there is no control signal present.
  • the processor 37 identifies the time slots of the control signal bits and maintains a "lock" on these. To do this, the processor 37 selects one bit of the signal input along D at random, for example the first bit it receives.
  • the processor 37 determines the value of every one thousandth bit thereafter until it has collected one hundred such values.
  • the processor 37 adds the one hundred values obtained and compares the result with a threshold. If the result is above the threshold, the processor 37 determines that it has correctly identified the time slots in which the control signal bits are being sent. If the result is below the threshold, then the processor 37 disregards the values collected, and repeats the process collecting one hundred samples, the time slots of these samples being displaced by time slot with respect to the previous one hundred samples collected. The processor 37 continues to repeat this process until the sum of one hundred samples lies above the threshold.
  • the value of the threshold is set so as to provide a test to ensure that there is a sufficiently large number of Is in the 100 samples for the processor 35 to determine that the Is are caused by the control signal rather than noise.
  • the processor 37 Having identified the time slots in which control signal bits are being transmitted, the processor 37 passes only values received in these time slots to the control signal FEC decoder 38. However, the processor 37 continues to add samples separated by one thousand time slots to obtain one hundred samples and compare these against the threshold in the manner previously described. If at any time the sum of the samples lies below the threshold, the processor 37 takes samples displaced by one time slot and continues the process until it has regained the "lock" on the control signal time slots.
  • the control signal FEC decoder 38 decodes the input signal by applying a conventional Trellis decoding algorithm.
  • the output from the control signal FEC decoder 38 is a control signal relatively free from errors.
  • the first embodiment was described with reference to VSATs, that is antennas that are the equivalent of 1.8 metres diameter or less.
  • VSATs that is antennas that are the equivalent of 1.8 metres diameter or less.
  • any satellite antenna may be used.
  • a Viterbi code was used for the FEC code of the user signal and a Trellis code was used as the FEC code for the control signal.
  • a Trellis code was used as the FEC code for the control signal.
  • Different codes may be used. The same code may be selected for the user signal and the control signal. Examples of codes include convolutional codes such as Viterbi, Trellis, sequential, Reed-Solomon and Golay codes, and block codes such as Bose-Chaudhuri-Hocquenhem (BCH) and Hamming codes.
  • a Viterbi code was used in the first embodiment for the user signal since it has a high ability to detect and correct errors.
  • the selection of the code determines the number of bits which need to be transmitted. This is because, as described previously, redundant bits are introduced into a signal when it is FEC encoded, the number of redundant bits being determined by the particular type of code. In the case of the control signal, this is particularly important because it affects the time required to transmit the signal. Trellis coding was used in the first embodiment as the
  • FEC code of the control signal because it is an efficient code, that is it introduces a relatively small number of redundant bits compared with other codes.
  • Trellis coding could be used in conjunction with Reed-Solomon coding for either or both of the user and control signals.
  • Reed-Solomon code may remove any errors remaining after decoding the Trellis code. Such errors may remain since decoding of convolutional codes (including Trellis and Viterbi codes) may produce burst type errors.
  • one control signal value is introduced every one thousand user signal values. However, control signal values may be introduced more or less frequently. The maximum frequency at which the values may be introduced is dependent on the strength of the user signal FEC code, that is its ability to correct errors, and the amount of errors that can be tolerated in the output signal at the receiver.
  • An XOR gate 15 is used in the first embodiment to modify user signal values with control signal values.
  • the XOR gate 15 may be replaced by any other device which achieves this. A corresponding modification would be made in the decoder.
  • the modulator 16 performs QPSK signal processing.
  • any form of modulation may be performed, for example binary phase shift buying (BPSK) or 8-PSK.
  • BPSK binary phase shift buying
  • 8-PSK 8-PSK.
  • the demodulator 28 in the receive channel 11 of VSAT 2 would need to be changed accordingly.
  • the modulator 16 and demodulator 28 are described as separate devices. However, since the processor 4 of each VSAT 1 comprises a transmission channel 10 and a recieve channel 11, the modulator 16 and demodulator 28 may be replaced by a modem.
  • processors 35 and 37 are shown. These may be replaced by a single processor performing the same functions.
  • the signal output by processor 35 along connection B has had the probability information removed by the processor 35.
  • the probability information may be left in this signal so that it may be used by the processor 37 and/or control signal FEC decoder 38.
  • the processor 37 achieves and maintains "lock” to the time slots of the control signal values.
  • the same control signal value may be transmitted in time slot 1 and time slot 500, or in time slot 1, time slot 250, time slot 500 and time slot 750. In this way, the time required to achieve or regain "lock" is reduced.
  • the frequency with which the control signal values can be repeated is determined by the strength of the FEC code of the user signal and the amount of errors that are tolerable in the output signal from the decoder.
  • control signal values are introduced into the user signal at frequency Fl (one control signal bit every 500 user signal bits say) then the decoder 29 may assign a value 0, and it would assign a value 1 if the frequency is F2 (one control signal bit every 1000 user signal bits for example) . Alternatively, the decoder 29 may assign a value 0 if there are no control signal values in the expected time slots and a value 1 if there are control signal values present.
  • VSAT transmitting the control signal does not need to be co-located with the VSAT transmitting the user signal.
  • the second embodiment is applicable to a satellite communications network as shown in Figure 1, and will be described with reference to Figures 7 to 11. With reference to Figure 7, there are shown three VSATs in a satellite communication network. VSAT
  • VSAT 3 receives the user signal and control signal from the satellite 2.
  • VSAT 1 In transmitting the user signal, VSAT 1 passes the signal through a user signal FEC encoder 12 which encodes the signal so as to be decodable according to a conventional Viterbi algorithm.
  • the binary signal output by the user signal FEC encoder 12 is input to a modulator 16 which performs QPSK signal processing as described in the first embodiment.
  • the output from the demodulator 16 is passed through an amplifier 17 and an output filter 18 before being passed to an antenna
  • VSAT 2 receives the user signal carrier from the satellite 2 via its antenna 3. The signal is then passed to the receive channel 11 via a waveguide 5.
  • the signal passes through an input filter 25 which removes noise and spurious signals at unwanted frequencies, and a signal level detector 26 which determines the amplitude of the received carrier and drives an amplifier 27 so as to amplify the signal to lie within the defined input range of a demodulator 28.
  • the demodulator 28 demodulates the signal in a conventional manner and outputs a signal which represents the amplitude and phase of the user signal carrier received from the satellite 2.
  • the output of the demodulator 28 is then passed to a processor 50 within the transmission channel 10 of VSAT 2.
  • the processor 50 monitors the signal from the demodulator 28 and controls the control signal FEC encoder 13, modulator 51 and amplifier 52 which are used during the transmission of the control signal in a manner which will now be described.
  • the processor 50 determines the timing of the user signal carrier values at the satellite 2, and drives the control signal FEC decoder 13 and modulator 51 such that:-
  • Each control signal carrier value is transmitted such that it arrives at the satellite and corrupts only one user signal carrier value. That is, the processor 50 synchronises the timing of the control signal carrier values with the user signal carrier values.
  • Point (b) is illustrated in Figure 8. With reference to Figure 8, there is shown the frequency spectra 60, 61 and 62 of user signal carrier values from three adjacent time slots. Each spectrum has the form of a sin x/x function. The frequency spectrum of a control signal carrier value 63 also has the form of a sin x/x function.
  • the processor 50 controls the control signal FEC encoder 13 and modulator 51 such that the frequency spectrum 63 of the control signal carrier value is the same after the user signal carrier and control signal carrier have been filtered by the input filter 25 in the receive channel 11 of VSAT 3 as that of the spectrum 61 of the user signal carrier value which it is desired to corrupt.
  • the zero crossings of the tails of the control signal carrier value spectrum occur at the centres of neighbouring user signal carrier value spectra, and hence the corruption of the control signal carrier value is limited to one user signal carrier value only.
  • the processor 50 monitors the signal from the demodulator 28 and controls the amplifier 52 so as to amplify the signal from the modulator 51 such that the signal-to-noise ratio of the user signal carrier and the control signal carrier at the satellite will be approximately the same.
  • control signal is passed through a control signal FEC encoder 13 which encodes the signal according to a standard Trellis algorithm.
  • the output from the encoder 13, which is a binary signal, is input to a modulator 51 (which is under the control of the processor 50 as previously described) which performs QPSK signal processing, the frequency of the carrier signal being the same as that of the user signal carrier.
  • the output of the modulator 51 is then passed through the amplifier 52 (which is also controlled by the processor 50 as previously described), and an output filter 18 before being passed to the antenna 3 via the waveguide 5.
  • the output filter 18 is of the same nature as that in the first embodiment and performs the same functions as described with reference to the first embodiment.
  • the satellite 2 combines the user signal carrier transmitted by VSAT 1 and the control signal carrier transmitted by VSAT 2 by linear addition, which is one of the few simple signal combination operations a conventional satellite is able to perform without on-board communication signal processes.
  • This is illustrated in Figure 9.
  • a vector 65 representing the phase and amplitude of the user signal carrier and a vector 66 representing the phase and amplitude of the control signal carrier are linearly added to produce a resultant vector 67.
  • the linear addition process in the satellite 2 is further illustrated in Figure 10.
  • the envelope of a resultant carrier signal 72 comprises the envelope of the user signal carrier 70 plus the envelope of the control signal carrier 71.
  • the amplitude of the resultant carrier signal 72 is greater than the amplitude of the user signal carrier 70 alone.
  • a protocol is introduced such that control signal carrier values do not arrive at the satellite simultaneously causing simultaneous increases in signal power and overloading the satellite.
  • VSAT 3 receives the resultant carrier (that is, the user signal carrier and the control signal carrier) from the satellite 2. Within the receive channel 11 of VSAT 3, the signal is passed from the antenna 3 to an input filter 25 via a waveguide 5.
  • the input filter is of the same nature and performs the same functions as described previously with reference to the first embodiment.
  • the signal from the input filter 25 is passed through a signal level detector 26 which drives an amplifier 27 to amplify the signal by a known factor (defined as "X") such that the signal amplitude is within the acceptable input range of a demodulator 28.
  • the demodulator 28 outputs a signal representing the amplitude and phase of the input signal.
  • the output from the demodulator 28 is a signal representing the amplitude and phase of the user signal carrier, that is the amplitude and phase of the vector 65 shown in Figure 9.
  • the output from the demodulator 28 is a signal representing the amplitude and phase of the resultant vector 67 shown in Figure 9.
  • the outputs of the demodulator 28 are passed to a decoder 75 together with information on the amplification factor "X" from the signal level detector 26.
  • the decoder 75 is shown in Figure 11.
  • the signal from the demodulator 28 travels along connections H.
  • This signal is the resultant vector multiplied by an amplification factor "X" which was introduced by the signal level detector 26 and amplifier 27 so that the signal lay within the input range of the demodulator 28, together with noise multiplied by the same amplification factor. That is, the signal which passes along connection H is:-
  • the signal is input to a processor 80 and, via a delay device 84, to a linear subtractor 81.
  • the processor 80 performs the same function as the processor 35 in embodiment 1. That is, it assigns bit values (0 or 1) based on the phase of the received vector with respect to the four defined QPSK phases shown in Figure 4. It also assigns a probability value as described with reference to the first embodiment which represents the probability that it has assigned the value correctly.
  • the output from the processor 80 is a series of three bit words, the first bit representing the assigned value 1 or 0 and the second and third bits representing the assigned probability value.
  • the output is (ENC.USER) + NOISE + PROBABILITY INFO.
  • connection I This travels along connection I, before being input to a user signal FEC decoder 36 which decodes the signal according to the same standard Viterbi algorithm used by the user signal FEC encoder 12 in VSAT 1.
  • the decoder 36 removes errors due to noise and to corruption by the control signal, and outputs an essentially error free user signal.
  • This signal is then passed through a user signal FEC encoder 12 which outputs an encoded user signal along connection J.
  • This signal is input to a processor 82 together with a signal from the signal level detector 26 which represents the amplification factor "X" introduced into the signal as it passed through the amplifier 27.
  • the signal from the signal level detector 26 is input to the processor 82 via connection K.
  • the processor 82 multiplies the encoded user signal input via connection J by the amplification factor "X" (i.e. the signal input via connection K) , remodulates the resultant signal, and outputs a signal along L which is a signal representing the amplitude and phase of the user signal vector after multiplication by the amplification factor "X" .
  • the signal output by the processor 82 along L is then applied to one input of a subtractor 81 and the signal from the demodulator which travels along connection H, is applied to the other input via a delay device 84.
  • the delay device 84 operates so as to ensure that the inputs to the subtractor 81 are synchronised, that is a signal value which has travelled via the delay device 84 to the subtractor 81 is input at the same time as the same signal value which has been modified by processor 80, user signal FEC decoder 36, user signal FEC encoder 12 and processor 82, and is input to the subtractor 81 via connection L.
  • the subtractor 81 linearly subtracts the signal input along L from the signal input along H and outputs a signal along M which is the control signal vector (66 in Figure 9) multiplied by the amplification factor "X", together with noise multiplied by the amplification factor "X" .
  • the signal output by the subtractor 81 is then passed through a further processor 83 which assigns bit values (0 or 1) based on the phase of the control signal carrier with respect to the four defined phases of the QPSK signal.
  • the processor 83 also performs the process of "locking" to the control bit time slots and maintaining this lock as described in the first embodiment with reference to processor 37.
  • Control signal bits are passed from the processor 83 to the control signal FEC decoder 38 which decodes the control signal according to the conventional Trellis algorithm used by the control signal FEC encoder 13 in VSAT 1.
  • the output from the control signal FEC decoder 38 is an essentially error free control signal.
  • the modulator 51 performs QPSK signal processing. However, any form of modulation may be applied to the signal.
  • the types of modulation applied to the user signal and the control signal need not be the same.
  • the modulator 51 may be replaced by a frequency-agile modulator.
  • the processor 50 would drive the frequency-agile modulator such that a first control signal carrier value would be transmitted at a first frequency followed by a second control signal carrier value at a second frequency and a third control signal carrier value at a third frequency etc.
  • VSAT 2 could provide control signal information on numerous satellite frequency channels. Since a properly transmitted carrier signal has both a main lobe and side lobes, at any time the frequency-agile modulator would be outputting components at different frequencies from contiguous control signal carrier values. In a further modification, only the main lobes need be transmitted, thus avoiding transmitting two frequencies simultaneously.
  • the transmission VSAT transmits the user signal carrier at a first frequency and at the time slot corresponding to every one thousandth value, it changes frequency and transmits a control signal carrier value. That is, a complete user signal carrier value including side lobes is removed and replaced by a control signal carrier value and its side lobes at a different frequency.
  • the VSAT receiving the user signal carrier will receive no signal during the period when the control signal carrier value is transmitted. This is treated as an error due to noise and may be removed in the decoder.
  • This modification would enable a single VSAT to transmit user signal and control signal carriers without having to do so simultaneously at two frequencies, which would require extra power. In a further modification, only the main lobe of the user signal carrier value is removed.
  • the processor 50 in the transmission channel 10 of VSAT 2 drives the amplifier 52 such that the signal-to-noise ratios of the user signal carrier and control signal carrier at the satellite 2 are similar. It is possible to make the amplitude of the control signal carrier larger than the amplitude of the user signal carrier to make the control signal carrier values robust against imperfect removal of the user signal carrier in the decoder 75 in the receive channel of VSAT 3.
  • the user signal carrier and the control signal carrier are synchronised to produce the frequency spectra illustrated in Figure 8.
  • errors in the transmission channel 10 of VSAT 2 may create discrepancies in the synchronisation.
  • the effect of such synchronisation errors may be reduced by modifying the demodulator 28 in the receive channel 11 of VSAT 3 and introducing an extra processor into the decoder 75 of VSAT 3.
  • the demodulator 28 outputs a signal indicating the amplitude and phase of the input signal once every time slot.
  • the demodulator 28 may be modified so that two signals are output representing the amplitude and phase of the input signal at different times within a single time slot. In this way, it is likely that information on the amplitude and phase of the user signal and control signal can be attained.
  • the extra processor in the decoder 75 would determine if the synchronisation of the user signal and control signal is erroneous and correct the timing if necessary, for example by introducing a delay into the control signal values.
  • the processor would output correctly synchronised signals.
  • the strength of the FEC code of the user signal and the level of errors which are acceptable will determine whether such a modification can be made.
  • One possible use of such a modification is to send an unsynchronised control signal which performs the operation of terminating the link.
  • differences in the tolerances of the oscillators in modulator 16 used to modulate the user signal and modulator 51 used to modulate the control signal may cause the frequency of the user signal carrier and the control signal carrier to differ, for example by a few kHz. Since, in the receive channel 11 of VSAT 3 there is a relatively long time between control signal values (one thousand time slots), the effect of the frequency difference is magnified causing the processor 83 in the decoder 75 difficulties in maintaining "lock”.
  • Use of a phase-lock-loop technique or differential phase shift keying (DPSK) with a frequency discriminator may be employed to reduce these problems.
  • DPSK is described in J J Spilker, "Digital Communications by Satellite", Prentice Hall 1977.
  • bit values are assigned to the demodulated signal on the basis of consecutive carrier values. That is, if consecutive values are different, a bit value of 1 is assigned and if consecutive values are the same, a bit value of 0 is assigned.
  • a differential modulation technique may be employed, particulrly if the control signal is of a low bit rate.
  • the invention may be applied in any transmission and/or recording system.
  • the invention may be applied to cellular radio networks.
  • the invention may also be applied to computer data storage media, for example the hard disc in a personal computer.
  • data is stored on the hard disc in a coded form which allows the detection and correction of errors when it is read, and a second data set is subsequently written onto the disc, introducing bits from the second data set by overwriting bits from the first data set at predetermined intervals.
  • the same procedure can be applied to floppy discs.
  • the invention may be applied in embodiments to covertly transmit or store signals.
  • a signal described as a "control signal” is disclosed.
  • this signal may be used as an engineering order wire (EOW) signal.
  • EOW engineering order wire

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Artificial Intelligence (AREA)
  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • Aviation & Aerospace Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Les utilisateurs d'un réseau de communication par satellite émettent des signaux vers un satellite (2) et reçoivent des signaux dudit satellite (2). Afin d'émettre une pluralité de signaux à l'intérieur des limites de la largeur de bande de canal de communication disponible, on combine un premier signal à un deuxième signal en introduisant des modifications dans le deuxième signal à des intervalles prédéterminés. On peut effectuer la combinaison de signaux au niveau de l'émetteur ou au niveau du satellite (2). Dans le but de séparer le deuxième signal, on traite les modifications en tant qu'erreurs dues au bruit et on les corrige quand le signal combiné passe à travers un décodeur (29, 75). Dans le but de séparer le premier signal, on identifie la période des modifications et on détermine les valeurs du signal combiné au moment desdites périodes.
EP92924829A 1991-12-11 1992-12-11 Combinaison de deux signaux, le deuxieme apparaissant en tant que bruit pour le premier Withdrawn EP0616743A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB919126431A GB9126431D0 (en) 1991-12-11 1991-12-11 Data transmission technique
GB9126431 1991-12-11
PCT/GB1992/002309 WO1993012598A1 (fr) 1991-12-11 1992-12-11 Combinaison de deux signaux, le deuxieme apparaissant en tant que bruit pour le premier

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EP0616743A1 true EP0616743A1 (fr) 1994-09-28

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EP92924829A Withdrawn EP0616743A1 (fr) 1991-12-11 1992-12-11 Combinaison de deux signaux, le deuxieme apparaissant en tant que bruit pour le premier

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EP (1) EP0616743A1 (fr)
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WO (1) WO1993012598A1 (fr)

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Publication number Priority date Publication date Assignee Title
US5521942A (en) * 1993-06-14 1996-05-28 At&T Corp. Method for increasing the dynamic range of a signal in a simultaneous voice and data system by the use of overlapping signal point regions and trellis coding
US5463641A (en) * 1993-07-16 1995-10-31 At&T Ipm Corp. Tailored error protection
EP0797877A1 (fr) * 1994-12-12 1997-10-01 BRITISH TELECOMMUNICATIONS public limited company Systeme de transmission numerique pour le codage et le decodage de donnees d'attribut en symboles de controle d'erreurs des donnees principales
US6035007A (en) * 1996-03-12 2000-03-07 Ericsson Inc. Effective bypass of error control decoder in a digital radio system

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Publication number Priority date Publication date Assignee Title
US4271520A (en) * 1979-06-25 1981-06-02 Motorola, Inc. Synchronizing technique for an error correcting digital transmission system
GB2116403B (en) * 1982-03-01 1985-10-23 British Broadcasting Corp Improvements relating to digital data transmission
DE3910739C3 (de) * 1989-04-03 1996-11-21 Deutsche Forsch Luft Raumfahrt Verfahren zum Verallgemeinern des Viterbi-Algorithmus und Einrichtungen zur Durchführung des Verfahrens
US5068858A (en) * 1989-12-21 1991-11-26 International Business Machines Corporation Error correction capability varied with track location on a magnetic or optical disk

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See references of WO9312598A1 *

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WO1993012598A1 (fr) 1993-06-24

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