EP0613595A4

EP0613595A4 - Digital demodulator.

Info

Publication number: EP0613595A4
Application number: EP92924443A
Authority: EP
Inventors: Mark D Hedstrom; Robert B Porter; Charles R Crego
Original assignee: NUMA TECHNOLOGIES Inc
Current assignee: NUMA TECHNOLOGIES Inc
Priority date: 1991-11-20
Filing date: 1992-11-17
Publication date: 1995-01-18
Also published as: CA2124114C; JPH08500942A; KR100363288B1; CA2124114A1; WO1993010596A1; EP0613595A1

Abstract

A digital demodulator for frequency modulated, pulse-width modulated and other temporally modulated signals uses a sign detector (14) to determine zero-crossings of the modulated signal. The periods between zero-crossings are determined by at least one gate circuit (16, 18) and at least one counter (22, 24) which counts clock pulses from a high-speed clock (20) gated by the gate circuit in response to zero-crossings. The period information is converted to a demodulated signal by a numerical processor (12), or a signal processor (12') or a digital-to-analog converter (12'').

Description

DIGITAL DEMODULATOR

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation-in-part application Serial No. 07/900,367, filed June 18, 1992 whi is a continuation-in-part of application Serial N 07/794,150, filed November 20, 1991.

FIELD OF THE INVENTION This invention relates to a method and apparatus f detecting and demodulating signals with temporally modulat features, and particularly to frequency modulated signals.

BACKGROUND OF THE INVENTION In Frequency Modulation (FM) , a sinusoidal carri signal of constant amplitude and frequency is modulated an input signal of a lower frequency and of varyi amplitude. FM thereby produces an output signal that constant in amplitude, varying in frequency in accordan with the input signal, and within a specified frequency ran called the deviation bandwidth. In particular, t instantaneous amplitude of the input signal is linear transformed into a change dω in the instantaneous frequen ω(t) of the carrier frequency ω_c. To recover the inp modulating signal from the output modulation signa frequency demodulation must be performed using an demodulator.

FM demodulators are well known, and consist of devic such as ratio detectors, Foster Seeley discriminators, phas locked loop detectors, pulse-counting detectors, a quadrature or coincidence detectors. All of the demodulators — whether implemented as analog or digit apparatus — pass data to post-processing stages, and ultimately to an output amplifier.

For example, the Heathkit AJ-1510 Digital FM Tuner employs a digital discrimination technique for demodulating a frequency modulated signal. The discriminator is of the pulse position modulation type, is inductorless and diodeless, and contains two integrated circuits: a retriggerable monostable multivibrator, and an operational amplifier. An input signal at the retriggerable monostable multivibrator causes it to change states for a fixed period of time, as determined by an RC network to provide a sequence of pulses of constant width and amplitude that are generated at about one-half of the IF rate. Each pulse represents a zero-crossing event. Signal information is represented as deviations in the frequency of the zero-crossing pulses from a constant IF frequency.

In a pulse integration type of FM demodulator, the frequency modulated signals typically are amplified and "hard-limited" to produce square waves which have zero- crossings spaced in the same manner as the zero-crossings of the FM signals. The square waves are then converted into a sequence of constant width and amplitude pulses, one pulse for each zero-crossing of the modulated input signal. Each pulse is integrated (or filtered) and subsequently differentiated to reproduce the modulating input signal information.

There are pulse integration demodulators that employ a single one-shot multivibrator that is triggered at each zero- crossing. However, recovery time difficulties are encountered during high frequency operation because the internal delay of the multivibrator approaches the period of the high frequency signals as the operating frequency is increased.

In another form of pulse integration demodulator, a source of frequency modulated signals is coupled to a coincidence detector by a first and second signal path. The first and second signal paths have unequal signal del characteristics, so that the coincidence detector provid an output signal that includes a series of constant wid pulses, wherein pulse width is determined by a difference signal delay between the first and second signal paths. low pass filter is coupled to the coincidence detector recover the signal modulation represented by the series constant width pulses. However, this form of pul integrator exhibits operating disadvantages due non-linearity of the integrating network which impairs i ability to perform sufficiently precise integration on t applied signal pulse train.

SUMMARY OF THE INVENTION An apparatus and method is provided for demodulating frequency modulated (FM) , pulse-width modulated (P M) , other temporally modulated signal. Without employing analog-to-digital converter, modulating signal informati is extracted from a modulated signal as numeric information. To demodulate an FM signal, for example, a hi gain stage is applied to an incoming FM signal to produce corresponding sequence of square waves. The period betwe zero-crossings of the square waves is precisely measured a represented numerically using a high-speed clock and at lea one counter. Numerical period information is then provid to a signal processor that serves to convert the sequence period measurement values into a demodulated signal with high signal-to-noise ratio.

After a received FM signal is heterodyned with a loc oscillator signal, the resulting FM intermediate frequen (IF) signal is "hard-limited" to yield a hard-limited FM signal that substantially resembles a sequence of squa waves which are provided to a sign detector for detecti zero-crossings. In preferred embodiments, the frequency the local oscillator signal . is chosen so as to yie relatively low FM IF frequencies. The sign detector coupled to a pair of gating circuits, each gating circuit being coupled to a respective pulse counter, and to a clock. The gating circuits are alternately enabled in accordance with the instantaneous sign of the hard-limited FM IF signal. When enabled, each sample gating circuit provides a sequence of clock pulses from the clock to a respective pulse counter. Each pulse counter stores a respective count value that represents the period between zero-crossings of the hard- limited FM IF signal. The foregoing elements together constitute a digital discriminator. In one embodiment, a numerical processor, connected to the counters of the digital discriminator, is responsive to the changing respective count values, and reconstructs in real time the original modulating input signal. The numerical processor performs calculations upon the signal including: weighting, scaling, impulse response filtering, windowing, and interpolation/decimation. Increasing the rate of the clock yields improved resolution in the reconstructed modulating signal, up to the maximum resolution of the counting circuit. Subsequent digital filtering provides a low pass filter function that effectively eliminates high frequency components.

The digital demodulator of the invention exploits the linearity of digital processing to provide excellent performance. Since the demodulation method of the invention requires only low level signals and introduces minimal noise, lower total noise levels result, and a high signal-to-noise ratio is achieved. Consequently, the demodulator of the invention can more easily receive weak signals, and suffers fewer "drop-outs", a problem that is now common in fringe reception areas, as well as in dense urban centers. Also, the invention reduces the need for amplification of a received signal, thereby increasing reliability and reception quality. Therefore, at a given level of transmission power, greater transmission range is possible. One potential product area is in satellite broadcast applications; a smaller antenna could be used when the method of the invention is employed within the receiver. Further, th invention can be practiced using currently available relatively inexpensive components. Also, since it i consistent and cooperative with existing modulation standard and transmission formats, the invention actually increase the value of the currently installed base of transmissio equipment. Although the invention provides benefits whe included in 2-way radio, cellular telephone, and FM broadcas applications, the invention is not limited to a specifi frequency band, or to a particular application.

The demodulation method and apparatus of the inventio introduces negligible noise, as contrasted with the level of noise added by conventional FM demodulation circuitry.

In another embodiment of the invention, a so-terme "reciprocal fit count scaling" method is employed tha provides better performance than a linear count scalin method, and improved performance with respect to a least squares-fit, nonlinear count scaling method. Such improve performance provides an estimated signal with significantl higher scaling accuracy, lower total harmonic distortion, an an excellent signal-to-noise ratio. In fact, the reciproca count scaling method provides an exact analytic solution, an guarantees the most accurate and optimal results attainabl from a system of this type.

DESCRIPTION OF THE DRAWING

The invention will be more fully understood from th following detailed description, in conjunction with th accompanying figures, in which:

Fig. 1 is a block diagram of a digital discriminato cooperative with a numerical processor;

Fig. IA is a block diagram of a digital discriminato cooperative with a signal processor;

Fig. IB is a block diagram of a digital discriminato cooperative with a digital to analog converter; Fig.2 is a schematic diagram of a digital discriminator of the type which may be used in the circuits of Figs. 1, IA and IB;

Fig. 3 is a flow diagram of a process implemented by the numerical processor of Fig. 1;

Fig. 3 is a flow diagram of a process that includes reciprocal fit count scaling;

Fig. 3B is a flow diagram of a process that includes reciprocal fit count scaling and window functions; Fig. 3C is a flow diagram of a process that includes a bounds-checking routine and a second order fit;

Fig. 4 is a plot of linear scaled and weighted count values versus the original count values, together with a plot of scaled and weighted count values augmented with a second-order nonlinear term versus the original count values;

Fig. 5 is a plot of the difference of the linear scaled and weighted count values and the scaled and weighted count values augmented with a second-order nonlinear term, versus the original count values; Fig. 6 is a plot of scaled and weighted count values augmented with a second-order nonlinear term versus the original count values, together with a plot of reciprocal fit count values versus the original count values; and

Fig. 7 is a plot of the difference of the scaled and weighted count values augmented with a second-order nonlinear term and the reciprocal fit count values, versus the original count values.

DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to Fig. 1, a digital discriminator 10 is shown in cooperation with a numerical processor 12. The digital discriminator 10 utilizes zero-crossing detection and period measurement of a "hard-limited" FM IF signal to recover an associated modulating signal by exploiting the fact that the instantaneous frequency of an FM IF signal is inversely proportional to the instantaneous period of t associated modulating signal.

Discrimination is accomplished by applying "hard-limited" FM IF signal to the sign detector 14. To fo a hard-limited signal, an input signal is amplified and th clipped to provide what is essentially a square wave. T sign detector 14 ascertains the instantaneous polarity alo each corresponding half-cycle of the FM IF signal, there defining the moment of each zero-crossing. The peri between zero-crossings is determined by providing informati regarding the moment of each zero-crossing to gating circui 16 and 18. The gating circuits 16 and 18 are alternate enabled or disabled in accordance with the instantaneous si of the hard-limited FM IF signal provided by the si detector 14. When enabled, each sample gating circu provides a sequence of clock pulses from the clock 20 to respective pulse counter 16 or 18 until the other pul counter 18 or 16 is enabled. A short sequence of clo pulses between zero-crossings corresponds to a lar modulating signal amplitude, while a long sequence of syst clock pulses corresponds to a small modulating sign amplitude. Each sequence of clock pulses is integrated a respective counter 22 or 24 to provide a count value th represents the period of a half cycle of the FM IF signa The counters 22 and 24 alternately provide count values the numerical processor 12, which can be a commercial available digital signal processor, such as the 2101 Digit Signal Processor by Analog Devices.

In an alternate embodiment, shown in Fig. IA, t counters 22 and 24 alternately provide count values to signal processor 12' that can perform at least digital-t analog conversion. The output of the signal processor is usable demodulated signal.

In another embodiment, shown in Fig. IB, the counte 22 and 24 alternately provide count values to a digital analog converter (DAC) 12' ' . Referring to FIG. 2, a preferred embodiment of the discriminator 10 of FIG. 1 will now be discussed. A hard limited IF FM signal 26 is applied to the primary winding of transformer 28. This transformer stage provides the required impedance matching to the preceding circuit stages and dc decoupling or blocking to the succeeding stage. The center tap of the secondary of transformer 28 is biased by a reference voltage source 29 at the mid-point of the circuit supply voltage to provide a DC reference voltage. The reference voltage source 29 establishes a voltage level about which the oppositely phased voltages developed across the secondary winding of transformer 28 are symmetrical. These oppositely phased voltages represent zero-axis crossings corresponding to the zero-crossings of the modulated IF FM signal. The signal 30 from the transformer 28 is limited in amplitude by small signal diodes 31-36, and is low pass filtered by resistor and capacitor pairs 38, 40 and 42, 44. This limited and filtered signal 46 is applied in a differential manner to the inverting and non-inverting inputs of comparator 48. Switching hysteresis is provided by applying positive feedback from both Q and ^~Q outputs via resistors 50 and 52, respectively. The comparator outputs Q and ^~Q produce gate pulses proportional in width to the zero crossings of the FM IF signal. This gate pulse is applied to one of the inputs on each of the NAND gates 54 and 56. Clock 58 provides a source of high frequency clock pulses which is similarly applied to the other inputs of NAND gates 54 and 56. The resultant output of NAND gates 54 and 56 contain multiple sample clock periods wherein the number of sample clock periods are directly proportional to the width of the gating pulse. Comparator 48 outputs Q and?-? are applied to one input of OR gate 60 and 62 this signal is combinatorially or'd with the READ signal to provide &CLR

= Q * READ function which is subsequently fed to inverter gates 66 and 68 for signal inversion and is then applied to the clear inputs of counters 70 and 72, and counters 74 a 76. The counter clear operation occurs during the RE operation for each counter 70-76 on each alternating ha cycle of the gate pulses produced at Q and ^~Q of comparat 48. The UP counters 70-76 count clock transitions appli to the clock input of the first 4-bit counter stage duri a positive or high level at either Q or ^~Q of comparator 4 Each counter 70-76 alternately counts during each half cyc of the FM signal. Each counter is then cleared during t opposite counters "UP" count period. The count informati of each counter is latched into the corresponding 8-bit lat on the rising edge of the alternate counters "gate pulse" and ^~Q . This allows the data to be latched before t information is cleared from the counter during the next val clear signal. Period information in the form of "cou values" are subsequently read from each counter on alternating basis. Data is available to the data bus duri a valid READ signal from the numerical processor 12 (FI 1), signal processor 12' (FIG. IA) or DAC 12" (FIG. IB). Given the incoming binary pulse-count data provided the counters 22 and 24, the system shown in the embodime of FIG. IB, for example, provides complete demodulation an FM IF signal, in the sense that a voltage proportional a commensurate with the binary pulse-count data is output the DAC 12.

Low-pass filtering can then be used to reduce inba noise, and smooth out residual quantization jitter. T filters used include, but are not limited to, direct fo (DF) , finite impulse response (FIR) , and infinite impul response (IIR) filter realizations. The direct form filte for example, has the following form.

j

A(x) - Σ A(x - k) + b_k N(x - k) k=l k=0 where, A(x) , the filter output, is the result of the recursion step where previous outputs, A(x-k) , are convolved with IIR coefficients a_k, and previous inputs are convolved with FIR coefficients b--. For example, a low order (e.g. 5-10 zeros and poles) IIR

Butterworth filter can be applied to a signal template, in real time, just prior to signal output to the DAC stage 12. A Butterworth filtering technique was chosen due to its exceptionally flat passband response, and approaches a true "brick-wall" type filter in its digital realization.

Additionally, it may be desirable to weight and scale the count values prior to filtering, and such weighting and scaling can be adequately performed using simple analog circuitry, as is well-known in the art. The numerical processor 12 of Fig. 1 will now be discussed. The advent of digital signal processing (DSP) chips has allowed the development of real-time DSP applications. Prior to DSP-specific chipsets, the operating speeds of conventional Von Neumann processors prohibited their application to real-time digital signal processing. Current DSP microprocessors are typically based on the "Harvard Architecture". The primary difference between the Harvard-type and the Von Neumann-type architectures is the separate data and instruction buses within the Harvard Architecture chip. This bus scheme allows for simultaneous data and program memory fetches.

Another important innovation in DSP chip technology is the so-termed single cycle instruction set. This capability allows each instruction in a DSP chip to be executed in one clock cycle, brought about by implementing the instruction sets of DSP chips as part of the architecture itself, rather than in microcode, as is common in most non-DSP processors.

To further enhance the operating speed of DSP processors, chip manufacturers added parallelism and pipelining functions to the Harvard Architecture devices.

Parallelism refers to the capability of a signal processing device to carry out more than one operation at a time. F example, data may be read from the parallel data bus via parallel input/output port, while the address of the incomi data is being placed into the shifter stack and the ne program instruction is concurrently being fetched from t instruction stack. Conversely, it is also possible transmit previous results from the serial port of t processor to the DAC during data processing steps. excellent "pseudocode" example of parallelism in a D processor is as follows: fetch an instruction; compute t next instruction's address; perform one or two da transfers; update one or two data address pointers; a perform a computation, all within a single cycle.

"Pipelining" refers to a process whereby the result( of a first operation within the processor are immediate available as input(s) to a second operation, without t added requirement that data be moved via a program step. F example, the result of a shifter operation may be direct used as an input to a multiplier accumulator section. this context, pipelining is considered only one level dee Future processors will most likely allow for several leve of pipelining. These innovations have enabled DSP chips process large quantities of data much faster than previous thought possible, making real-time data-processing a realit According to the invention, further computation efficiencies are obtained by choosing a computational optimal order for executing mathematically equivale statements. Although the order of operations typically do not matter in arithmetic, it does influence computation speed considerably. For example,

(Add, then multiply) = (Multiply, then add) (A + B) * (C + D) = AC + AD + BC + BD Both sides are identical mathematically, but the le half takes two "adds" and one "multiply", while the rig half takes three "adds" and four "multiplies", providing significant difference in computational overhead. The instructions executed by the numerical processor 12 exploit all of the above-mentioned efficiencies to perform computations in an extremely efficient manner, thereby providing extra time for performing additional instructions. Furthermore, any new means for enhancing performance of the numerical processor 12 that may become available in the future will serve to enhance the performance of the apparatus and method of the invention. Moreover, the apparatus and method of the invention is not limited to any particular numerical processor, or any DSP in particular.

The numerical processor 12 of Fig. 1 receives zero- crossing interval information from the counters 22, 24, and performs a differentiation process, to be described below, on successive interval values to recover modulating amplitude information. Since there are two zero-crossing events in a sinusoidal wave, an instantaneous frequency value F(t) can be recovered by taking the reciprocal of twice the period T(t) between successive zero-crossing events. Thus,

F(t) = 1 / (2 * T(t)). (1)

The zero-crossing periods T(t) are given (within the limits of quantization) by:

T(t) = N(t) * T_clock, (2)

where-"N(t)" is the number of "counts", i.e., clock pulses, within a given zero-crossing period, and "T_cl0-_k" is the period of the clock, i.e., the time between clock pulses. Quantization errors e(t) exist due to ambiguities in the pulse counting process. During a clock period, an actual zero-crossing could take place at any point in time from: T = (N - 0.5) * T_cIo-k to T = (N + 0.5) * T_cIock, giving an uncertainty e(t) in the knowledge of the exact moment of a zero-crossing of: e (t) = ±0 . 5 * T_cl∞k . (

The accuracy of the digitization process is therefo dependent upon the frequency of the clock. As the clo speed '^•F_c-_c-._k" increases, the uncertainty in a given measureme decreases, since F_clocl. = l/T_-lock. A typical system clock spe is 50 Megahertz, which results in an uncertainty e ±10 nanoseconds, as calculated from equation (3) . The me error in e(t) is zero, since the ideal quantization err probability density function is symmetric. Also, t standard deviation is approximately 0.29*T_clock, which is al the rms value of the uncertainty e(t) . The rms value of e( can also be considered as a measure of signal noise due digitization. For example, if the maximum period betwe zero-crossings is quantized using 256 quantizing increment the peak signal-to-rms-noise ratio would be 0.4%, or abo 48 db.

The actual number of quantizing increments, i.e., clo pulses that fit within a zero-crossing period is bounded the deviation frequency (DF) bandwidth. The width of zero-crossing period is simply the clock frequency divid by twice the quantity "IF frequency ± the DF frequency Thus, the maximum number of clock pulses in a digitiz sample is given by:

N_{m x} = C 2T_cl0Ck ( IF + DF^) ] -- . (

while the minimum number of clock pulses in a digitiz sample is given by:

_mi_n = [ 2T_clock ( IF + DF.-- ] ^■' . (

To determine the resolution width after digitizatio subtract equation (5) from equation (4) to obtain:

DN = F_clock * DF / (IF² - DF²) . ( The actual count N is represented as a binary coded decimal (BCD) in the counter stage 70-76, and is transferred through the latches 80-82, and into the numerical processor 12, with "n-bit" resolution. The actual sample resolution n, valid to within the 1-bit error term e(t) , is given by:

n = Log₁₀(DN) / Log₁₀(2) = 3.32 Log₁₀(DN) (7)

and the fullscale sinewave RMS signal to RMS noise ratio in Nyquist bandwidth is given by:

SNR = 6.02n + 1.76 dB = 20 Log₁₀(DN) + 1.76 dB. (8)

Count values provided to the numerical processor 12 are scaled and weighted, as explained below, to exploit the full n-bit range of the numerical processor. Next, one or more of the following processes is used: a "windowing" process for pulse averaging, using a Rectangular Window, or a Hamming Window, for example, and for providing data filtering and a preliminary treatment of digital quantization errors; and low-pass filtering, for limiting the data to a specific frequency band, and for removing noise, thereby improving the signal-to-noise ratio. Data thus processed by the numerical processor 12 is subsequently provided to a digital-to-analog converter (DAC) .

Scaling and weighting of count values is governed by the equation:

A(i) = a * N(i) + b (9)

where a and b are scaling and weighting constants, respectively, N(i) represents the "i"th time-period count value between zero-crossings "i-1" and "i", and A(i) is the "i"th scaled and weighted count value. Given the incoming binary pulse-count data N(i) provided by the counters 22 and 24, the system implements equation (9) to provide complete demodulation of an FM IF signal, in the sense that a volta proportional and commensurate with the "number" A(i) output to the DAC.

The constants a and b, are found using the full-sca positive (FSP) , and full-scale negative (FSN) DSP process values. The FSP and FSN values are determined by t "full-range" n-bit value, e.g., 65,536 for 16 bits, such th FSP is equal to (Full-Range)/2-1, and FSN is equal -(Full-Range) /2, expressed in a two's complement bina representation. As such, a and b are given by:

FSP = a * Nmin + b (1 and

FSN = a * Nmax + b, (1 such that a = (FSP - FSN) / (Nmin - Nmax) and (1

b = FSP - [ (FSP - FSN) / (Nmin - Nmax) ] * Nmin. (1

When simple pulse-averaging is used, a so-term rectangular averaging window of width M slides over t scaled and weighted count values A(i) , where M is the numb of count values within the averaging window, and the M cou values are averaged together to provide an average scaled a weighted count value A(j) over the last M count values. value A(j) can be generated for each A(i) by advancing t window by one count value to A(i-t-l) , or a value A(j) can generated for every nth count value A(i+n) to reduce the da rate, thereby allowing more time for other operations. a preferred embodiment, M=2 and n=2, so the window includ two count values and advances by two count values at a tim thereby halving the data rate. Other combinations of n a M can also be used. The average scaled and weighted cou value A(j) is given by: A(j ) = (1 / M) * SUM(A(i) ) , (9b)

where A(i) is given by equation (9) , i == h, h-1, ... h-(M - 1) , and h is the index i of the current count value A(i) . Window functions such as the simple window averaging just described are used to pre-condition incoming data. Other typical window functions are, for example, of the Hamming or Von Hann type, that generally serve to deemphasize the effect of certain coefficients within a sliding window, while augment the effect of others within the window. The Hamming window coefficients w_H(n) are of form:

W_H(m) = 0.54 ( 1 - 0.8519 cos(2 pi * m / (M - 1)))/14)

while the Von Hann window coefficients w_v(n) are given by:

w_v(m) = 0.50 ( 1 - cos(2 pi * / (M - 1)) ), (15)

with m = 1, ... M, and M = the number of count values A(x) in the window. For example, whenM=3, w_H(m)=[a, b, c], where a, b, and c are constants computed according to equation (14) . The window can advance by one or more count values, and upon each advance, the inner product of the array w_H(m) and the array of values within the window is computed to yield a scalar quantity. To reduce the data rate, the window can advance by more than one value each time it advances. The Hamming or Von Hann window function can be used in addition to, or in place of, the simple rectangular window averaging scheme discussed above. Next, the method of the invention employs low-pass filtering to reduce inband noise, and smooth out residual quantization jitter. As mentioned above, the filters used include, but are not limited to, direct form (DF) , finite impulse response (FIR) , and infinite impulse response (IIR) filter realizations. The direct form filter, for example, has the following form, A (x) = b_k N (x - k) (1 k=l k=0

where, A(x) , the filter output, is the result of t recursion step where previous outputs, A(x - k) , a convolved with IIR coefficients a_k, and previous inputs a convolved with FIR coefficients t^.

In the current embodiment, a low order (e.g. 5-10 zer and poles) IIR Butterworth filter is applied to a sign template, in real time, just prior to signal output to t

DAC stage. A Butterworth filtering technique was chosen d to its exceptionally flat passband response, and approach a true "brick-wall" type filter in its digital realizatio

In summary, Fig. 3 illustrates the sequence of process used to transform the sequence of count values provided the discriminator 10 of Fig. 1 to the numerical processor 1

The values N are first weighted and scaled (90) , and then a window averaged (92) , thereby reducing the rate of da passed to subsequent calculations. In a preferr embodiment, a window transformation technique, such as

Hamming or Von Hann transformation (94) , is then used. T data is then filtered (96) by a low-pass filter, just pri to being introduced to the DAC step (98) .

It may be desirable to weight and scale the count valu prior to filtering, and such weighting and scaling can adequately performed using simple analog circuitry, as well-known in the art.

The clock rate for measuring zero-crossing intervals preferably a rate of generally at least 8 times the Nyqui rate of the highest audio frequencies encountered so as minimize distortion.

The zero-crossing periods T(t) of equation (1) are giv within the limits of count sample quantization uncertaint i.e., one clock period (e,g., about 100 nanoseconds), equation (2) . To provide further improved performance in the presence of noise in the signal to be demodulated, a so-termed "bounds-checking" routine is used. In a demodulation apparatus of the invention, noise manifests itself as count anomalies. These count anomalies occur throughout the full range of count values, including "In-Band Noise", which falls within the range of N^ to H,^.

To avoid problems introduced by this noise, the numerical processor implements the bounds-checking routine, which routine parses through incoming zero-crossing count data, and identifies data which falls outside of the range N,-,--. to -_a--_; by testing for data below N_min and testing for data above N_^. Should a value fall outside of the range of N^ to N_m_₀., it is assigned a value at a corresponding extremum point, i.e., the FSN or FSP point. For example, the bounds- checking routine is shown in Fig. 3C as step 126, occurring after the step of period measurement 124. Steps 128-136 illustrate subsequent steps in a polynomial curve-fitting method, described below. In the linear first order estimation of equation (9) , digitized zero-crossing samples are input to the numerical processor, e.g. , a digital signal processor (DSP) , where they are subjected to "count scaling" to exploit the full n-bit range of the DSP. Equation (9) , in conjunction with incoming binary count data, represents a complete signal demodulation estimation process.

Fig. 4 is a plot of equation (9) , where a=-780 and b=162,240, which are the parameters when F_clo-k=40 Mhz, IF=100

Khz, DF_rωx=20 Khz, FSP=-FSN=32760, and thus N_max=250 and N_πώ-=166. Also, at N(i)=208, A(i)=0, where N(i)=208 is referred to as the "linear" IF.

Equation (9) is the equation of a straight line, and equation (1) is the equation of a reciprocal function. Over a very short region, a straight line can sufficiently model a curve. However, the range of numbers encompassed here is large, suggesting that a "linear fit" might perform well only at the endpoints of the range of the fit, i.e., between and N_^, and poorly in the middle of this range, i.e., at linear IF. This can be tested by examining the fit at value of A(i) where N(i) corresponds to 100 Khz, the IF. the IF, DF = 0, and since the width of a zero-crossing per is simply the clock frequency divided by twice the quant "IF frequency + the DF frequency", N=200. However, solving equation (9) with N = 200, A(i)=6240, which value A(i) represents an incorrect response with about 10% err This error is introduced mostly due to estimation of signal about the Linear IF value.

A polynomial curve-fitting method will now be discus which directly addres'-as and solves the aforementio problem of linear fit inconsistencies. This approach co very close to the behavior associated with a function of form given by equation (1) .

The FSP Value, FSN Value, and an Intermediate Value used to generate a second-order nonlinear equation w coefficients that make the nonlinear equation "closest" the expression of equation (1) in a "Least Squares" sen The coefficients for estimating data in the range N_min to can be found using a least-squares-fit process, such as employing the Vandermonde matrix, as can be found in the MATHLAB User's Guide, by the MATHWORKS, October 1990. polynomial solution is of form

A(N) = c₀ + c-N + c₂N², (

where c₀, c,, and c₂ are the zeroth, first, and second or coefficients respectively, and N is an incoming zero-cross count value. As an example, data from the previous section's examp with FSP = 32760 (N^ = 166) , FSN = .32760 (N,^ = 250) , Intermediate Value equal to zero (0) , was used as input the second order fitting routine. Fig. 4 shows the sec order solution in the range of zero-crossing count val from 166 to 250, with the data curve corresponding to the linear equation overlaid as a reference. Thus, the difference between the linear and the nonlinear approaches is significant. In Fig. 4 it is of particular interest to note that the curve marked "2nd Order Fit" not only ends perfectly at the count extrema, but also passes directly through the count midpoint, N(i) , since this point was used to obtain the curve. Several other random points were evaluated off-line for accuracy, and were observed to fall within 1% of the expected values. In addition, the accuracy of the second- order estimation method was also borne out in real-time testing using a Total Harmonic Distortion (THD) analyzer.

To validate the error associated with a linear fit to the data, a data set was generated which contains the difference between the linear and the second order fit. The results are shown in Fig. 5, wherein it can be determined that almost 75% of the estimated values from the linear fit will incur at least 5% error. In another preferred embodiment, a so-termed "reciprocal fit count scaling" method is employed that provides better performance than the linear count scaling method, and improved performance with respect to the least-squares-fit nonlinear count scaling method. Such improved performance provides an estimated signal with significantly higher scaling accuracy, lower total harmonic distortion, and an excellent signal-to-noise ratio. In fact, the reciprocal count scaling method provides an exact analytic solution, and guarantees the most accurate and optimal results attainable from a system of this type.

Recall that the average instantaneous frequency F(t) of a sinusoidal temporally modulated signal can be represented by the reciprocal of twice the period T(t) measured between zero-crossings, where F(t) = 1 / (2 * T(t)), as in equation (1). The value of the average instantaneous frequency F is bounded by the deviation frequency extrema DF-_^ and DF where OF_Bύa is equal to -DF-_^. As previously stated, number of counts N(t) within a period T(t) is direc proportional to the reciprocal of the product of the sys clock period T_-lock with the instantaneous deviation freque "IF + DF(t)". Thus,

N(t) = [ 2T_cl0Ck (IF + DF(t) ) ]--. (

Therefore, the maximum possible number of clock counts wit a period T(t) is given by

N_m = [ 2T_cl∞k (IF + DF^) ]-'.

Likewise, the minimum possible number of clock counts wit a period T(t) is given by

N_min = [ 2T_clock (IF + DF^) ] ^"' .

Count values N(t) are provided to the numeri processor 12 that scales and weights the count values N according to a set of scaling and weighting coefficients provide scaled and weighted values. To obtain the scal and weighting coefficients, the numerical processor empl its full "n-bit" range, and may apply a linear fit meth a least squares fit method, or a reciprocal fit (RF) meth The RF method of count-scaling is generally expres by the equation

A(i) = a/N(i) + b (

In equation (19) , the inverse slope parameter a and y-intercept parameter b represent scaling and weight coefficients. N(i) represents the "i"th time-period sam count value between zero-crossings "i-1" and "i", and A represents the "i"th scaled and weighted count value, with maximum/minimum extrema of +2¹⁵.

Equation (19) , in conjunction with the incoming binary count data and a precalculated knowledge of the count extrema, represents a complete signal demodulation method. One need only to calculate the values of a and b.

The parameters a and b are found using full-scale positive (FSP) and full-scale negative (FSN) numerical processor values. The FSP and FSN values of the numerical processor are determined by the "full-range" n-bit value, i.e., 65536 for 16 bits, where FSP is equal to "full range/2 - 1", and FSN is equal to "-full range/2". Thus, a and b are evaluated by

FSP = a / Nmin + b (20) and

FSN = a / Nmax + b (21) such that a = 2*[(N_mϊn * N^) / (N-^ - N-_^)] * FSP (22) and b = -[(N- . + N-₃- / * FSP (23)

Using these expressions for a and b in equation (19) , A(i) can be expressed as

A(i) = [FSP/(N^- _^ ] * ( (2*N_Bώl*N_nιlx/N_i) - (N^+N-^+N-_^)! . (24)

With reference to Fig. 6, a comparison of the reciprocal fit scaling method and the least squares fit nonlinear scaling method is provided by plotting a scaled and fitted output value versus the integer count input value for F_clock -= 10 Mhz, IF = 25 Khz, DF-^ = 5 Khz, and FSP = -FSN = 32760. ^N _m» ⁼ 250 , and N^ = 166. From equations (22) and (23), a = 390*83000, and b = 390*416. By using these results in equation (24) , the expression for A(i) in the case of the reciprocal fit is given by A ( i) = 390 * [ ( 83000/N ( i) ) - 416 ] , (

As illustrated in Fig. 6, the least squares nonlinear scaling method provides a very high level of sig resolution, making the theoretically predicted differe between the least squares method and the exact reciprocal scaling method apparently inconsequential. In particul the average theoretical error associated with the le squares approximation as compared to the reciprocal scaling method is 0.20%, i.e., 0.02 dB difference, while maximum theoretical error associated with any given d point is just 1.0%, i.e., 0.1 dB difference. While th theoretical results might lead one's intuition to assume t the two methods are effectively equivalent, in practice, reciprocal fit scaling method provides an improvement signal-to-noise ratio of approximately 1 dB. Thus, since reciprocal fit scaling method does not incur implementation penalty, the optimal choice is the recipro fit scaling method.

Figs. 3A and 3B show how the reciprocal fit steps and 112, respectively, occur in two exemplary embodiments the method of the invention. Steps 100, 104-108, 110,

114-122 have been discussed above in the context of Fig.

Other modifications and implementations will occur those skilled in the art without departing from the spi and the scope of the invention as claimed. Accordingly, above description is not intended to limit the invent except as indicated in the following claims.

Claims

What is claimed is:

1. A digital demodulator for efficient demodulation oftemporally modulated signals, the demodulator comprising: a zero-crossing event detector, responsive to a temporally modulated signal, that serves to detect zero- crossing events of said temporally modulated signal, and thereby provide zero-crossing event information; a period measurer, connected to said zero-crossing detector, that serves to receive said zero-crossing event information and measure the period between said zero-crossing events, thereby providing a sequence of period measurement values; and a signal processor, connected to said period measurer, that serves to convert said sequence of period measurement values into a demodulated signal.

2. The digital demodulator of claim 1, wherein said period measurer measures the period between said zero-crossing events at a resolution corresponding to a clock rate of generally at least 8 times the Nyquist rate of a maximum encountered frequency of said temporally modulated signal.

3. The digital demodulator of claim 1 wherein said signal processor includes: a digital-to-analog converter that receives said sequence of period measurement values and provides said demodulated signal.

4. The digital demodulator of claim 1 wherein said signal processor includes: a conversion element that receives and transforms s sequence of period measurement values into a transfor digital data stream with a higher signal-to-noise ratio t said sequence of period measurement values; and a digital-to-analog converter that receives s transformed digital data stream and provides said demodula signal.

5. The digital demodulator of claim l wherein said sig processor includes: a digital-to-analog converter that receives s sequence of period measurement values and provides an anal version of said demodulated signal; and an analog filter that receives said analog version said demodulated signal and removes noise from said anal version of said demodulated signal to provide a demodula signal with a higher signal-to-noise ratio than said anal version of said demodulated signal.

6. A method for demodulating a temporally modulated signa the method comprising the steps of: measuring the period between zero-crossings of intermediate signal of a modulated signal to provide sequence of period values; and transforming said sequence of period values to provi a demodulated signal.

7. The method of claim 6 wherein the step of transformi includes the steps of: filtering said sequence of period values to provide sequence of filtered values; and converting said sequence of filtered values into analog signal.

8. The method of claim 6 wherein the step of transform includes the steps of: converting said sequence of period values into an analog signal; and filtering said analog signal to provide a demodulated signal with a higher signal-to-noise ratio than said analog signal.

9. The method of claim 6 wherein the step of transforming includes the step of: for each period value that exceeds a maximum period value, replacing said period value with said maximum period value, and for each period value that does not exceed a minimum period value, replacing said period value with said minimum period value.

10. A method for demodulating a temporally modulated signal, the method comprising the steps of: measuring the period between zero-crossings of an intermediate signal of a modulated signal to provide a sequence of period values; obtaining a sequence of reciprocal values by computing the reciprocal of each period value in said sequence of period values; scaling and weighting each reciprocal value of said sequence of reciprocal values to provide a sequence of scaled and weighted reciprocal values; filtering said sequence of scaled and weighted reciprocal values to provide a sequence of filtered values; and converting said sequence of filtered values into an analog signal.

11. A method for demodulating a temporally modulated signal, the method comprising the steps of: measuring the period between zero-crossings of an intermediate signal of a modulated signal to provide a sequence of period values; obtaining a sequence of reciprocal values by comput the reciprocal of each period value in said sequence period values; scaling and weighting said sequence of reciprocal val to provide a sequence of scaled and weighted recipro values; averaging the scaled and weighted reciprocal val within a sliding window to provide a sequence of win averaged values; executing a Von Hann window function upon the seque of window averaged values to provide a sequence of Von H values; filtering said sequence of Von Hann values to prov a sequence of filtered values; and converting said sequence of filtered values into analog signal.

12. A method for demodulating a temporally modulated sign the method comprising the steps of: measuring the period between zero-crossings of intermediate signal of a modulated signal to provide sequence of period values; obtaining a sequence of reciprocal values by comput the reciprocal of each period value in said sequence period values; scaling and weighting said sequence of reciprocal val to provide a sequence of scaled and weighted recipro values; averaging the scaled and weighted reciprocal val within a sliding window to provide a sequence of win averaged values; executing a Hamming window function upon the seque of window averaged values to provide a sequence of Hamm values; filtering said sequence of Hamming values to provid sequence of filtered values; and converting said sequence of filtered values into an analog signal.

13. A method for demodulating a temporally modulated signal, the method comprising the steps of: measuring the period between zero-crossings of an intermediate signal of a modulated signal to provide a sequence of period values; squaring and scaling each period value of said sequence of period values to provide a sequence of squared and scaled values; scaling and weighting said sequence of period values to provide a sequence of scaled and weighted values; augmenting said sequence of scaled and weighted values by adding a squared and scaled value to each corresponding scaled and weighted value to provide an sequence of augmented values; filtering said sequence of augmented values to provide a sequence of filtered values; and converting said sequence of filtered values into an analog signal.

14. The method of claim 10, 11, 12, or 13 further including the step of: after the step of measuring the periods between zero-crossings, for each period value that exceeds a maximum period value, replacing said period value with said maximum period value, and for each period value that does not exceed a minimum period value, replacing said period value with said minimum period value.

15. A digital demodulator for efficient demodulation of temporally modulated signals, the demodulator comprising: a zero-crossing event detector, responsive to a temporally modulated signal, that serves to detect zero- crossing events of said temporally modulated signal, thereby provide zero-crossing event information; a period measurer, connected to said zero-cross detector, that serves to receive said zero-crossing ev information and measure the period between said zero-cross events, thereby providing a sequence of period measurem values; and a numerical processor, connected to said per measurer, that serves to convert said sequence of per measurement values into a demodulated signal with a h signal-to-noise ratio.

16. The digital demodulator of claim 15 wherein s numerical processor includes: a digital data stream generator that receives converts said sequence of period measurement values int digital data stream representative of said demodula signal; and an digital-to-analog converter that receives s digital data stream and provides said demodulated signal

17. The digital demodulator of claim 15 wherein s numerical processor converts said sequence of per measurement values into said demodulated signal in real ti

18. The digital demodulator of claim 15 wherein said ze crossing detector provides zero-crossing event informat as a sequence of square waves with zero-crossi commensurate with the zero-crossings of said tempora modulated signal.

19. The digital demodulator of claim of claim 15 wher said period measurer includes: a clock; a counter; and a clock pulse gate, connected to said clock, said counter, and said zero-crossing detector, that permits clock pulses to propagate from said clock to said counter in response to zero-crossing event information provided by said zero-crossing detector.

20. The digital demodulator of claim 19 further including: a second clock pulse gate, connected to said clock and said zero-crossing detector; and a second counter, connected to said second clock pulse gate.

21. A method for demodulating a temporally modulated signal, the method comprising the steps of: measuring the period between zero-crossings of an intermediate signal of a modulated signal to provide a sequence of period values; and numerically processing said sequence of period values to provide a demodulated signal.

22. The method of claim 21 wherein the step of numerically processing includes the steps of: weighting and scaling said sequence of period values to provide a sequence of weighted and scaled values; filtering said sequence of weighted and scaled values to provide a sequence of filtered values; and converting said sequence of filtered values into an analog signal.

23. The method of claim 22 further including the step of: after the step of weighting and scaling, and prior to the step of filtering, averaging the weighted and scaled values within a sliding window to provide a sequence of averaged values to be filtered. 24. The method of claim 23 wherein the sliding win includes two values and is advanced two values at a time

25. The method of claim 22 further including the step o after the step of weighting and scaling, and prior the step of filtering, executing a Hamming window funct upon the sequence of weighted and scaled values to prov a sequence of values to be filtered.

26. The method of claim 22 further including the step o after the step of weighting and scaling, and prior the step of filtering, executing a Von Hann window funct upon the sequence of weighted and scaled values to prov a sequence of values to be filtered.

27. The method of claim 22 further including the steps after the step of weighting and scaling, averaging weighted and scaled values within a sliding window to prov a sequence of averaged values; and prior to the step of filtering, executing a Hamm window function upon the sequence of weighted and sca values to provide a sequence of values to be filtered.

28. The method of claim 21 wherein the step of numerica processing includes the steps of: weighting and scaling said sequence of period values provide a sequence of weighted and scaled values; averaging the weighted and scaled values within sliding window to provide a sequence of window avera values; executing a Von Hann window function upon the seque of window averaged values to provide a sequence of Von H values; filtering said sequence of Von Hann values to prov a sequence of filtered values; and converting said sequence of filtered values into an analog signal.

29. The method of claim 21 wherein the step of numerically processing includes the steps of: weighting and scaling said sequence of period values to provide a sequence of weighted and scaled values; averaging the weighted and scaled values within a sliding window to provide a sequence of window averaged values; executing a Hamming window function upon the sequence of window averaged values to provide a sequence of Von Hann values; filtering said sequence of Hamming values to provide a sequence of filtered values; and converting said sequence of filtered values into an analog signal.

30. A digital demodulator for efficient demodulation of temporally modulated signals, the demodulator comprising: a zero-crossing event detector, responsive to a temporally modulated signal, that serves to detect zero- crossing events of said temporally modulated signal, and thereby provide zero-crossing event information; and a period measurer, connected to said zero-crossing detector, that serves to receive said zero-crossing event information andmeasure the period between said zero-crossing events, thereby providing a sequence of period measurement values that represents a demodulated signal.

31. The digital demodulator of claim 30, further including: a digital-to-analog converter that receives said sequence of period measurement values and provides an analog form of said demodulated signal. 32. The digital demodulator of claim 30 wherein said zer crossing detector provides zero-crossing event informati as a sequence of square waves with zero-crossin commensurate with the zero-crossings of said temporal modulated signal.

33. The digital demodulator of claim of claim 30 where said period measurer includes: a clock; a counter; and a clock pulse gate, connected to said clock, sa counter, and said zero-crossing detector, that permits clo pulses to propagate from said clock to said counter response to zero-crossing event information provided by sa zero-crossing detector.

34. The digital demodulator of claim 33 further includin a second clock pulse gate, connected to said clock a said zero-crossing detector; and a second counter, connected to said second clock pul gate.

35. A method for demodulating a temporally modulated signa the method comprising the steps of: measuring the period between zero-crossings of intermediate signal of a modulated signal to provide sequence of period values that represents a demodulat signal. AMENDED CLAIMS

[received by the International Bureau on 25 March 1993 (25.03.93) ; original claims 1 and 13 amended; remaining claims unchanged (2 pages)]

1. A digital demodulator for efficient demodulation of temporally modulated signals, the demodulator comprising: a zero-crossing event detector, responsive to a temporally modulated signal, that serves to detect zero- crossing events of said temporally modulated signal, and thereby provide zero-crossing event information; a period measurer, connected to said zero-crossing detector, that serves to receive said zero-crossing event information and measure the period between said zero-crossing events, thereby providing a sequence of period measurement values ; and a signal processor, connected to said period measurer, that serves to convert said sequence of period measurement values into a demodulated signal.

4. The digital demodulator of claim 1 wherein said signal processor includes: converting said sequence of filtered values into a analog signal.

13. A method for demodulating a temporally modulated signal the method comprising the steps of: measuring the period between zero-crossings of a intermediate signal of a modulated signal to provide sequence of period values; squaring and scaling each period value of said sequenc of period values to provide a sequence of squared and scale values; scaling and weighting said sequence of period values t provide a sequence of scaled and weighted values; augmenting said sequence of scaled and weighted value by adding a squared and scaled value to each correspondin scaled and weighted value to provide a sequence of augmente values; filtering said sequence of augmented values to provid a sequence of filtered values; and converting said sequence of filtered values into a analog signal.

14. The method of claim 10, 11, 12, or 13 further includin the step of: after the step of measuring the periods betwee zero-crossings, for each period value that exceeds a maximu period value, replacing said period value with said maximu period value, and for each period value that does not excee a minimum period value, replacing said period value with sai minimum period value.

15. A digital demodulator for efficient demodulation o temporally modulated signals, the demodulator comprising: a zero-crossing event detector, responsive to temporally modulated signal, that serves to detect zero