KR101113902B1 - Apparatus and Method for Receiving Near Wireless Signal Using Digital Radio Frequency Processing and Zero Crossing - Google Patents

Abstract

The present invention relates to a short-range wireless signal receiving apparatus and method using a digital high-frequency processing technology and a zero-crossing technique. Thereafter, the detected zero-crossing signal is converted into a digital signal, and the converted digital signal is converted into a processable short range wireless signal. According to the present invention, it is possible to reduce the hardware size of the short range wireless signal receiver and reduce the power consumption of the short range wireless signal receiver by using a digital high frequency processing technique and a zero crossing technique.

RF signal, zero crossing signal, IF signal, short range wireless signal

Description

Apparatus and Method for Receiving Near Wireless Signal Using Digital Radio Frequency Processing and Zero Crossing}

The present invention relates to a short range wireless signal reception technology using digital high frequency processing technology and zero crossing technology, and more particularly, to detect an intermediate frequency signal from a high frequency signal received from the outside and convert the detected intermediate frequency signal into a digital signal. Afterwards, the present invention relates to a digital high frequency processing technique for converting a digital signal into a short range wireless signal that can be processed by a receiving apparatus, and a short range wireless signal receiving apparatus and method using a zero crossing technique.

Since a conventional RF (Radio Frequency) receiver uses a structure of a heterodyne and a homodyne, an imaginary signal is generated. Therefore, the RF receiver requires two paths, and a plurality of AD converters for converting analog signals into digital signals are required, and each requires 8 bits of resolution.

In the case of heterodyne structure, when directly converting a high frequency signal (hereinafter referred to as an RF signal) to a low frequency signal and lowering it to a low frequency signal, the number of components decreases, thus simplifying the structure of a receiver, but a big disadvantage of DC offset. This happens.

In the case of the homodyne structure, when the RF signal is divided into several stages and lowered to an intermediate frequency signal (hereinafter, referred to as an IF signal) and lowered to a baseband signal, stability is improved than the direct modulation method, but the volume of the receiver is increased. The disadvantage is that power consumption is increased. In addition, when the AD converter is used, a problem arises in that a high resolution is required.

As such, the use of multiple components in the construction of the receiver increases in volume and increases chip manufacturing costs.

However, in recent years, since most small devices including portable terminals have been developed in the direction of miniaturization and low power design, it is possible to reduce the volume of the receiving device by minimizing the parts of the receiving device implemented in the small devices and to perform low power. The need for technology is emerging.

In order to solve this problem, an object of the present invention is to detect a single bit of an intermediate frequency signal from a high frequency signal received from the outside, and convert the intermediate frequency signal into a short range wireless signal to process the converted short range wireless signal. The present invention provides a short range wireless signal receiving apparatus and method using a high frequency processing technique and a zero crossing technique.

In order to achieve the above object, the short-range wireless signal receiving apparatus using the digital high frequency processing technique and the zero crossing technique according to the present invention receives a high frequency signal from the outside, the first specific signal factor, the second specific to the received high frequency signal A digital high frequency processor for sequentially removing a signal factor, a third specific signal factor, and converting the signal into an intermediate frequency signal; when the detected intermediate frequency signal is received, a zero crossing signal is detected from the intermediate frequency signal, and the detected zero crossing signal It characterized in that it comprises a zero-cross signal detection unit for converting to a digital signal.

The zero-cross signal detection unit may be any one of a selection zero-cross signal detection unit and an average zero-cross signal detection unit.

(여기서,

는 중간 주파수신호이고,

는 수신된 고주파 신호, M,N,O는 제1,2,3 특정 신호 인자임)인 것을 특징으로 한다.In addition, the intermediate frequency signal is characterized in that a single bit.
In addition, the intermediate frequency signal is

(here,

Is an intermediate frequency signal,

Is a received high frequency signal, M, N, O is a first, second, third specific signal factor).

The zero-cross signal detection unit detects the time difference between the domains of the plurality of intermediate frequency signals when the domains of the plurality of intermediate frequency signals are received from the digital high frequency processor to detect the zero-cross signal and detects the detected zeros. And converting the cross signal into a digital signal.

delete

delete

The short range wireless signal receiving apparatus may further include a signal processing unit outputting the digital signal output from the zero-cross signal detection unit to a physical layer protocol data unit.

In addition, the short-range wireless signal reception method using the digital high-frequency processing technology and the zero crossing technology according to the present invention is the first specific signal factor, the second specific signal factor, the third specific signal from the high-frequency signal received from the near field wireless signal receiver Sequentially removing signal factors, converting the high frequency signal into an intermediate frequency signal, and the short range wireless signal receiver detects a zero crossing signal from the intermediate frequency signal, and converts the detected zero crossing signal into a digital signal. Characterized in that it comprises a step.

As described above, the present invention detects a single bit of an intermediate frequency signal from a high frequency signal received from the outside, converts the intermediate frequency signal into a short range wireless signal, and processes the converted short range wireless signal to thereby obtain a hardware size of the short range wireless signal receiver. And it is effective to reduce the power consumption of the short-range wireless signal receiver.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention belongs and are not directly related to the present invention are omitted. This is to more clearly communicate without obscure the core of the present invention by omitting unnecessary description.

1 is a block diagram illustrating a schematic configuration of a short range wireless signal receiving apparatus using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a short range wireless signal receiver 100 using a digital high frequency processing technique and a zero crossing technique may include a digital high frequency processor 10 (hereinafter referred to as a digital RF processor) and a zero crossing signal detector 20. Zero Crossing Detector, hereinafter referred to as ZXD), and a signal processor 30.

More specifically, the DRP 10 includes an amplifier 11, a multi-tap direct sampling mixer 12 (hereinafter referred to as MTDSM), and an intermediate frequency processor (13, hereinafter referred to as IF processor). do.

Although not shown, the amplifier 11 includes a low noise transconductance amplifier (LNA) and a transconductance amplifier (TA), which are received from the outside (hereinafter, referred to as RF signals). Amplification). In particular, the LNA amplifies a low noise signal of the RF signal according to an automatic gain control signal (AGC) input from a control unit (not shown) of the receiver 100 to detect transconductance. The TA outputs the impedance generated by amplifying the transconductance provided from the LNA to the MTDSM 12.

The MTDSM 12 detects the front-end stage of the analog signal by removing a specific signal factor from the RF signal of the impedance, and after detecting the intermediate frequency signal (hereinafter referred to as IF signal). We first remove the specific signal factor from the IF signal.

To this end, the MTDSM 12 includes a sampler 12a, an RF filter 12b, and a first IF filter 12c.

The sampler 12a samples the impedance provided from the amplifier 11 and provides the sampled RF signal to the RF filter 12b.

The RF filter 12b is an RF Decimation Filter, which filters the RF signal provided from the sampler 12a and detects and removes m, which is the first specific signal factor, from the filtered RF signal. The RF filter 12b provides the RF signal from which the m factor is removed to the first IF filter 12c.

The first IF filter 12c is an IF Decimation Filter. The first IF filter 12c filters an RF signal provided from the RF filter 12b to detect an IF signal, and detects and removes n, a second specific signal factor, from the IF signal. The first IF filter 12c provides the IF processor 13 with the IF signal from which the n factor is removed.

The IF processor 13 detects a domain of the IF signal.

To this end, the IF processor 13 includes an IFA 13a and a second IF filter 13b.

The IFA 13a amplifies the IF signal provided from the first IF filter 12c and provides it to the second IF filter 13b.

The second IF filter 13b is an IF Decimation Filter, which filters the IF signal provided by the IFA 13a and detects and removes a third specific signal factor o from the filtered IF signal to back-end stage of the analog signal. ).

The second IF filter 13b detects the domain of the IF signal by using the start end of the analog signal detected by the RF filter 12b and the end of the analog signal detected by the second IF filter 13b. In this case, it is preferable that the IF signal is a single bit.

The ZXD 20 detects a zero crossing signal from a domain of an IF signal which is a single bit provided from the IF processing unit 13, and converts the detected zero crossing signal into a digital signal. In addition, in the present invention, the ZXD 20 is described as Selecting ZXD, but is not necessarily limited thereto, and may be converted and applied to Averaging ZXD.

To this end, the ZXD 20 includes a comparator 21, a parallax meter 22, and a data detector 23.

The comparator 21 is a 1-bit comparator, which receives the domain of the IF signal continuously from the MTDSM 12, and compares the IF signal according to the domain of the IF signal sequentially or repeatedly.

The parallax 22 measures the time difference for the domain of the IF signal compared in the comparator 21.

The data detector 23 detects a single bit of zero-crossing signal from the IF signal according to the measured time difference, and modulates the detected zero-crossing signal into a digital signal.

The chip-to-bit mapping device 31 of the signal processor 30 receives a digital signal from the data detector 23, converts the digital signal into a short range wireless signal, and converts the converted short range wireless signal into a PPDU (physical layer). Output to PHY Protocol Data Unit. In this case, the short range wireless signal may be replaced with a signal of short range wireless communication using a communication method such as Bluetooth, Zigbee, Ultra Wide Band (UWB), Infrared Data Association (IrDA), or the like.

As described above, the present invention configures both the RF signal and the IF signal in a single bit, and the AD converter also has a structure of converting a 1-bit comparator using ZXD technology, rather than using a conventional 8-bit resolution. . Through this, the hardware size of the short range wireless signal receiver 100 may be reduced, and power consumption of the short range wireless signal receiver 100 may be reduced.

2 is a flowchart illustrating a method for receiving a short range wireless signal using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

1 and 2, when the amplifier 11 of the DRP 10 receives the RF signal from the outside in step S41, the LNA (not shown) included in the amplifier 11 is controlled by the controller (not shown) in step S42. The transconductance is detected by amplifying a low noise signal of an RF signal input from the outside according to an automatic gain control signal (AGC). Thereafter, in step S43, the TA included in the amplifier 11 outputs the impedance generated by amplifying the transconductance detected by the LNA to the MTDSM 12.

In step S44, the sampler 12a of the MTDSM 12 samples the impedance provided from the amplifier 11 and provides the sampled RF signal to the RF filter 12b. The RF filter 12b is an RF Decimation Filter, which filters the RF signal provided from the sampler 12a and detects and removes m, which is the first specific signal factor, from the filtered RF signal. The RF filter 12b removes the m factor to detect the start of the analog signal, and provides the RF signal from which the m factor is removed to the first IF filter 12c.

Thereafter, in step S45, the first IF filter 12c, which is the IF Decimation Filter, detects the IF signal by filtering the RF signal provided from the RF filter 12b, and detects and removes n, the second specific signal factor, from the IF signal. . The first IF filter 12c provides the IF processor 13 with the IF signal from which the n factor is removed.

In step S46, the IFA 13a amplifies the IF signal provided from the first IF filter 12c to provide it to the second IF filter 13b, and the second IF filter 13b, which is an IF Decimation Filter, is provided at the IFA 13a. The provided IF signal is filtered and the third specific signal factor o is detected and removed from the filtered IF signal. The second IF filter 13b removes the o factor to detect the termination of the analog signal.

The second IF filter 13b detects the domain of the IF signal by using the start end of the analog signal detected by the RF filter 12b and the end of the analog signal detected by the second IF filter 13b. In this case, it is preferable that the IF signal is a single bit.

Subsequently, in step S47, the comparator 21 of the ZXD 20 receives the domain of the IF signal, which is a single bit, continuously from the IF processor 13, and sequentially or repeatedly compares the IF signal according to the domain of the IF signal. do.

In step S48, the parallax meter 22 of the ZXD 20 measures the time difference between the IF signals compared by the comparator 21.

Thereafter, in step S49, the data detector 23 of the ZXD 20 detects a single bit of zero-crossing signal from the IF signal according to the measured time difference, and in step S50, the data detector 23 detects the detected zero-crossing signal. Modulate with a digital signal.

In operation S51, the chip-to-bit mapping unit 31 of the signal processor 30 receives the digital signal from the data detector 23, converts the received digital signal into a short range wireless signal, and then performs operation S52. The chip-bit mapper 31 outputs the converted short range wireless signal as a PPDU.

3 is a graph illustrating a simulation result of a short range wireless signal receiver using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

Referring to FIG. 3, in order to derive a simulation result, parameters such as RF input frequency, TA transconductivity, MTDSM input impedance, and first to third specific signal factors M, N, O, and IF signals are required.

In order to derive the simulation result of the present invention, the band of the RF input frequency (RF signal) was set to 2,4 GHz, and the TA transcontuctivity was set to 7.5 ms, which is a measured value. In addition, Decimation Factors were set to 8, 6, and 4MHz, respectively, considering the IF signal. At this time, the important thing when considering the IF signal is that the virtual frequency signal does not occur.

When the DRP 10 converts an RF signal into an IF signal by using an equation, it is expressed by Equation 1 below.

f _if = f _rf / M * N * O

In Equation 1, f _rf represents the frequency of the received high frequency signal, f _if represents the frequency of the intermediate frequency signal to be output from the DRP (10), M, N, O is the first, second, third specific signal It means an argument.
In addition, as a result of the simulation, in order to obtain a BER of 10 ^-2 in the conventional receiver, about -2.6 dB of power is required, but in the receiver 100 using the digital high frequency processing technique and the zero crossing technique according to the present invention, In order to obtain a BER of 10 ^-2 , it can be seen that power is about 3 dB lower than that of the conventional receiver. However, this is not a big problem in preparation for the advantages that can be obtained by using the receiving apparatus 100 using the digital high frequency processing technology and the zero crossing technology as shown in Table 1 and Table 2 below.

At this time, Table 1 is a table showing the advantages for Hardware Expense, Table 2 is a table showing the advantages for Power Consumption. Table 1 shows a 68% reduction in hardware expenditure, and Table 2 shows a 67% reduction in power consumption.

Receiver Function Conventional receiver with a simple binary correlator SZXD & simple binary correlator DRP front end 1 DRP front-end with two branches for inphase and quadrature components
≒ 101% 1 DRP front-end with a single branch for the intermediate frequency signal
≒ 50% Analog-to-digital conversion 2 analog-to-digital converters (ADCs), having a resolution of minimum 8bits, operating at 8MHz each
≒ 155% 1 Comparator and a counter operating at 60MHz ~ 90MHz
≒ 0.01% Receiver processing before correlation Matched filter with two branches and a threshold detector
≒ 62% Sample selector
≒ 50% 318% 100%

Receiver Function Conventional receiver with a simple binary correlator SZXD & simple binary correlator DRP front end ≒ 104% ≒ 52% Analog-to-digital conversion ≒ 106% ≒ 0.01% Receiver processing before correlation ≒ 85% ≒ 48% ≒ 295% 100%

While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

The present invention can be applied to a technique for receiving a high frequency signal. In particular, by combining a digital high frequency processing technique and a zero crossing technique, an intermediate frequency signal is detected from a high frequency signal received from the outside, and converted into a short range wireless signal. By processing, the hardware volume of the receiver can be reduced, and a low power design can be achieved, thereby reducing the production cost of the receiver.

1 is a block diagram illustrating a schematic configuration of a short range wireless signal receiving apparatus using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

2 is a flowchart illustrating a method for receiving a short range wireless signal using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

3 is a graph illustrating a simulation result of a short range wireless signal receiver using a digital high frequency processing technique and a zero crossing technique according to an exemplary embodiment of the present invention.

<Description of main parts of drawing>

10: digital high frequency processor 11: amplifier

12: MTDSM 12a: Sampler

12b: RF filter 12c: first IF filter

13: IF processor 13a: IFA

13b: second IF filter 20: zero-cross signal detection unit

21: comparator 22: parallax

23: data detector 30: signal processing unit

31: chip-bit mapper 100: short-range wireless signal receiver

Claims (8)

Receiving the high frequency signal, and sequentially removing the first specific signal factor, the second specific signal factor, and the third specific signal factor from the received high frequency signal, thereby converting the high frequency signal into an intermediate frequency signal.

(here,

Is an intermediate frequency signal,

A digital high frequency processor converting the received high frequency signal, M, N, O into first, second and third specific signal factors; A zero crossing signal detection unit detecting a zero crossing signal from the intermediate frequency signal, and converting the detected zero crossing signal into a digital signal; Short range wireless signal receiving apparatus using a digital high-frequency processing technology and zero-crossing technology comprising a. The method of claim 1, The zero-cross signal detection unit A short-range wireless signal receiving apparatus using a digital high frequency processing technique and a zero crossing technique, characterized in that either one of the selected zero crossing signal detection unit or the average (Averaging) zero crossing signal detection unit. The method of claim 1, The intermediate frequency signal is Short range wireless signal receiving apparatus using digital high frequency processing technology and zero crossing technology, characterized in that single bit. delete delete The method of claim 1, The zero-cross signal detection unit A short range wireless signal using a digital high frequency processing technique and a zero crossing technique characterized by detecting a time difference for a domain of a plurality of intermediate frequency signals, detecting the zero crossing signal, and converting the detected zero crossing signal into a digital signal. Receiver. The method of claim 1, And a signal processor for outputting the digital signal output from the zero-cross signal detection unit to a physical layer protocol data unit (PPDU). The short range wireless signal receiver sequentially removes the first characteristic signal factor, the second characteristic signal factor, and the third characteristic signal factor from the high frequency signal received from the outside, thereby converting the high frequency signal into an intermediate frequency signal.

(here,

Is an intermediate frequency signal,

Is a received high frequency signal, M, N, O are first, second and third specific signal factors; Detecting, by the short range wireless signal receiving apparatus, a zero crossing signal from the intermediate frequency signal, and converting the detected zero crossing signal into a digital signal; Short-range wireless signal receiving method using a digital high-frequency processing technology and zero-crossing technology comprising a.

Images