EP0594830A4

EP0594830A4 - System for monitoring circuit breaker operations and alerting need of preventative maintenance.

Info

Publication number: EP0594830A4
Application number: EP19930911207
Authority: EP
Inventors: David L Swindler
Original assignee: Square D Co
Current assignee: Schneider Electric USA Inc
Priority date: 1992-05-12
Filing date: 1993-05-10
Publication date: 1994-11-23
Also published as: CA2113193A1; AU4242293A; EP0594830A1; WO1993023760A1; AU665433B2; MX9302782A

Abstract

A system which automatically monitors critical circuit breaker (C) operating parameters during each operation of the circuit breaker. Monitored parameters include the currents being interrupted, trip coil voltage and current, position of the contacts, initiation of closing, over travel of the contact mechanism on closing, contact opening and closing point and pressure in SF6 circuit breakers. These parameters are sampled and stored in memory (M) in the circuit breaker. The sample memory is connected to a local microcomputer (M) which is in communication with a host computer (H). Upon receipt of a command from the host computer (H) a local microcomputer in the circuit breaker (C) transmits the sample data to the host computer (H) for storage and analysis. The host computer (H) compares the stored data for each operation with acceptable operation curves. If the data indicates operation outside of various acceptable ranges, the maintenance department is automatically notified of the potential problem, to allow preventative maintenance and further testing, if desired.

Description

Title: SYSTEM FOR MONITORING CIRCUIT BREAKER

OPERATIONS AND ALERTING NEED OF PREVENTATIVE MAINTENANCE

SPECIFICATION BACKGROUND 07 THE INVENTION

1. Field of the Invention

The invention relates to operation of power circuit breakers, and more particularly to monitoring operations of power circuit breakers and determining if a potential failure is developing so that preventative maintenance can be performed.

2. Description of the Related Art Circuit breakers are used in industrial environments to prevent damage to both the connected electrical equipment, typically transformers and electric motors, and the remainder of the electrical system. These circuit breakers are available in numerous sizes and ratings, commonly for nominal voltages ranging from 4 kV to 13.8 kV, interrupting capacities from 250 to 1000 MVA and continuous currents from 1200 to 3000 A.

There are two predominant types of these breakers in this range of ratings, vacuum and SFg, referring to the medium in which the arc^' is developed on contact opening. The breakers are generally large units which are relatively difficult to move and physically inspect. Further, the contact mechanism is located in a sealed chamber or bottle to preserve the vacuum or SFg environment.

As the circuit breakers are electromechanical devices, they wear and age, and as a result may fail during operation. As a failure may have highly undesirable results, such as damage to electrical equipment or upset of a process being controlled, it is desirable to determine the condition of the breaker so that preventative maintenance can be performed to replace suspect components. Breakers always include an operation counter, but this count provides only a very general indication of condition and so can not be used when more accurate conditions must be known. To this end it is conventional to test the circuit breaker at periodic intervals. Various tests include motion analysis, where the operating speed and contact break time are monitored; pressure testing for vacuum or SF₆ leaks; dielectric testing; trip coil voltage and current monitoring during simulated trip conditions; and mechanical vibration monitoring during operations. However, most of these tests require that the circuit breaker be removed from service during the test. Because of the time required to perform the tests and the number of circuit breakers commonly present in an industrial setting, the expense of the testing and the significant down times are a major burden in operation of the plant. As a result, the testing is often not performed on a sufficiently frequent basis to detect the onset of problems.

In a partial resolution, some circuit breakers include pressure sensors, motion analyzers and total energy dissipation recorders. However, visual inspection of the units is still required and the analysis capability of the units is limited, so many of the tests still have to be performed. ^"•

It is therefore desirable to have a system which automatically monitors circuit breakers without requiring them to be removed from service, with this monitoring being performed frequently to allow early detection of possible problems, so that maintenance on the circuit breaker can be coordinated with a planned down time for the plant. SUMMARY OF THE INVENTION

A system according to the present invention automatically monitors critical circuit breaker operating parameters during each operation of the circuit breaker. These parameters are stored and provided to a host computer for analysis. The host computer compares the stored data for each operation with acceptable operation curves. If the data indicates operation outside of various acceptable ranges, the maintenance department is automatically notified of the potential problem, to allow preventative maintenance and further testing, if desired.

Numerous parameters of the circuit breaker are monitored during each operation. Preferably these parameters include the currents being interrupted, trip coil voltage and current, position of the contacts, initiation of trip and closing, overtravel forces on the contact mechanism on closing in vacuum breakers, contact open and close status, trip latch status, and pressure. When the circuit breaker is tripped, these parameters are sampled at a relatively high rate and digital values are stored in a sample memory until the breaker is closed. Preferably the sample memory is sufficiently large to allow sampling over both a sufficient time for each portion of each operation and for a plurality of operations.

The sample memory is also connected to a local microcomputer which is in communication with a host computer. Upon receipt of a command from the host computer, the local microcomputer transmits the sample data to the host computer for storage and analysis. On a periodic basis the host computer analyzes the sample data with reference to various curves and information developed from historical data and manufacturer test data. Preferably the analysis provides several levels of warnings, such as a simple notice, higher level warnings and highest level alerts, when the sample data indicates that the breaker condition is deteriorating to the various levels. Preferably the analysis also indicates which components in the breaker may need replacement.

Thus a system according to the present invention automatically monitors each circuit breaker operation and automatically analyzes each operation against acceptable performance parameters to determine when the breaker may need maintenance to prevent a failure. The monitoring is done while the circuit breaker is in service, greatly reducing the out of service time of the breaker, and at a very high frequency, namely each operation of the breaker. Notices are provided to allow scheduled maintenance.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained with the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:

Figure 1 is a block diagram of a monitoring and analysis system according to the present invention; Figure 2A and 2B are detailed block diagram portions of the circuit breaker C and the monitor M of Figure 1;

Figures 3A and 3B are side and front views of portions of the operating mechanism of a vacuum breaker showing the installation of the pressure transducer; Figure 4 is a state machine illustration of operation of the state machine 110 of the monitor M of Figure 2B; Figures 5, 6 and 7 are flow chart illustrations of operating sequences of the microcomputer 124 of Figure 2B; and

Figure 8 is a flow chart illustration of the operating sequence of the host computer H of Figure 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to Figure 1 the general organization of a system according to the present invention is shown. A circuit breaker C is connected to a monitor M. The monitor M in turn is connected to a host computer H. As shown in Figure 1, a plurality of circuit breaker C and monitor M pairs can be connected to the host computer H. In the shown embodiment the monitor M preferably communicates with the host computer H over a serial communications link, such as one according to a standard protocol such as RS-422, and the host computer H includes a plurality of serial data ports to communicate with the various monitors M. In other embodiments the monitors M can be connected to local area networks or other multiported or bused communications arrangements. Indeed, the communications link between the monitor M and the host computer H can be done over dial-up links so that the host computer H is located at a great distance from the monitor M, not in the particular plant location of the circuit breaker C and the monitor M.

The circuit breaker C includes certain new or additional elements for inclusion in a circuit breaker according to the prior art. Referring now to Figure 2A, this new circuitry is shown. Preferably the circuit breaker C is for three phase operation such that phases A, B and C or øA, φB and φC are referred to in this description. Circuit breaker C for three phase operation includes three individual bottles 20, 22 and 24, used respectively for phases A, B and C of the three phase line. Each bottle 20, 22 and 24 contains the breaking hardware or contacts for the particular phase. The actual contact mechanism in each bottle 20, 22 and 24 is driven simultaneously by various levers, bars, arms and shafts contained in the circuit breaker C. For purposes of the illustration of Figure 2A, the drive mechanism or arm is represented as element 26, which is connected to and driven by a trip coil 28. It is understood that this is a highly simplified illustration of operation of an actual circuit breaker, which have numerous variations in design. It is understood that the present invention can be adapted to the various types of circuit breakers which are available and that they all operate in a similar fashion. A potentiometer 30 has its wiper 32 connected to the arm 26. This wiper 32 arrangement is used to provide position feedback of the contacts in the circuit breakers C. As the arm 26 is moved by the trip coil 28 and the other mechanisms in the circuit breaker C, the wiper 32 traverses the potentiometer 30, either in a rotary or linear fashion depending upon the particular arrangement, such that the voltage present at the wiper 32 varies, thus allowing a determination of contact position. The potentiometer 30 and the wiper 32 are connected to position interface circuitry 34, which provides the necessary voltages to the potentiometer 30 and utilizes the wiper 32 signal to develop an output signal referred to as the POSITION signal utilized by the monitor M. Preferably the

POSITION signal is an analog signal having a desired range preferably from -5 to +5 volts as the arm 26 traverses. By sampling this POSITION signal at predetermined times not only the actual position but also the rate of the travel of the arm 26 can be developed. A close coil 29 is also connected to the arm 26 and is used to initiate the closing process.

The circuit breaker C preferably provides a contact set opened and closed by the trip latch of the breaker C, this contact set referred to as the trip latch switch contacts. The trip latch switch is used to enable the closing circuitry to automatically reclose. When the contacts are open the mechanism is not in position to allow closing of the circuit breaker. The trip latch switch contacts can thus be monitored to determine when the reclosing operation could be commenced.

The circuit breaker C also preferably provides a contact set which is used to indicate the open/closed status of the circuit breaker C. These contacts can be either normally open or normally closed, as desired. Thus monitoring of the state of the contacts allows a determination of the open/closed state of the circuit breaker C. In the preferred embodiment each of the bottles 20, 22 and 24 includes a pressure sensor to allow determination of the pressure of either the vacuum or the SF₆ contained in the bottle 20, 22 and 24. The pressure transducers produce signals referred to PRESSUREA, PRESSUREB and PRESSUREC, which are provided to pressure interface circuitry 38. The pressure interface circuitry 38 appropriately conditions and level shifts the PRESSUREA, PRESSUREB and PRESSUREC signals and produces PRESSAF, PRESSBF and PRESSCF signals, which are provided as three inputs of a four input analog multiplexor 40. Preferably the fourth input of the multiplexor 40 receives a highly accurate calibration analog level which is used in calibration of the monitor M. The output of the multiplexor 40 is referred to as the PRESSM or multiplexed pressure signal. The selection of the particular inputs of the multiplexor 40 is provided by two signals referred to as C0UNT<5-6> provided to the selection inputs of the multiplexor 40. The COUNT signals will be defined in greater detail below.

The PRESSM signal is provided as one input to a four input analog multiplexer 41. The output of the multiplexer 41 is the PRESS & FORCE signal. The selection of the particular inputs is provided by two signals referred to as COUNT<3-4>.

Each of the bottles 20, 22 and 24 in vacuum breakers preferably also includes a pressure switch or transducer in each individual operating mechanism, which is shown in Figs. 3A and 3B, described below in more detail. As the contacts are closing, the pressure in the operating mechanism is relatively low until the contacts are actually closed. At that time the force increases as the mechanism overtravels, providing a bias force to keep the contacts closed. Measuring the force in each individual mechanism allows a determination of the actual contact closing point and wear, as the force increase point can be compared against the arm 26 position as provided by the potentiometer 30. The RFORCEA, RFORCEB and RFORCEC signals from the pressure switches or transducers are provided to force interface circuitry 39. The force interface circuitry 39 converts and level shifts the RFORCEA, RFORCEB and RFORCEC signals to produce the FORCEA, FORCEB and FORCEC signals, which are provided to three inputs of the multiplexer 41, so that the force values can be monitored.

One additional parameter considered desirable to monitor for operation of the circuit breaker C is the actual currents present in each of the phases being interrupted. To this end current transformers 40, 42 and 44 are provided on the φA, φB and φC lines. Output signals from the current transformers 40, 42 and 44 are provided to current interface circuitry 46, 48 and 50, which provide as outputs the IφA, IφB and IφC signals, which are analog signals representative of the current level in the phase lines. The actual filtering and scaling of the signals is dependant on the desired output swing, the currents intended to be measured and the current transformer ratio. The current transformer 40, 42 and 44 signals are also provided to coil sensing circuitry 52. This is conventional circuitry in the circuit breaker C which is used to determine when the circuit breaker C should actually trip and perform its interrupting function. The coil sensor circuitry 52 provides a signal referred to as TRIP to the monitor M to indicate that circuit breaker operation is commencing. The coil sensor circuitry 52 is also connected to the trip coil 28. The signals provided to the trip coil .28 are provided to trip coil interface circuitry 54 which monitors both the voltage across and the current in the trip coil 28. The trip coil interface circuitry 54 provides TRIPV and TRIPI signals for use by the monitor M.

Preferably the coil sensor circuitry 52 also drives the close coil 29. Close coil interface circuitry 55 monitors the current provided to the close coil 29 to determine when the closing :operation has started. When the operation has started the close coil interface circuitry 55 provides a high level on a CLOSE START signal. This allows a determination of when closing has started so that closing parameters can be monitored.

Preferably the various interface circuitry 34, 38, 41, 46, 48, 50, 54 and 55 is located in the monitor M, which may preferably be located inside the actual housing of the circuit breaker C or may be at another location. Preferably the monitor M is located in the actual circuit breaker C housing so that only a single pair of wires for serial communication need be utilized between the circuit breaker C and any remote device.

Proceeding now to Figure 2B, the sampling and host interface circuitry of the monitor M is shown in more detail. Prior to discussing the actual operation of the circuitry, a brief overview is considered appropriate to help understand the detailed description to follow. Generally the monitor M has two portions, a sampling portion and a host interface portion. A bank of random access memory (RAM) 100 is provided to store sample data. During sampling of events, which are initiated by the TRIP signal and continue until sampling has been completed when the breaker C is closed, the sampling portion of the circuitry has exclusive control of the sample data RAM 100 to sample at a predetermined rate preferably selected to allow both sufficient resolution and sufficient total sampling time for calculation and comparison purposes. When sampling has been completed, a microcomputer 124 located in the host interface portion can communicate with the sample data RAM 100 to transfer data from the sample data RAM 100 to the host computer H over the serial link.

As a center of events, the sample data RAM 100 is preferably 16 bits wide to allow sufficient resolution for the phase current measurements and preferably comprises four banks of 32k words. With this size, each bank can conveniently be developed using a pair of 32k x 8 bit static RAMs which are readily available. Therefore a set of eight of these RAMs provides the necessary total sample data memory. Four banks of sample data RAM are preferably utilized because in the preferred embodiment the circuit breakers C can operate within three seconds of previous operations, a time considered to generally be insufficient to both complete sampling and allow complete data transmission to the host computer H over inexpensive serial ports. Therefore by allowing a plurality of banks of RAM, multiple operations can be stored without the need for high speed communications between the monitor M and the host computer H. Preferably this number is four banks because in most cases circuit breaker operation is completed after three short cycle operations, at which time the circuit breaker C goes fully open until manually reset.

Addressing now the sampling portion of the monitor M, the various analog signals such as IφA, IφB, IφC, POSITION, TRIPI, TRIPV and PRESS & FORCE are provided to seven of eight inputs of an eight input analog multiplexor 102. The output of the multiplexor 102 is provided to a sample and hold circuit 104, preferably a unit such as the SHA114H manufactured by Analog Devices, Inc. The output of the sample and hold circuit 104 is provided to the input of a 16 bit analog/digital (A/D) converter 106, preferably one such as the Analog Devices ADC1140 or other 16 bit A/D converter which is capable of sampling at preferably the audio frequency range. In the preferred embodiment the A/D converter 106 provides a STATUS signal to the sample and hold circuit 104 to control the operation of the sample and hold circuit 104 so that stable signals are provided to the A/D converter 106 for its operation. The outputs of the A/D converter 106 are signals referred to as VALUE<0-15>, the 16 bits of sample data. These data values are provided to the inputs of a 16 bit tristate buffer 108. The output of the tristate buffer 108 is provided to a 16 bit DATA bus which is connected to the data inputs of the sample data RAM 100. The tristate. control input of the buffer

108 is active low and receives the ANALOG signal from a state machine 110. The state machine 110 controls the operation of the sampling portion of the monitor M and will be explained in more detail below.

Preferably a 32.768 kHz oscillator is present in the monitor M to provide a basic clocking signal utilized to control the frequency of the sampling. This signal is provided to the clocking input of a D- type flip-flop 112. The inverted output of the flip- flop 112 is provided to the D-input so that the flip- flop 112 is configured in a toggling configuration. The noninverted output of the flip-flop 112 is referred to as the 16kHz signal, the basic clocking signal of the system, while the inverted output is referred to as the 16kHz signal. In this description a signal mnemonic with a line over it is the inverse of the signal mnemonic alone. Additionally, in many cases a signal mnemonic with a line over it is- considered to be active when in a low voltage or zero condition. The 16kHz signal is provided to the clocking input of a 16 bit counter 114. The 16 bit counter 114 has an inverted, asynchronous clear input which receives a CRESET signal from the state machine 110. The state machine 110 can thus control when the counter 114 is cleared and reset. The counter 114 also has a high true enable input which receives a CEN signal from the state machine 110 to allow the state machine 110 to stop and start the counter 114, preferably after opening sampling has completed and close sampling starts, ^"respectively. The counter 114 has 16 parallel outputs to indicate the actual count. All 16 bits are provided to the state machine 110 to allow the state machine 110 to determine when opening sampling is complete to prepare for closing sampling. The state machine 110 clears the counter 114 when bit 15, the most significant bit, becomes true. Thus the 16 bit counter 114 will count to a value of 32,768 and is then reset to 0, so that 32,768 samples are actually taken during a sampling phase. Based on a 16 kHz clocking signal, this provides an approximately 2 second total sampling interval when used with a 32k word sample data RAM bank. If a higher sampling rate is desired or less total sample time is desired, either the size of the sample data RAM 100 can be changed or the sampling frequency can be altered as desired. For instance, if greater resolution is required the 32.768kHz clocking signal can be increased. The lower 15 bits of the output of the counter 114 are referred to as the COUNT<0-14> signals. As previously noted, the C0UNT<5-6> signals are provided to the multiplexor 40 and the COUNT<3-4> signals are provided to the multiplexer 41 for selection of the particular input. The COUNT<0-2> signals are provided to the selection inputs of the multiplexor 102 so that each of the eight various inputs can be selected. It is noted that the input 0 of the multiplexor 102 is not connected. In this manner as the counter 114 counts through its various channels, each of the various inputs to the multiplexor 102 are cycled at approximately a 2 kHz rate, with the PRESS & FORCE signal from its second stage multiplexor 41 cycling through those particular four inputs at a slightly slower rate and the PRESS M signal from its first stage multiplexer 40 cycling at an even slower rate. The approximate 500 Hz rate for the FORCE signals is considered satisfactory as the mechanism movement is relatively slow and actual contact tip wear can be readily judged with this resolution. The even slower sampling rate for the PRESSURE signals is considered acceptable because the pressures do not change dramatically in the various bottles 20, 22 and 24 and are utilized more in a long term fashion then for transitory measurements. Further, calibration need not be taken with every sample set and therefore this infrequent reference to the calibrate level signal is considered satisfactory.

The COUNT signals have further uses. One of these uses is to form the address for the particular data sample in the sample data RAM 100. To this end, the COUΝT<0-14> signals are provided to the inputs of a 15 bit tristate buffer 116. The output of the buffer 116 is connected to a 15 bit ADDR or address bus. The fifteen bits of the ADDR bus are connected to the fifteen address inputs of the preferred devices in the sample data RAM 100. The inverted tristate control input of the buffer 116 receives a_signal referred to as μC or not microcomputer. This signal is a logic low level when sampling is occurring and the microcomputer 124 does not have access to the sample data RAM 100.

The COUNT<0-14> signals are also provided to the inputs of a 15 bit tristate buffer 118. The output of the buffer 118 is connected to the least significant 15 bits of the DATA bus. The inverted tristate control input of the buffer 118 receives a DIGITAL signal from the state machine 110. This DIGITAL signal is a logic level low signal when the count value indicates that the zero position of the multiplexor 102 is being accessed. In this case an analog value is not stored in the sample data RAM 100, but the state of the trip latch switch contacts and the COUNT value. The trip latch switch contacts are provided to an input of a tristate buffer 120, whose output is connected to the most significant or 15th bit position of the DATA bus, and ground. A resistor 121 is connected to the input of the buffer 120 and a logic high level to provide a pullup function, so that the open or closed state of the trip latch switch contacts can be determined. The DIGITAL signal is also connected to the inverted tristate control input of the buffer 120. Thus, the first sample of each sample set has as its most significant bit the trip latch switch contacts state and as its lower 15 bits the actual address of the data location. By providing this address as data, synchronization of the data in the sample data RAM 100 can easily be accomplished if for some reason synchronization is lost. The ANALOG signal is at a logic low level when the sampling section is active and the three least significant bits of the COUNT value are not zero, indicating that one of the connected analog channels of the multiplexor 102 is being selected and sampled.

The A/D converter 106 requires a signal to initialize a conversion operation. This signal is referred to as CONVERT A/D and is provided at the output of a two input AND gate 122. One input of the AND gate 122 receives the 16kHz signal while a second input receives the CRESET or counter reset signal from the s ite machine 110. The CRESET signal is active high during counting operations and thus also during sampling operations and is low at other periods when sampling is not being performed. The inverted form of the 16kHz signal is utilized so that a sample is actually obtained and converted during the second half of the actual cycle so that the various multiplexors have a time to properly settle out.

The TRIP signal produced by the trip coil sensor circuitry 52 is provided to the state machine 100 to initiate operation of a sampling cycle. Preferably the TRIP signal is a momentary signal which is removed or goes inactive prior to the completion of a sampling set. If this is not the case, the state machine 110 can be modified and additional circuitry can be added to convert the TRIP signal provided by the trip coil sensor circuitry 52 to the desired pulse.

The CLOSE START signal developed by the close coil interface circuitry 55 is provided to the state machine 110 to initiate closing operation sampling and is also preferably a momentary signal. The open/closed switch contacts are connected between ground and an input of the state machine 110. This input is pulled up by a resistor 123. This allows the state machine 110 to have a CLOSED signal which, when true, indicates that the circuit breaker C is closed, to stop closing operation sampling. Early termination of closing operation sampling is preferred because in many cases the circuit breaker C can retrip in 40 ms after becoming fully closed. Thus all sampling for the operation must be complete and all preparations for sampling the next operation must also be complete before the 40 ms elapses. If a full closing sampling time was allowed, the preparations may not be completed and the data for one operation would be lost. As noted above, the host computer H communicates with the monitor M by means of a microcomputer 124. Preferably this microcomputer 124 is an Intel Corporation 8051 microcomputer or similar, such as the Motorola Corporation 6801, the Texas Instruments TMS7041 and so on. Preferably the microcomputer 124 includes serial interface circuitry and has the capability to access external memory in addition to having various addressable input and output pins. The microcomputer 124 includes a serial link utilizing signals RXD and TXD which couple it to the host computer H. Not shown in Figure 2B are the other necessary signals to properly develop a complete serial link according to RS422. These signals are omitted for simplicity of the drawing and can be readily added and developed by one skilled in the art. In an alternative embodiment the RXD, TXD and other signals could be connected to a modem, which is then interfaced to a modem associated with the host computer H.

Four of the output bits of the microcomputer 124 are utilized to select the particular bank of the sample data RAM 100. Four bits are utilized because preferably the monitor M can address different banks during sampling and during data transmission to the host computer H. This allows data sampling to be interspersed with communications so that no loss of sample data is developed. The two bits of the sample data bank value are provided to the inputs of two tristate buffers 126 and 128, whose inverted tristate control inputs receive the Zc signal. The two bits forming the bank selection value for the communication portion are provided to the inputs of two tristate buffers 130 and 132. The noninverted tristate control inputs for the buffers 130 and 132 receive the μϋ signal. The output of the tristate buffer 126 and tristate buffer 130 are connected together and to a first input of a two to four decoder 134. The output of the buffer 128 and the output of the buffer 132 are connected together and to the second selection input of the decoder 134. By use of the tristate buffers 126- 132 the conversion between sampling and data communication is automatically made upon receipt of the TRIP signal without any further intervention by the microcomputer 124. The four outputs of the decoder 134, which is preferably 1/2 of a 74LS139, are provided to the active low chip enable inputs of the four banks of the sample data RAM 100.

As noted above, the microcomputer 124 is interfaced to the sample data RAM 100. To this end an 8 bit latch 136 is providing having its D inputs connected to the P0 output port of the preferred 8051 microcomputer 124 and having its enable input connected to the ALE or address latch enable signal of the microcomputer 124. The noninverted outputs of the latch 138 thus form the processor address PA<0-7> signals. Preferably bit positions 1-7 are provided to a 7 bit tristate buffer 138. The noninverted tristate control input of the buffer 138 is connected to the /Ic signal. The outputs of the tristate buffer 138 are connected to the seven least significant bits of the ADDR bus. The P2 port of the preferred 8051 microcomputer 124 provides the upper 8 bits of the desired address, referred to as the PA<8-15> signals. The P2 port is connected to the inputs of an 8 bit tristate buffer 140, whose noninverted tristate control input is connected to the μC signal. The outputs of the buffer 140 provide the 8 most significant bits of the address bus for the sample data RAM 100. Thus all 15 bits of the address are provided from the 15 most significant bits of the address provided by the microcomputer 124.

In the preferred embodiment the microcomputer 124 has the capability to read from and write to the sample data RAM 100. Therefore bidirectional transceivers are necessary from the DATA bus to the microcomputer 124. As the microcomputer 124 is preferably only an 8 bit microprocessor, selection of the particular halves of the DATA bus must be performed. To this end the upper 8 bits of the DATA bus, i.e. the DATA<8-15> signals are connected to the inputs of an 8 bit transceiver 142. The inverted tristate output control input of tt^r transceiver 142 is the PDOE1 signal or processor data bus output enable 1 signal. This signal is p: jvided by the output of a decoder block 144, preferably formed by a programmable logic device (PLD) such as programmable array logic (PAL) . The decoder 144 receives the R and TJ signals, the write and read strobes, from the microcomputer 124. The decoder 144 also receives the μC signal output by an inverter 152 whose input is the μC signal; the 16 kHz signal and the PA<0> signal. The decoder 144 provides the PDIR, PDOE1, PDOE2, RAMOE, RAMR/W1 and RAMR/W2 signals. The PDIR signal is provided to the direction input of the transceiver 142. The remaining signals are described below. The PDIR signal is based on the R and RD signals, while the

PDOE2 signal is a combination of the WR, ^"D, PA<0> and μC signals which is active only during the proper portions of the high byte read and write cycles when the microcomputer 124 has access to the sample'RAM 100. The outputs of the transceiver 142 are connected to the processor data or PD<0-7> lines, which are also the lines of the PO port.

The eight least significant bits of the DATA bus, that is bits <0-7>, are connected to the eight inputs of an 8 bit transceiver 146, whose outputs are also connected to the PD<0-7> signals. The direction input of the transceiver 146 receives the PDIR signal, while the inverted tristate output control input of the transceiver 146 receives the PD0E2 signal, which is pr rided by the decoder 144 during the proper portions of low byte read and write cycles when the microcomputer 124 has access to the sample RAM 100.

It is also necessary to properly control the output enable and read/write inputs of the sample data RAM 100. The read/write inputs of the sample data RAM 100 are connected to the RAMR/Wl and RAMR/W2 signals from the decoder 144. The decoder 144 uses the 16 kHz, μC, PA<0> and R signals to develop the RAMR/Wl and RAMR/W2 signals so that during the second half of a sample cycle the data is written to both the high and low bytes of the selected bank of the sample RAM 100 and during microcomputer 124 writes the proper byte of the selected bank is written. The output enable signal of the sample data RAM 100 is the RAMOE signal of the decoder 144. The decoder 144 uses the μC and RD signals to develop the RAMOE signal so that the sample RAM 100 is providing data during microcomputer 124 read operations. Sample PAL equations for the decoder 144 as shown below. RAMOE = RD • μC

RAMR/Wl = 16 kHz + μC • WR • PA<0>

RAMR/W2 = 16 kHz + μC • WR • PA<0> PDIR = WR

PD0E1 = μC • RD • PA<0> + μC • WR • PA<0> PD0E2 = μC • RD • PA<0> + μC • WR • PA<0> By this arrangement the output enable and read/write signals of sample data RAMs 100 are automatically developed depending upon whether the sample section or the microcomputer 124 has control of the sample data RAMs 100.

Two further connections are made to the microcomputer 124. One is the connection of the TRIP signal to an interrupt input of the microcomputer 124. Preferably this TRIP signal is connected to the higher priority interrupt, while the serial port interrupt developed by the internal serial port of the microcomputer 124 is a lower priority for reasons which will be described. For test purposes the microcomputer 124 also provides an output signal referred to as TEST which is provided to the state machine 110. By appropriately setting the TEST signal, operation of the sample section can be initiated upon request. This allows a calibration test to be performed by the microcomputer 124 upon initialization. In addition, the microcomputer 124 also includes an internal timer which allows the development of a real time clock for purposes of recording circuit breaker operation time and date. Preferably the timer interrupt is a lower priority interrupt. Referring to Fig. 3A, details of the pressure transducer or switch mounting are shown. The arm 26 is connected to an operating block 160. The operating block 160 is around a threaded rod 162, which has a nut 164 to retain the operating block 160. A pressure switch or transducer 166 is located around the rod 162 between the operating block 160 and the nut 164. As the circuit breaker C closes, the arm 26 moves upwardly, forcing the rod 162 upwardly. The motion is very easy until the operating block 16-0 contacts a flange 170, which is in contact with a spring 168. The operating block 160 continues upward against the force of the spring 168. At some time the contacts will close. At this time an additional counterforce beyond that of the spring 168 must be overcome. The additional counterforce is provided by the overtravel of the mechanism. The pressure transducer 166 has been partially loaded for the travel to this point, so that when the contacts close and the additional counterforce is applied, this change is transmitted by the transducer 166.

Fig. 3B is a side view of a breaker C showing the arm 26 and the bottle 20 so that the movement of the arm 26 can be more readily visualized.

Referring now to Figure 4, upon reset of the monitor M the state machine 110 proceeds to state S. In state S the CRESET and CEN signals are a logic low, while the ANALOG, DIGITAL and μϋ signals are at high logic levels. Thus in this state the microcomputer 124 has access to the sample data RAMs 100 and the sample section is on hold. The state machine 110 remains in state S while the TRIP signal and TEST signals are both inactive or low. If either of the signals goes to an active or high state, control proceeds to state 0 on the next rising edge of the 16kHz signal, the clocking signal of the state machine 110. In state 0 the CRESET and CEN signals are raised, and the DIGITAL and μC signals are lowered or made active. This is an indication that the trip latch contacts state and address value are to be provided to the sample data RAM 100 and that the sample section is in control. If the CLOSED signal developed from the open/close switch contacts is true, this is an indication that all sampling has completed and control returns to state S. If CLOSED is false, indicating sampling is still occurring. Control then proceeds to state 1, where the first analog value is actually provided to the sample data RAMs 100. The CRESET and CEN signals remain set high, while the ANALOG signal is made active or low and the DIGITAL signal is made inactive or high. Thus the buffers 108 are activated to provide data values from the A/D converter 106 to the sample data RAMs 100. Upon the next rising edge of the 16 kHz signal, control returns to state S if the CLOSED condition is true. Otherwise, the state machine 110 then proceeds through states 2, 3, 4, 5 and 6 (not shown for simplicity), where the various output signals remain the same. In these various states the other analog signals provided to the multiplexor 102 are sampled and provided to the sample data RAMs 100. Each of states 2, 3, 4, 5 and 6 similarly transfer to state S if the CLOSED signal became true, otherwise transferring to the next numerical state. In state 7, the final analog sampling state, again the values remain the same for analog data storage. From state 1 , control returns to state 0 if the breaker is not closed and the COUNT value has not reached 3FF or 16,383, which value indicates that opening operation sampling has completed, and the state machine 110 proceeds to go through the next sample set. If the CLOSED signal becomes true, control returns to state S. Control is also transferred to step S if the COUNT value is 3FF, the breaker C is not closed and a test is in process, so that the test can be stopped. The microcomputer 124 senses the return to state S and removes the TEST signal before the next rising edge of the 16 kHz signal, so that an endless loop does not form. If the COUNT value is 3FF, a test is not occurring and the breaker C is not closed, control proceeds to state R. In state R the CEN signal is lowered, so that the counter 114 is st pped. Thus the sample data RAM 100 is half full of opening operation data, with no more data being provided until state R is exited. Control remains in state R while the CLOSE START signal is not true. Therefore the sample section is holding, waiting for the breaker C to start closing. When the CLOSE START signal is received, control returns to state 0 and closing operation sampling commences. Closing operation sampling continues until the breaker C is closed, when control returns to state S, waiting for the next open operation. Additionally, when bit 15 of the counter 114 goes high, this is an indication that the final sample has been taken in any case and then control preferably proceeds directly to state S where the counter is reset and control of these sample data RAMs 100 is returned to the microcomputer 124. Preferably the BIT15 signal is used as an additional reset of the flip-flops comprising the state machine 110, so that an asynchronous transfer is made to state S. This prevents a 32,769th sample from overwriting the first sample in the sample data RAM 100. Asynchronous operation is considered acceptable in this case as the asynchronous change will occur while the 16kHz signal is high, so that a data write operation will not have commenced. Alternatively, a determination can be made if the count value is 7FFFh and this determination used as the transfer from state 7, with the true condition returning to state S and the false condition continuing sampling at state 0. Control remains in state S until the TRIP or TEST signals are again received. The microcomputer.124 performs certain operating sequences to enable it to perform its necessary functions. Referring now to Figure 5, the reset sequence 200 is shown. Upon reset of the microcomputer 124, control proceeds to step 202 where the necessary initialization steps are performed. Generally this will include presetting the port directions, preparing the serial port for operation and setting necessary memory values. Control then proceeds to step 204, where the TEST output bit is set to initiate a sample of the sampling section. It is noted that at this time the interrupts are preferably disabled so that communication with the host computer H cannot occur. Control then proceeds to step 206, where the output of the inverter 152, the μC signal, is continuously sampled until it goes to a low level, indicating that the sampling has been completed and the microcontroller 124 has control of the sample data RAM 100. Control proceeds to step 208, where the TEST bit is cleared so that the state machine 110 does not continually loop in the cycle. This clearing is readily done before the next rising edge of the 16 kHz signal so that the state machine 110 stays in state S. Control then proceeds to step 210 after all the samples have -een obtained to determine if the calibration values are satisfactory. As noted above, on a relatively infrequent basis the calibrate level signal is provided through the multiplexors 40, 41 and 102 to the A/D converter 106. As this level is preferably accurately set, when the microcomputer 124 reads a location or series of locations from the sample data RAM 100 which contain the calibration value, a simple determination can be made if the sample section is performing properly. If not, control proceeds to step 212, where a no calibration flag is set to indicate that the monitor M may not be operating properly. If calibration is satisfactory or after the no calibration flag is set in step 212, control proceeds to step 213 where all of the sample data RAM 100 is cleared. This clearing allows the host computer H to determine when close operation sampling stopped. Control then proceeds to step 214, where the interrupts are enabled and the microcomputer 124 proceeds to wait for an interrupt. This interrupt will either be based on the TRIP signal developing or upon one of the two lower priority events, either a serial communications event completion, either a transmission or reception, or a timer tick interrupt. Control remains in step 214, except for interrupt operations, as now all events of concern to the monitor M are interrupt triggered. As noted above, the TRIP signal is preferably the higher priority interrupt. If the TRIP signal is received, this initiates the trip sequence 250 as shown in Figure 6. In step 252 the microcomputer 124 monitors the μC signal input or output of inverter 152 to determine if the sample section has actually started sampling data. If not, control loops in step 252 until sampling has commenced. If sampling has started, control proceeds from step 252 to step 253, where the time and date are stored to allow determination of when the operation occurred. Control then proceeds to step 254, where the μC signal input is further monitored until sampling has been completed. In this manner, the microcomputer 124 can easily tell when it has access to the sample data RAM 100. After sampling has been completed, control proceeds from step 254 to step 256 where a determination is made if the sample RAM bank value is set to RAM bank 3. As indicated above, preferably there are four sample data RAM banks, numbered 0-3. If the current bank is already 3, control proceeds to step 258, where the set bank 3 full flag is set to indicate that valid data is contained in bank 3. If not, control proceeds to step 260, where the next sample RAM bank is selected, that is, the RAM bank number is incremented and provided to the particular output port. Control then proceeds to step 262 which is a return from the interrupt, which returns control to step 214 of the reset sequence 200. It is preferable that the TRIP interrupt be the higher interrupt so that the sample RAM bank incrementation done in step 260 can proceed even during data transmission so that no samples are lost until the circuit breaker C operates more than four times between collections of sample data.

If a low priority interrupt is received, indicating either that a serial operation interrupt or a timer interrupt has been issued, control of the microcomputer 124 proceeds to the serial/timer interrupt sequence 300 (Figure 7) . The first step of the serial interrupt sequence 300 is step 301, where a determination is made whether the interrupt is from the serial port or from the timer. If from the timer, control proceeds to step 303, where the various timekeeping functions necessary to keep time and date are performed. If the interrupt was a serial port interrupt, control proceeds to step 302, where the microcomputer 124 determines if the interrupt was based on a transmit complete or whether data has been received. If the microcomputer 124 was transmitting data, control proceeds to step 304 to determine if the microcomputer 124 was transmitting sample data to the host computer H. If not, this is an indication that the transmission has been completed and control proceeds to step 306, which is a return from the interrupt sequence 300. If sample data is being sent, this is an indication that the microcomputer 124 is in the midst of a long 64k byte data transfer and control proceeds to step 307 to see if the time pointer is equal to zero. The time pointer is a value used to indicate progress through the time and date value for the particular sample. If not equal to zero, control proceeds to step 309, where the indicated time data byte for the particular bank is transmitted and the time pointer value decremented. Control then proceeds to step 306. If the time pointer was equal to zero, control proceeds to step 306 to transmit the sample data byte and to increment an address pointer to the next value in the sample data RAM 100. Control then proceeds to step 308 to determine if this particular 16 bit value has rolled over to a value of 0 upon the increment. If so, this indicates that a complete 64k value bank has been read and control proceeds to step 310 to increment the read RAM bank number and to reset the time pointer to seven for the next bank. Control then proceeds to step 312 to determine if the last RAM bank was sampled. If not, or if the value was not 0 in step 308, control proceeds to step 306. If the last bank had been indeed been sampled, control proceeds from step 312 to step 316, where the sample data RAM 100 is cleared, the bank numbers of both the sample and read RAM banks are reset to 0 and the bank 3 full flag is reset or cleared. Control then proceeds to step 306.

If it was determined in step 302 that data had been received from the host computer H, control proceeds from step 302 to step 320 to determine if the microcomputer 124 had received the RAM bank number command from the host computer H. With this particular command the host computer H can determine the sample bank number being utilized by the microcomputer 124 to determine if any samples have been obtained. This value is incremented in the trip interrupt sequence 250 after a sample has been developed. Therefore if the value is not 0 this is an indication that a sample has been obtained. If this is the RAM bank number command, control proceeds from step 320 to step 322 where the sample bank number is transmitted to the host computer. Control then proceeds to step 306.

If the RAM bank number command was not received as determined in step 320, control proceeds to step 324 to determine if a transmit data command has been received for the host computer H. In this command all of the sampled data is transmitted from the monitor M to the host computer H for "storage and analysis. If this command has been received, control proceeds to step 326 where the read RAM bank value is set to 0; the RAM address value is set to 0; the time pointer value is set to six to allow for hours, minutes, seconds, month, day and year values and the first byte of time information is read and transmitted to the host computer H. Control then proceeds to step 306. If the transmit data command has not been received in step 324, control proceeds to step 327. It is assumed in the preferred embodiment that numerous other commands from the host computer H to the microcomputer 124 will be utilized, such as commands to request a test operation, determine if the monitor M is in calibration, set the time and date and others, but these commands are not detailed in this description for simplicity. If it was not another legal command, control proceeds to step 306. If a legal command has been received, control proceeds from step 327 to step 328, where the particular command is performed or the particular desired value is transmitted to the host computer H. The host computer H must also perform certain operating sequences to maintain contact with the monitor M and to perform its operations. This is shown in flowchart format in Figure 8. The host operating sequence 400 is commenced at step 402 by initialization of the host computer H. It is noted that the host computer H can be any particular computer such as personal computer, a dedicated, ruggedized, industrial computer, a mainframe computer and so on. It simply needs to be one that can communicate with the monitors M, store data as required and provide outputs and reports to the maintenance group at the plant. After initialization has completed, control proceeds to step 404, where a RAM bank number command is sent to the particular monitor M with which the host computer H is in communication. Control proceeds to step 406 to determine if the RAM bank number provided by the monitor M is equal to 0. If not, control proceeds to step 408, where the host computer H sends the transmit data request to the monitor M so that it can receive the data. Control then proceeds to step 410, where the data and time of operation is received and stored for later analysis. Additionally in step 410 the operation of the circuit breaker can be logged, such as on a printer, on a CRT or in a special log file. If the RAM bank number was equal to 0 in step 406 or after data is received from the monitor M in step 410, control proceeds to step 412, where a breaker number value is incremented. In the shown embodiment the host computer H preferably polls the various circuit breakers or monitors M. In other embodiments as can be developed by those skilled in the art, the monitor M could initiate its own communications with the host computer H but the polling scheme is considered preferable. After the breaker number is incremented, control proceeds to step 414 to determine if the last breaker in the polling sequence has been monitored. If not, control proceeds to step 404, where the next monitor M is interrogated. If the last breaker has been polled, control proceeds to step 416 to determine if it is time to perform the analysis operations. In the preferred embodiment the host computer H only performs the analysis at certain predetermined intervals to ease its processing functions and to allow the host computer H to be used for other activities. For instance, the host computer H could be used for other activities during the day and during late night or off shift times the desired analysis could be performed.

If it is time for analysis, control proceeds to step 418 where the necessary analysis is performed on all newly received data. This analysis includes several different areas. As a first function, circuit breaker lifetime accumulated values can be developed, such as closing and interrupting I²t, which are stress indicators. These values can then be compared against established limits so that maintenance needs can be indicated. In another analysis function, by comparing the current sir-it,"ure for the particular operation versus an ideal current signature, the arcing times can be compared, both for opening and closing of the breaker C. If the interruption or resumption occurs at the ideal time, the operation is satisfactory. If at some other time, then stress is indicated and a report can be logged. This signature is developed based on the actual magnitude of currents being interrupted or resuming and the relationship of the instantaneous current zeroes with the contact opening or closing. This signature can also be used to track the cumulative stress on the breakers, so that stress warnings, both cumulative and per operation can be provided if limits are exceeded. The number of recognitions, resumptions of current flow during opening, can also be readily determining from the phase current data, providing further basis for comparison. The opening and closing movements of the contacts themselves can be analyzed against acceptable values, so that if slow or erratic operation is shown, the possible problem can be noted. Similarly, the timing and operation of the trip latch switch can be monitored to determine if and when the breaker C was allowed to close. Additionally the actual contact tip wear can be monitored. As previously stated, the pressure transducer 166 indicates an increase in pressure when the contacts actually begin closing. By monitoring this point with the actual position of the arm 26 as provided by the potentiometer 30, a change in the tip condition can be determined. As the point of contact as indicated by the pressure transducer 166 is delayed in the cycle, tip wear is indicated, which can be the basis for logging a flag. The trip coil current and voltage can be compared against normal values, with problems logged for deviances beyond certain limits. Pressure for both SF₆ and vacuum breakers can be compared against norms and warnings logged when appropriate. After the analysis is completed, control proceeds to step 420 where particular reports are provided automatically based on problems or points logged during the analysis phase so that the maintenance department can determine and be informed of the various states of the particular circuit breakers. Preferably these reports include various levels of warnings such as the possibility of growing problems and alerts for the most severe problems or impending failures. If it was not time for analysis in step 416 or after the reports are developed in step 420, control proceeds to step 422 to determine if it is time to again poll the monitors M. If not, control loops at step 422 or performs other tasks as desired. When it is time to poll, control proceeds to step 424 where the breaker number is set to 0 and control proceeds to step 404 to poll the breakers.

The host computer H can also perform polling or analysis on demand from the operator. In one embodiment the operator can request an operational review of a single operation. After specifying the circuit breaker C and the particular operation, the stored data for that operation is displayed graphically, much as on an oscilloscope or strip chart recorder. Plotting of the data can also be requested. The host computer H may also be programmed to receive performed maintenance information so that an actual maintenance log for each particular breaker can be developed, in addition to the maintenance requests and warnings automatically provided by the host computer H based on its analysis functions. The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the invention.

Claims

CLAIMS: 1. A system for monitoring and analyzing circuit breaker operations comprising: a circuit breaker; means connected to said circuit breaker for recording circuit breaker operating parameters during each operation of said circuit breaker; a host computer located away from said circuit breaker and said means for recording operating parameters; and means connected to said host computer and said means or recording operating parameters for transferring said recorded circuit breaker operating parameters to said host computer; wherein said host computer includes: means to receive and store said recorded circuit breaker operating parameters; means to compare said recorded circuit breaker operating parameters to predetermined values for said circuit breaker operating parameters to determine if said recorded circuit breaker operating parameters are within acceptable limits; and means for providing an indication if said recorded circuit breaker parameters are outside of said acceptable limits.

2. The system of claim 1, wherein said means for recording circuit breaker operating parameters includes: means for receiving a plurality of analog signals representing said operating parameters; means for sampling said plurality of received analog signals at a predetermined rate and providing a plurality of digital signals corresponding to said plurality of analog signals; and means for storing the values of said plurality of digital signals.

3. The system of claim 2, wherein said host computer further includes means to request transfer of said recorded circuit breaker operating parameters and wherein said means for transferring includes: means for communicating with said host computer to receive said transfer request; and means responsive to said transfer request for reading said values stored in said means for storing and means for communicating said values to said host computer.

4. The system of claim 1, wherein said operating parameters include circuit breaker contact position and circuit breaker phase currents and wherein said host computer means for comparing includes means for developing a signature of expected phase current versus circuit breaker contact position to compare against actual phase currents and circuit breaker contact position.

5. The system of claim 1, wherein said operating parameters include circuit breaker trip coil current and wherein said host computer means for comparing includes means for comparing said actual trip coil current versus predetermined expected trip coil current.

6. The system of claim 1, wherein said operating parameters include circuit breaker opening and closing phase currents, wherein said means for recording records said parameters at regular intervals and wherein said host computer means for comparing includes means for developing, accumulating and storing a time - current stress value and comparing said accumulated value with predetermined limits.

7. The system of claim 1, wherein said circuit breakers are installed and operational in an electrical system.

8. The system of claim 1, wherein said circuit breaker includes a pressure bottle, wherein said operating parameters include the pressure in said pressure bottle and wherein said host computer means for comparing includes means for comparing said pressure with predetermined pressure limits.

9. The system of claim 1, wherein said circuit breaker includes a contact tip which wears, wherein said operating parameters include closing force, with said closing force increasing when said contacts are actually closed, and contact position, and wherein said host computer means for comparing includes means for comparing said contact position when said closing force increases with predetermined contact position values.

10. The system of claim 1, wherein said operating parameters include contact position, wherein said means for recording records said parameters at regular intervals and wherein said host computer means for comparing includes means for developing a movement profile of said contacts and comparing said profile with a predetermined profile. 11. A system for monitoring and analyzing a plurality of circuit breakers; the system comprising: a plurality of circuit breakers; a host computer; a plurality of means connected to said circuit breakers for recording circuit breaker operating parameters during each operation of said circuit breakers, one of said means for recording associated with each of said circuit breakers; and a plurality of means connected to said host computer and said means for recording operating parameters for transferring said recorded circuit breaker operating parameters to said host computer, one of said means for transferring associated with each of said means for recording; wherein said host computer includes: means to receive and store said recorded circuit breaker operating parameters for each of said circuit breakers; means to compare said recorded circuit breaker operating parameters to predetermined values for said circuit breaker operating parameters to determine if said recorded circuit breaker operating parameters are within acceptable limits for each of said circuit breakers; and means for providing an indication if said recorded circuit breaker parameters are outside of said acceptable limits.

12. The system of claim 11, wherein each of said means for recording circuit breaker operating parameters includes: means for receiving a plurality of analog signals representing said operating parameters; means for sampling said plurality of received analog signals at a predetermined rate and providing a plurality of digital signals corresponding to said plurality of analog signals; and means for storing the values of said plurality of digital signals.

13. The system of claim 12, wherein said host computer further includes means to request transfer of said recorded circuit breaker operating parameters from each of said means for recording and wherein each of said means for transferring includes: means for communicating with said host computer to receive said transfer request; and means responsive to said transfer request for reading said values stored in said means for storing and means for communicating said values to said host computer.

14. The system of claim 11, wherein said operating parameters include circuit breaker contact position and circuit breaker phase contact currents and wherein said host computer means for comparing includes means for developing a signature of expected phase current versus circuit breaker contact position to compare against actual phase currents and circuit breaker contact position.

15. The system of claim 11, wherein said operating parameters include circuit breaker trip coil current and wherein said host computer means for comparing includes means for comparing said actual trip coil current versus predetermined expected trip coil current. 16. The system of claim 11, wherein said operating parameters include circuit breaker opening and closing phase currents, wherein each of said means for recording records said parameters at regular intervals and wherein said host computer means for comparing includes means for developing, accumulating and storing a time - current stress value and comparing said accumulated value with predetermined limits.

17. The system of claim 11, wherein each of said circuit breakers are installed and operational in an electrical system.

18. The system of claim 11, wherein each of said circuit breakers includes a pressure bottle, wherein said operating parameters include the pressure in said pressure bottle and wherein said host, computer means for comparing includes means for comparing said pressure with predetermined pressure limits.

19. The system of claim 11, wherein each of said circuit breakers includes a contact tip which wears, wherein said operating parameters include closing force, with said closing force increasing when said contacts are actually closed, and contact position, and wherein said host computer means for comparing includes means for comparing said contact position when said closing force increases with predetermined contact position values.

20. The system of claim 11, wherein said operating parameters include contact position, wherein each of said means for recording records said parameters at regular intervals and wherein said host computer means for comparing includes means for developing a movement profile of said contacts and comparing said profile with a predetermined profile.