EP0569906A2 - Verfahren und System zum unmittelbaren Anschluss und Vermittlung eines digitalen Verzweigernetzes - Google Patents

Verfahren und System zum unmittelbaren Anschluss und Vermittlung eines digitalen Verzweigernetzes Download PDF

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Publication number
EP0569906A2
EP0569906A2 EP93107564A EP93107564A EP0569906A2 EP 0569906 A2 EP0569906 A2 EP 0569906A2 EP 93107564 A EP93107564 A EP 93107564A EP 93107564 A EP93107564 A EP 93107564A EP 0569906 A2 EP0569906 A2 EP 0569906A2
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Prior art keywords
input
output
matrix
center stage
dedicated
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EP93107564A
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French (fr)
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EP0569906B1 (de
EP0569906A3 (de
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Edward K. Bowdon
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Alcatel Lucent SAS
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Alcatel NV
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Priority claimed from US07/882,920 external-priority patent/US5343194A/en
Priority claimed from US07/883,593 external-priority patent/US5369400A/en
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Publication of EP0569906A3 publication Critical patent/EP0569906A3/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

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  • the present invention is concerned generally with electronics and more specifically with communications systems. Even more specifically, the invention is concerned with a method and system that eliminates delays in reswitching matrix configuration network devices when connections must be rearranged to permit signals to flow through the devices.
  • the invention is also concerned with a method and system for maintaining hitless connections in a cross-connect communications network while rearrangement operations in the communications matrix take place to eliminate service delays and interruptions during the network rearrangements.
  • Digital cross-connect communications network devices such as the 1631 SX manufactured by Alcatel Network Systems, Inc.
  • 1631 SX manufactured by Alcatel Network Systems, Inc.
  • Known designs for such cross-connect devices make use of matrices to connect the input gates to the output gates.
  • designers seek to minimize the number of cross-connects in the matrix This objective becomes more complicated as market demands for communications services increase.
  • the devices must service more and more input and output signals.
  • a rearrangeable matrix One matrix configuration that uses a minimal number of matrix cross-connects for a given number of input gates and output gates and that provides a potentially optimal solution is known as a "rearrangeable" matrix.
  • the number of center stage switches must equal or exceed the number of input gates on each input switch of the matrix.
  • a rearrangeable matrix there exists a set of conditions such that, although the device does not use all input gates and all output gates, an attempt to use an idle input gate and an output gate is prohibited because existing connections block the signal flow through the matrix. This may happen, for example, if existing connections already occupy at least one link in every possible path between the input and output gates in question.
  • rearrangeable In a rearrangeable network, it is always possible to unblock a flow path from an idle input gate to an idle output gate by moving existing connections in the network.
  • the present invention achieves this object with a minimal amount of additional circuitry and avoids the service delays and interruptions of known reswitching methods and systems.
  • the present invention achieves this object with a minimal amount of additional circuitry and avoids the service delays and interruptions of known rearrangement methods and systems.
  • FIGURE 1 a large matrix configuration is shown that provides for connection and test access for up to 1,024 DS3 ports (or equivalently, 32,678 DS1 ports) for the 1631 SX device.
  • This is a five-stage, Time-Space-Space-Space-Time (TSSST)-division multiplexed connecting matrix network 50.
  • Matrix configuration 50 includes time stage 52 that through connections 54 connects to three center space stage (SSS) designated generally by reference numeral 56.
  • Three center space stage SSS 56 connects through output line 58 to output time stage 60.
  • the network 50 includes a time-domain of time stages 52 and 60 and a space domain of three center space stage 56.
  • FIGURE 1 illustrates logically the relationship between time stages 52 and 60 and the center space stages 56.
  • Input time stage 52 uses 128 time slots per input 62.
  • the time slots may be represented by the connections 64 between I/O shelf inputs 62 to each time slot 66 of matrix 56.
  • Center space stage 56 includes 128 time slots 66, each of which time slot 66 includes a N(17,16,16) matrix.
  • the number 17 of time slot matrix 66 represents the number of center stage switches; the first number 16 represents the number of inputs to each input stage switch, and the second 16 the number of input stage switches. (By symmetry, there are 16 outputs from each output stage switch and 16 output stage switches.)
  • Output time stage 60 uses 128 time slot connections such as connection 68 for each matrix output 70 to an I/0 shelf.
  • center space stage 56 is represented mathematically as a three-stage connecting network cube of matrices 72 for each of which the symbol N(17,16,16) fully describes each of the matrices.
  • N(17,16,16) matrix 72 there are in the example of FIGURE 2, 16 input switches such as input switch 74, for which each receives 16 input gates such as input gate 76.
  • the total number of input gates 76 make up the I/O shelf-to-time slot connections 64 of FIGURE 1 for each time slot.
  • From each input switch 74 go input switch-center switch connections 78 to the center switches such as center switch 80.
  • each N(17,16,16) matrix 72 includes 17 center stage switches 80.
  • Each output switch 84 provides 16 output gates such as output gate 86 that connect to I/O shelves such as I/O shelf 70 of FIGURE 1. The total number of output gates 86 make up the time slot-to-I/O shelf connections 68 of FIGURE 1 for each time slot.
  • Connections are made between input gate 76 and output gate 86 immediately using the present connection technique.
  • This technique sets up a connection by using a route through input switch 74, center switches 80 and output switches 84 that attempts to use the most used part of a matrix 72 first and the least used part of the matrix 72 last.
  • the rearrangement process of the preferred embodiment encounters elements with the smallest number of preexisting connections. This minimizes the volume of necessary computations for matrix rearrangement.
  • the preferred embodiment uses a dedicated time slot when rearrangement is necessary in the time domain.
  • the 128th time slot may be dedicated as an extra time slot for use during matrix 50 rearrangement.
  • rearrangement uses a dedicated or extra center switch.
  • center switch 17 may be the dedicated or extra center switch.
  • the present connection technique automatically uses the dedicated or extra element (either the dedicated or extra time slot in the time domain or the dedicated center stage switch in the space domain) when a rearrangeably blocked condition exists.
  • FIGURE 3 illustrates that N(17,16,16) matrix 72 of FIGURE 2 may be generalized to matrix 88 for which the expression N(m,n,r) describes the configuration. Following the convention of the N(17,16,16) matrix 16, the generalized notation N(m,n,r) describes generalized matrix 88.
  • m the number of rxr center stage switches (as well as the number of outputs from each nXm input stage and the number of inputs to each mXn output stage switch);
  • n the number of inputs to each nXm input stage switch (as well as the number of outputs from each mXn output stage switch);
  • r the number of nXm input stage switches (as well as the number of mXn output stage switches).
  • matrix 88 m at least equals n+1. This limitation on m for a given n assures that there exists at least one extra center stage switch.
  • generalized matrix 88 has n input gates 90 that connect to input switches, such as input switch 92, having m output connections 94.
  • input switches such as input switch 92
  • the input switch-to-center switch connections 94 connect to the rXr center switches such as center switch 96 where each center switch 96 receives r center switch connections 94 and provides r output connections 98.
  • Each center switch-to-output switch connection 98 from center switches 96 connects to an output switch 100.
  • Each output switch 100 receives m center switch-to-output switch connections 98 and outputs to n output gates such as output gate 102.
  • Both the N(17,16,16) matrix 72 of FIGURE 2 and the N(m,n,r) matrix 88 of FIGURE 3 are said to be rearrangeable matrices if, respectively, for a given state of the matrix and any given idle pair of input gates 76 or 90 and output gates 86 or 102, the existing connections within the matrices may be reassigned to new paths, if necessary, to allow connecting the respective idle pairs.
  • the matrices are rearrangeable if and only if m ⁇ n.
  • the notation ⁇ (m,n,r) denotes the number of connections that must be rearranged in order to connect an idle pair of input and output gates.
  • Paull's Method derives from the property that ⁇ (n,n,n) ⁇ n-1.
  • N(n,n,n) matrix it is necessary to move at most n-1 connections to connect an idle input gate to an idle output gate.
  • FIGURE 4 introduces notation to assist in understanding the preferred embodiment.
  • FIGURE 5 provides a flow chart to illustrate the basic concepts of the immediate connect method and system of the present invention.
  • FIGUREs 6 through 14 show an example of the operation of the method and system in the presence of a rearrangeably blocked condition of a matrix 72 of the three center stage space matrix 56.
  • FIGUREs 15 through 34 that use a simplified N(5,4,4) rearrangeable matrix having the ability to perform immediate connection in a rearrangeably blocked condition.
  • FIGURE 4 notation beneficial for understanding the present invention uses square matrix 110 to represent connections existing in a space domain matrix such as matrix 88 of FIGURE 3.
  • Square matrix 110 has rows 112 designating input switches (such as input switch 92 of FIGURE 3) and columns 114 representing output switches (such as output switch 100 of FIGURE 3.)
  • the simplified example of FIGURE 4 shows the number of rows 112 and columns 114 equals 8.
  • FIGURE 5 could show a matrix having 16 rows representing input switches 74 and 16 columns representing output switches such as output switch 84.
  • matrix position 116 there are m possible symbols that may appear. These m symbols correspond to the center switches such as center stage switch 96 of FIGURE 3.
  • matrix position 116 may have m possible entries, one for each of the center stage switches 96 appearing in FIGURE 3.
  • the ordered pair (3,1) denotes matrix position 116, where 3 is the row designation, i.e., row 3 having reference numeral 118, and 1 is the column position, i.e., column 1 having the reference numeral 120.
  • the entry B (1 ⁇ B ⁇ m) in matrix position (3,1) corresponds to a connection from input switch 3 through intermediate switch B to output switch 1.
  • each input switch 92 has only one connection 94 to each center switch 96, no two symbols in any row 112 may be the same.
  • each output switch 100 has only one connection 98 from each center switch 96. No two symbols in any column 114 may be the same.
  • a square matrix 110 satisfying these restrictions is said to be "legitimate" since it has only legitimate entries.
  • flow chart 140 describes the steps and functions of the preferred embodiment of the present invention. Beginning at start step 142, the method is first to query, as query block 144 indicates, whether there is a pair of ports presented for connection. In the example of FIGURE 3, the step is to query whether there is an idle input gate 90 to connect to an idle output gate 102. If there is such a pair, then flow goes to block 146 to begin time domain connections. If there is not a pair of ports presented for connection, then flow goes to block 148 which is described below. At begin time domain step 146, flow goes to block 150 where the method selects the lowest numbered time slot available for connection. Then, at block 152 space domain operations begin for selecting the lowest numbered center stage input switch available for connection at step 154. Having selected the lowest numbered center stage for connection, the connections are made at block 156 and square matrix 110 or a similar status table designating connections is updated at block 158.
  • a query of whether space rearrangement is required takes place. If so, then flow goes to block 162 where the step is to select two center stage switches for rearrangement.
  • the step is to find the connections to be rearranged and, from the connections, the query at block 166 is of which path requires the least number of rearrangements. If the path X ⁇ A requires the least number of rearrangements, then program flow takes path 168. If X ⁇ B requires the least number of rearrangements, then program flow takes path 170. Regardless of which path program flow takes, at step 172 connections are rearranged, one at a time, using a "hitless roll.” The discussion below defines the term "hitless roll.” And flow returns to step 174 to end space domain operations. Note that if no space rearrangement was necessary, then flow from query block 160 goes directly to end space domain step at block 174.
  • step 176 the question is whether time rearrangement is required. If so, then flow goes to step 178 at which point the method is to select two time slots for rearrangement. Then, at block 180, the step is to find connections to be arranged.
  • a query occurs of which path requires the least number of rearrangements. If the X ⁇ A path requires the least number of rearrangements, flow goes along path 184. On the other hand, if the X ⁇ B path requires the least number of rearrangements, then flow follows path 186. The next step, regardless of whether program flow takes path 184 or 186, is to rearrange connections one-at-a-time, again using a hitless roll in the time domain at step 188. Program flow then goes to step 190 to end time-domain operations. Note that if query block 176 determines that no time rearrangement was required, flow proceeds directly to end time domain block 190.
  • the method determines whether a "pack connections after a disconnect" function is enabled. If so, then flow goes to query 198 to examine whether a rearrangement is in progress. If so, then flow will loop via path 200 until rearrangement is no longer in process.
  • FIGURE 5 shows disconnect as occurring subsequent to completing any necessary rearrangement
  • the present method and system may process a disconnect request in parallel with rearrangement. Therefore, if the system of the present invention seeks to direct connections to the most used part of matrix first so as to pack calls after a disconnect, the rearrangement-in-progress query of block 198, prevents attempting to pack during rearrangement.
  • next step is to determine the connections to the packed in the space at step 202.
  • the next step of flow chart 140 is to pack connections in the space domain using a hitless roll at block 204.
  • the step is to determine the connections to be packed in time, after which the connections are packed at block 206 in time using an automatically hitless roll.
  • Program flow then returns to point 210 to continue the previously described operations of flow chart 140.
  • Steps 162 and 178 execute Paull's Method to find the path requiring the fewest rearrangements. Specifically, with the blocked cell denoted (r1,c1) such as cell 121 of FIGURE 4, the method tests to find all symbol pairs (A,B) such that if A is in row 1, but not in column 1, and B is in column 1, but not in row 1. For given pairs of symbols, say (A,B), there are two possible rearrangement sequences, one of which will be shorter. Making this determination is part of step 16 in the space domain and step 182 in the time domain.
  • the sequence "X ⁇ A” denotes a sequence that starts with an immediate connection through the dedicated element (e.g., center stage switch 17 of FIGURE 2 for the space domain and the time slot 128 in FIGURE 1 for the time domain) and ends with the blocked cell being assigned to element A.
  • the sequence begins, for example, by starting with the blocked cell (r1,c1) at 121 of FIGURE 4). Since there is no B in row r1, the search for an A in r1 takes place. There must be an A in row r1, otherwise the matrix is not blocked. Once the A in row r1 is found, it is circled or tagged.
  • the sequence X ⁇ A continues to alternate between circling B's in columns in A's in rows, until there exists a column with no B to circle or a row with no A to circle. Note that not all A'S and all B's get circled, only those encountered in the above search.
  • Generating the X ⁇ B sequence occurs in similar fashion, as follows. Starting with the blocked cell (r1,c1) 121 of FIGURE 4, for example, there is no A in column 1, so the search begins for a B in column c1. There must be a B in column c1, otherwise the matrix would not be blocked. Then, procedure is to circle that B. Since the circled B is in position (r3,c1), the search for an A in row r3 begins. If there is no A in r3, then this sequence ends and program flow continues to step 164 or 180, as appropriate for the space or time domain. Otherwise, the procedure is to circle the A and continue. In this example, the circled A is in position (r3,c3), then the search begins for a B in column c3.
  • the next step is to choose the path generated by the sequence (either the X ⁇ A sequence or the X ⁇ B sequence) that contains the least number of circled symbols (i.e., A's or B's). For all such pairs of symbols, the step is to choose the pair (A,B) that contains the least number of circled symbols (either A's or B's).
  • This sequence determines the minimum number of rearrangements necessary to establish a path from the input to the output of the rearrangeable matrix.
  • the preferred embodiment Rather than completely generating all the X ⁇ A and X ⁇ B sequences, the preferred embodiment generates the shortest sequence. This is accomplished in block 164 in the space domain and block 180 in the time domain using a technique of the preferred embodiment that shall hereinafter be called a flooding algorithm.
  • the flooding algorithm starts by finding the first element of the X ⁇ A sequence. If the X ⁇ A sequence is not ended, the first element of the X ⁇ B sequence is found. Then, if the X ⁇ B sequence is not ended, the next element of the X ⁇ A sequence is found. This process continues until the shorter of the two sequences is generated. At the time that the shorter of the two sequences is generated, the search terminates.
  • the point at which flooding algorithm terminates determines the path of the minimum number of rearrangements as indicated in block 166 in the space domain and block 182 in the time domain.
  • step 172 for the space domain and step 188 for the time domain rearrangements take place using a hitless roll.
  • the method is to put an "X" in the (r1,c1) position indicating the connection was made through the extra center stage switch, (TABLE 1, Step 1 indicates this action).
  • the roll first adds X's (Step 2) and then removes the circled B's (Step 3).
  • the roll first adds the B's (Step 4) and then removes the circled A's (Step 5).
  • A's are first added (Step 6) and then the X's are removed (Step 7).
  • the X ⁇ B roll occurs in similar fashion to that of the X ⁇ A roll.
  • the first step is to put an X in the position (r1, c1) indicating the connection was made through the extra center stage (TABLE 2, Step 1).
  • the roll first adds X's (Step 2) and then removes the circled A's (Step 3).
  • the roll adds A's (Step 4) and then removes the circled B's (Step 5).
  • the roll adds the B's (Step 6) and finally removes the X's (Step 7).
  • Rearrangement is performed as necessary using a "head-end-bridge” and a “receive-end-switch” to effect a hitless roll (including the initial connection placed in the designated or extra element) to the lower numbered elements of the matrix.
  • head-end-bridge and receive-end-switch are defined and explained illustratively in connection with the example of FIGUREs 15 through 34 below.
  • Unpublished Appendix A includes a listing of the working source code to enable a computer to operate and perform the immediate connect method of the present method and system.
  • the following illustrative example shows how the preferred embodiment provides an immediate connect in the presence of a rearrangeably blocked condition in the space domain.
  • the time domain method becomes obvious upon understanding implementation of the space domain method.
  • FIGUREs 6 through 14 illustrate an example of the immediate connect method of the preferred embodiment.
  • cell (1,1) is marked as blocked because the present connection algorithm detected that the dedicated center stage switch is the only center stage switch having both an idle link to input switch 1 and an idle link to output switch 1.
  • connection algorithm in effect puts an X at (r1,c1) to make the connection, as FIGURE 6 shows.
  • the use of the notation "X" herein denotes the use of the dedicated or extra center stage switch in a rearrangeably blocked condition.
  • a rearrangeable blocking condition is automatically detected.
  • connection pair (1,1) Since the connection pair (1,1) is rearrangeably blocked, in order for a connection to be possible, there must exist an idle link between input switch 1 and some center stage switch, say A. Furthermore, there must exist an idle link between output switch 1 and some center stage switch, say B.
  • the pair (A,B) is one pair of center stage switches to be considered for rearrangement. In this example, the pair (A,B) is the only pair of center stage switches that meets the above criteria. Since the pair (A,B) constitutes the entire set of pairs to be searched, (A,B) is the pair that requires the fewest rearrangements.
  • FIGURE 7 shows the X ⁇ A sequence
  • FIGURE 8 shows the X ⁇ B sequence of the immediate connect algorithm of the preferred embodiment.
  • FIGURES 7 and 8 show the operation of the flooding algorithm of the preferred embodiment.
  • the first step starts off in FIGURE 7 at row r1 and finds an A in (r1,c2) which is circled.
  • FIGURE 8 shows the second step of the flooding algorithm which uses the X ⁇ B sequence and starts off in column c1 to find a circled B in (r3,c1).
  • the third step takes place back in FIGURE 7 wherein column c2 is examined for a B. This is found at position (r2,c2) and circled. Since there are no A's row r2, this X ⁇ A sequence is complete.
  • the two symbols in FIGURE 7 indicate two rearrangements are required.
  • FIGURE 8 Although the flooding algorithm of the present method ends at the third step, if it were to continue, in FIGURE 8 row r3 would be examined for an A, which would be found in position (r3,c3). This procedure would continue to alternate between circling B's in columns and A's in rows until either a column with no B to circle or a row with no A to circle.
  • the preferred embodiment chooses the X ⁇ A sequence for the pair (A,B). Since the pair (A,B) is the only pair of center stage switches being considered, the X ⁇ A sequence yields the minimum number of rearrangements.
  • the next step is to execute the rearrangements using the previously mentioned "hitless roll.” Since the X ⁇ A sequence yields the minimum number of rearrangements, the preferred embodiment uses the X ⁇ A roll in this example.
  • the hitless roll includes the initial connection placed in the dedicated center stage switch. This roll takes place by first performing the necessary rearrangement using a head-end-bridge and receive-end-switch.
  • FIGUREs 9 through 14 illustrate executing the X ⁇ A hitless roll.
  • the method changes the sequence of previously circled symbols A and B to clear the blocked cell as follows: For the circled B's add X's as FIGURE 9 shows. In this example, this step corresponds to setting up a head-end-bridge through the center stage switch at the extra switch X for the existing connection from input switch 2 through center stage switch B and a receive-end-switch through center switch X for the existing connection and from center stage B to output stage 2.
  • the next step is to remove the circled B's as FIGURE 10 shows.
  • the next step is to take down the connection from input switch 2 through center stage switch B to output switch 2.
  • FIGURE 11 shows for the circled A's add B's.
  • this step corresponds to setting up a head-end-bridge through the center stage switch B for the existing connection from input switch 1 through center stage switch A and a receive-end-switch through center stage switch B for the existing connection from center stage switch A to output switch 2.
  • FIGURE 12 shows, the circled A's are removed.
  • the next step is to take down the connection from input switch 2 through center stage switch A to output switch 2.
  • the next step is to add A's to the positions containing the X's, as FIGURE 13 shows.
  • this corresponds to setting up a head-end-bridge through center stage switch A for both the connection from input switch 2 through center switch X to output switch 2 and the immediate connection from input switch 1 through center switch X to output switch 1.
  • the final step is to remove the X's as FIGURE 14 illustrates.
  • the corresponding connection from the input switch through center switch X to the corresponding output switch may be taken down. Note that the extra center stage switch X is left idle, since all connections are rolled off the extra enter stage switch X to the appropriate center stage switch.
  • connection path selection method and system of the preferred embodiment For simplicity in describing this aspect of the present invention, the example considers connections in a further reduced N(5,4,4) space matrix 220 of FIGURE 15.
  • FIGURE 15 illustrates the state of a simplified N(5,4,4) space matrix 220 after initialization.
  • the fifth center stage switch 224 is labeled X to indicate that it is the dedicated or extra center stage switch.
  • legend 226 shows, short-dashed lines 228 indicate an idle link, continuous line 230 indicates a busy link, and long-dashed line 232 shows a switch connection. Since there are no inputs connected to any outputs in FIGURE 15, there are no input stage, center stage, or output stage switch connections and all of the links between the switches are idle.
  • FIGURE 15 uses the same reference numerals for input gates 90, input stage switches 92, etc. appearing in the generalized N(m,n,r) matrix of FIGURE 3. The following data definitions are useful in the description of the present connection method and system.
  • input/output gate or line conversions occur.
  • a connection may be requested in the form of IL-m ⁇ OL-n.
  • input line m to output line n.
  • the input line number is converted to an input switch stage number i and an input number for that input switch stage j such that IL-m ⁇ I(i,j).
  • the output line number is converted to an output switch stage number k and an output number for that output switch stage l such that OL-n ⁇ O(k,l).
  • the space input matrix 222 for the FIGURE 15 N(5,4,4) example is a 4x4 matrix which represents the connection of the input stage switches in the SSS such as switch 92.
  • Each row of space input matrix 222 corresponds to one of the input stage switches 92.
  • the columns of space input matrix 222 correspond to the input gates 90 to each of the first stage switches.
  • the entries in the space input matrix correspond to the outputs of the first stage switches such as outputs 94. Since the output of each of the input stage switches is connected to the center stage switch of the same number, the entries in the space input matrix may be viewed as the center stage switch to which that particular input stage switch (row), input (column) is connected.
  • the entries in space input matrix 222 range from 0 to X using the simplified example of FIGURE 15.
  • a 0 indicates that no connection has been assigned.
  • Entries of 1 through 4 are normal connections.
  • a numerical entry in matrix 222 of 5, in this example corresponds to the entry of "X" in FIGURE 6 and indicates that the extra center stage switch 224 has been assigned and the rearrangement process has been invoked.
  • Space center matrix 234 is a 5x4 matrix which represents the connection map of the center switches in the space domain such as center stage switches 96.
  • Each row of the space center matrix corresponds to one of the center stage switches 96.
  • the columns of the space center matrix correspond to the inputs to each of the center stage switches such as inputs 94.
  • the entries in the space center matrix correspond to the outputs of the center stage switches such as output 98. Since the output of each of the center stage switches 96 connects to the output stage switch of the same number, the entries in the space center matrix 234 may be viewed as the output stage switch to which that particular center stage switch (row), input column connects.
  • the entries in space center matrix 234 range from 0 to 4.
  • a 0 indicates that no connection has been assigned.
  • Entries of 1 through 4 are normal connections.
  • a zero entry in X th row i.e., the 5th row in this example indicates that the extra center stage switch 224 has been assigned and the rearrangement process has been invoked.
  • Space output matrix 236 is a 4x4 matrix which represents the connection map of the output stage of the space matrix in the space domain.
  • Each row of space output matrix 236 corresponds to one of the output switches such as output switch 100.
  • the columns of space output matrix 236 correspond to the output from each of the output switches such as output gates 102.
  • the entries in space output matrix 236 correspond to the input to which that output connects such as connections 98. Since the input of each output switch connects to the center stage switch of the same number, the entries in space output matrix 236 may be viewed as the center stage switch to which that particular output switch 100 (row), output gate 102 (column) connects.
  • the entries in space output matrix range 236 from 0 to X.
  • a 0 indicates that no connection has been assigned.
  • Entries of 1 through 4 are normal connections.
  • An entry of X i.e., 5 in this example) indicates that extra center stage switch 224 as been assigned and the rearrangement process has been invoked.
  • the present connection method attempts to make a given connection through the lowest-numbered center stage switch.
  • a given input stage switch such as input switch 92
  • a given output stage switch such as output switch 100
  • there must exist a certain center stage switch, such as center switch 96 with the property that there is an idle input link from input switch 92 to center switch 96 and an idle output link from center switch 96 to output switch 100.
  • the present method and system track idle input links and idle output links by using two different bit map arrays (one for input links and one for output links).
  • Each bit array map has a separate row for each row of the space center matrices.
  • the method uses a group of primitives to operate upon the bit maps to effect the connect and disconnect operations. The primitives, in turn, invoke the rearrangement process when required.
  • space input idle link bit map 238 is a 4x5 bit array that represents the idle input links 94 between the input switches 92 and the center switches 96 in the space domain.
  • Each row of space input idle link bit map 238 corresponds to one of the input stage switches 92.
  • the entries in space input idle link bit map 238 for a given row (input stage) and column (center stage) indicate the idle state of the input link 94 between that input stage and center stage.
  • An entry of 1 indicates that the input link is idle and available for assignment.
  • a 0 value indicates that the input link is in use and is not available for assignment.
  • a 0 entry in column X indicates that the extra center stage switch 234 is in use and the rearrangement method is in progress.
  • Space output idle link bit map 240 is a 4x5 bit array that represents the idle output links between the output and the center switches 96 in the space domain. Each row of space output idle link bit map 240 corresponds to one of the output stage switches 100.
  • the entries in the space output idle link bit map 240 for a given row (output switch) and column (center switch) indicate the idle state of the output link 98 between that output switch and center switch. An entry of 1 indicates that the output link is idle and available for assignment. A 0 value indicates that the output links is in use and is not available for assignment. A 0 entry in column X indicates that the extra center stage switch 224 is in use and the rearrangement method is in progress.
  • the initialize idle link bit maps primitive (used only for start-up operations) creates both space input idle link bit map 238 and space output idle link bit map 240 for the preferred embodiment. All entries in the idle link bit maps are initialized to 1, indicating that all links are idle. Primitive: set_link(i/o, j, k)
  • This primitive sets the k th bit of the j th row of the bit map specified by the "i/o" parameter to 1. If the bit map contains n elements and the value of j exceeds n, then the computer returns an error flag. Otherwise, the k th element is set to 1. Primitive: clear_link (i/o, j, k)
  • the preferred method and system connect between an input switch stage i and an output switch stage k using the lowest numbered center stage switch available. This is accomplished by a process that hereinafter shall be called “pumping" space_n_link[i] and space_out_link[k]. That is, space_in_link[i] is logically "ANDed" with space_out_link[k] to determine c, the lowest numbered center stage switch with both an idle link to input stage i and an idle link to output stage k. The index of the first non-zero entry in the result of the logical AND is c, the lowest numbered center stage switch with both an idle link to input stage i and an idle link to output stage k. The two links to c are then marked as "busy" in space_in-link[i] and space_out_link[k] and the center stage number c is returned. Table 3 illustrates an embodiment of this primitive macro.
  • FIGURE 16 illustrates the implementation data matrices after initialization.
  • the corresponding entries in the connection path selection matrices space_in_mat 222, space_cnt_mat 234, and space_out_mat 236, for the example, are illustrated in FIGURE 16. Since there are no switch connections, all of the entries are 0.
  • the contents of the space_in_link 238 and space_out_link 240 bit maps are as shown at initialization. Note that each input stage switch and each output stage switch has a 1 element for each idle center stage switch. In this example, after initialization, all five center stage switches are marked as "idle".
  • FIGURE 17 shows the implementation data after the first connection.
  • the first connection requested is to connect input line 1 to output line 1, or more simply, IL-1 ⁇ OL-1.
  • the first step is to convert the input line number to an input switch stage number and an input number for that input switch stage. In this case, IL-1 ⁇ I(1,1).
  • the output line number is converted to an output switch stage number and an output number for that output switch stage. In this case, OL-1 ⁇ O(1,1). So, we are going to make a connection between input stage 1 and output stage 1.
  • the present method and system attempt to make the connection between input stage 1 and output stage 1 by using the lowest numbered center stage switch available, which in this case is center stage 1. This is accomplished by using the pump_list macro of TALE 3 to compare space_in_link[1] with space_out_link[1] in FIGURE 16 and set the idle connects of the lowest center stage number common to both bit maps to "0". Then, the space_in_mat(i,j) and the space_out_mat(k,l) are set equal to that center stage number, and the space_cnt_mat(c,j) is set equal to k.
  • the corresponding space matrix data entries are shown in FIGURE 17 and the resultant state of the space matrix 220 is shown in FIGURE 18.
  • the request to connect IL-13 to OL-7 converts to a request connect I(4,1) ⁇ O(2,3).
  • the present method and system attempt to make the connection between input stage 4 and output stage 2 by using the lowest numbered center stage switch available, which in this case, is center stage switch number 4, as illustrated in FIGURE 20.
  • the pump_list macro of Table 1 compares space_in_-link[4] with space_out_link[2], determines the lowest center stage number common to both bit maps, and sets the idle status to "busy" in both bit maps. Then the space_in_mat(i,j) and the space_out_mat(k,l) are set equal to that center stage number and the space_cnt_mat(c,j) is set equal to k.
  • FIGURE 21 The corresponding space matrix data entries are shown in FIGURE 21 and the resultant state of the space matrix is shown in FIGURE 22. This process is accomplished using the following statements from the connect routine as before:
  • the put_back macro accomplishes the disconnect by breaking the connection between input stage 4 and output stage 2 and putting the freed-up center stage switch, number 4, back on the input/output stacks for subsequent use. More specifically, the put_back macro determines the freed-up center stage switch number and puts it back in the proper positions on both of the ordered-linked lists in space_in_link[4] and space_out_link[2]. Then, the space_in_mat(i,j), the space_cnt_mat(c,j), and the space_out_mat(k,l) are set equal to 0.
  • the present method and system attempt to make the connection between input stage 4 and output stage 3 by using the lowest numbered center stage switch available.
  • the X th or extra center stage switch 224 is the lowest number available center stage switch, as illustrated in FIGURE 25.
  • the pump_list macro accomplishes this by comparing space_in_stack[4] with space_out_stack[3] in FIGURE 23, determining the lowest center stage number common to both bit maps (which in this case is center stage switch "X"), and setting the idle status to "busy” in both bit maps. Then, the space_n_mat(i,j) and the space_out_mat(k,l) are set equal to that center stage number and the space_cnt_mat(c,j) is set equal to k.
  • An entry of 5 indicates that the X th center stage switch has been assigned and the rearrangement process is automatically invoked.
  • the corresponding space matrix data entries during rearrangement are shown in FIGURE 24 and the resultant state of the space matrix during arrangement is shown in FIGURE 25.
  • connection I(4,3) ⁇ O(2,1) that FIGURE 26 shows is "rolled" from center stage switch number 2 onto center stage switch number 4. This roll is performed hitlessly by creating a head-end-bridge at input stage switch 4 and a receive-end-switch at output stage switch 2 as shown in FIGURE 27.
  • the correct path is received at output stage switch 2 from center stage switch 4
  • the original connection through center stage switch 2 is dropped as shown in FIGURE 28 and the space matrix data is updated as shown in FIGURE 29.
  • This roll is performed hitlessly by creating a head-end-bridge at input stage switch 4 and an receive-end-switch at output stage switch 3 as shown in FIGURE 31.
  • the correct path is received at outputs stage switch 3 from center stage switch 2, the original connection through center stage X 224 is dropped.
  • FIGURE 32 shows the resulting state of the space matrix after rearrangement.
  • FIGURE 33 shows the corresponding space matrix data entries after rearrangement.
  • the system of the preferred embodiment invokes the rearrangement process automatically.
  • the system determines two center stage switches which will participate in the rearrangement process. This is accomplished using Paull's Method which is restated as follows: If (r1,c1) is blocked, test all symbol pairs (A,B), such that A is in row r1, but not in column c1 and B is in c1, but not in r1, to find which pair will require the fewest changes. The method then carries out the changing algorithm on that pair.
  • FIGURE 25 it is preferred to first transform the space_cnt_mat matrix data in FIGURE 24 into the format of FIGURE 4.
  • FIGURE 34 illustrates the results of this transformation.
  • the use of the dedicated center stage switch is indicated by the X in (r4,c3) of FIGURE 34.
  • the next step is to find all symbol pairs (A,B) such that A is in row r4, but not in column c3, and B is in column c3, but not in row r4. In this example, there is a 2 in row r4, but no 2 in column c3, so A is set to 2. Similarly, there is a 4 in column c3, but no 4 in row r4, so B is set to 4. Since there is only one value for A and one value for B, the (A,B) pair that requires the least changes is, obviously, the pair (2,4).
  • the X ⁇ A sequence starts with the immediate connection through the extra element and ends up with the blocked cell being assigned to element A or 2, in this case.
  • the blocked cell (r3,c4)
  • this step requires a circle around the 2 in row r3.
  • the circled 2 is in (r4,c2).
  • a search for a 4 in column c2 is necessary. Since there is none, this sequence is complete. (Note that not all 2's get circled.)
  • the X ⁇ B sequence starts with an immediate connection through the dedicated element 224 and ends up with the blocked cell being assigned to element B or 4, in this case.
  • the blocked cell (r3,c4)
  • there is no 2 in c4 so a circle goes around the 2 in c4.
  • the circled 4 is in (r3,c3).
  • a search for a 2 in r3 takes place. Since there is none, the sequence generation process is complete. (Note that not all 4's get circled.)
  • the flooding algorithm starts by finding the first element of the X ⁇ A sequence. If the X ⁇ A sequence is not ended, the first element of X ⁇ B sequence is found. Then, if the X ⁇ B sequence is not ended, the next element of the X ⁇ A sequence is found. This process continues until the shorter of the two sequences is completed. (So, the X ⁇ B sequence shown in FIGURE 34 is not really generated. It is shown here as an illustration of the alternate path.)
  • the method and system of the preferred embodiment immediately reswitch signal flow connections through a rearrangeable matrix that receives input lines having input signals to receive input signals or calls and has output lines for output signals, and therebetween center switching elements to connect the input lines to the output lines by immediately connecting an input line causing a rearrangeably blocked condition through the matrix to an output line through a dedicated or extra switching element of the center then detecting the rearrangeable blocking condition.
  • the method and system select a set of switching element pairs from the center switching element to form a plurality of possible connection configurations from the input lines to the output lines (excluding the dedicated switching element), then search from the set of all possible pairs of center stage switches for the connection configuration that requires a minimum number of rearrangements of the pre-existing connection configuration, and then reswitches the matrix according to the minimum connection configuration while maintaining all signal flow from the input lines through center stage switch into the output lines while removing signal flow through the dedicated switching element.

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EP93107564A 1992-05-14 1993-05-10 Verfahren und System zum unmittelbaren Anschluss und Vermittlung eines digitalen Verzweigernetzes Expired - Lifetime EP0569906B1 (de)

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US07/882,920 US5343194A (en) 1992-05-14 1992-05-14 Methods and system for immediately connecting and reswitching digital cross-connect networks
US07/883,593 US5369400A (en) 1992-05-14 1992-05-14 Method and system for hitlessly rearranging connections in a cross-connect communications network
US882920 1992-05-14
US883593 1992-05-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0569905A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren und System zum Selektieren von einer optimalen Umordnungs-Reihenfolge für einen Verzweigungsschalter
GB2315641A (en) * 1995-07-28 1998-02-04 Motorola Inc Adaptive telecomm switch

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08149524A (ja) * 1994-11-18 1996-06-07 Nec Corp 電子化本配線盤
JP2002320247A (ja) * 2001-04-24 2002-10-31 Fujitsu Ltd クロスコネクト装置
EP2337372B1 (de) 2009-12-18 2012-02-08 Alcatel Lucent Hochleistungsschaltsystem
CN113744948B (zh) 2021-09-01 2022-07-12 横店集团东磁股份有限公司 非晶磁粉芯前驱体颗粒、非晶磁粉芯、其制备方法及电感器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1344581A (fr) * 1961-11-24 1963-11-29 Western Electric Co Système de commande de réseaux de commutation
EP0240211A2 (de) * 1986-04-01 1987-10-07 Stc Plc Vermittlungsnetz
EP0399139A2 (de) * 1989-05-23 1990-11-28 ANT Nachrichtentechnik GmbH Verfahren zur Erweiterung eines dreistufigen regelmässigen Koppelfeldes
EP0569905A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren und System zum Selektieren von einer optimalen Umordnungs-Reihenfolge für einen Verzweigungsschalter
EP0569913A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren zur Wegeauswahl in einem Vermittlungsnetz

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394541A (en) * 1981-01-02 1983-07-19 Seiden Lewis J Three stage minimum configuration conditionally non-blocking matrix
US4887079A (en) * 1986-12-23 1989-12-12 At&T Bell Laboratories Rearrangeable multiconnection switching networks constructed using combinatorial designs

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1344581A (fr) * 1961-11-24 1963-11-29 Western Electric Co Système de commande de réseaux de commutation
EP0240211A2 (de) * 1986-04-01 1987-10-07 Stc Plc Vermittlungsnetz
EP0399139A2 (de) * 1989-05-23 1990-11-28 ANT Nachrichtentechnik GmbH Verfahren zur Erweiterung eines dreistufigen regelmässigen Koppelfeldes
EP0569905A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren und System zum Selektieren von einer optimalen Umordnungs-Reihenfolge für einen Verzweigungsschalter
EP0569913A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren zur Wegeauswahl in einem Vermittlungsnetz

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PROCEEDINGS OF THE EIGHTH ANNUAL JOINT CONFERENCE OF THE IEEE COMPUTER AND COMMUNICATIONS SOCIETIES, vol.1, 23 April 1989, OTTAWA (CA) pages 228 - 233, XP75832 N. FUJI 'Application of a Rearrangement Algorithm for Digital Cross-Connect System Control' *
PROCEEDINGS OF THE TWELFTH INTERNATIONAL TELETRAFFIC CONGRESS, vol.2, 1 June 1988, TORINO (IT) pages 908 - 914 JAJSZCZYK ET AL 'On congestion in switching networks composed of digital switching matrices' *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0569905A2 (de) * 1992-05-14 1993-11-18 Alcatel N.V. Verfahren und System zum Selektieren von einer optimalen Umordnungs-Reihenfolge für einen Verzweigungsschalter
EP0569905A3 (de) * 1992-05-14 1995-05-24 Alcatel Nv Verfahren und System zum Selektieren von einer optimalen Umordnungs-Reihenfolge für einen Verzweigungsschalter.
GB2315641A (en) * 1995-07-28 1998-02-04 Motorola Inc Adaptive telecomm switch
US5805574A (en) * 1995-07-28 1998-09-08 Motorola, Inc. Adaptive switch resource allocation in a satellite communication system

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CA2096206A1 (en) 1993-11-15
JPH06153249A (ja) 1994-05-31
CA2096206C (en) 2001-08-07
EP0569906B1 (de) 2003-01-15
AU3852393A (en) 1993-11-18
EP0569906A3 (de) 1995-05-24
KR100262474B1 (ko) 2000-08-01
CN1080106A (zh) 1993-12-29
KR930024350A (ko) 1993-12-22
ATE231316T1 (de) 2003-02-15
FI932176A (fi) 1993-11-15
SG49119A1 (en) 1998-05-18

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