EP0534133A1 - Insulating sealing device for lead-in layers of a protection housing - Google Patents

Insulating sealing device for lead-in layers of a protection housing Download PDF

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Publication number
EP0534133A1
EP0534133A1 EP92114206A EP92114206A EP0534133A1 EP 0534133 A1 EP0534133 A1 EP 0534133A1 EP 92114206 A EP92114206 A EP 92114206A EP 92114206 A EP92114206 A EP 92114206A EP 0534133 A1 EP0534133 A1 EP 0534133A1
Authority
EP
European Patent Office
Prior art keywords
layer
layers
intermediate carrier
printed conductors
conductor tracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92114206A
Other languages
German (de)
French (fr)
Inventor
Armin Dr. Baumgärtner
Wolfgang Heck
Johann Dr. Springer
Klaus Adam
Kurt Hägele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Alcatel Lucent NV
Original Assignee
Alcatel SEL AG
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SEL AG, Alcatel NV filed Critical Alcatel SEL AG
Publication of EP0534133A1 publication Critical patent/EP0534133A1/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Definitions

  • the invention relates to a device for the isolated routing of conductor tracks from a shielding housing, in which a thin-layer multilevel circuit with at least one integrated circuit mounted thereon is arranged on an intermediate carrier.
  • Such a device is known (publication: "Thin Film Polyimide Multichip Modules" from Advanced Packaging Systems p. 26).
  • a thin-layer multilevel circuit is arranged on an intermediate carrier, for example a ceramic plate, on which at least one integrated circuit is fastened.
  • the electrical connections of the integrated circuit are connected via micro wires to thin-film conductors on the multi-level circuit.
  • the thin-film multilevel circuit is arranged in a shielding housing, the wall of which is fastened to the intermediate carrier.
  • lines running beneath the wall of the shielding housing and embedded in the intermediate carrier are provided.
  • the technical problem on which the invention is based is to improve the known device in such a way that the routing of the conductive connections is easier to accomplish.
  • this solution has the advantage that the conductor tracks forming the leads do not have to be embedded in the intermediate carrier.
  • it is not necessary to produce the insulation layer and the solderable metal layer in separate process steps. Rather, they can be produced in the same operation in the production of the corresponding conductive layers and insulation layers of the thin-layer multilevel circuit.
  • the intermediate carrier 1 can be seen, which is attached to a printed circuit (not shown) and its contact surfaces 2 above Legs 3 are connected to conductors of the printed circuit in an electrically conductive manner.
  • the thin-film multilevel circuit 5, on which the integrated circuit 6 is fastened, is arranged on the intermediate carrier 1 within the shielding housing 4.
  • the electrically conductive connections between the integrated circuit 6 and the thin-layer multilevel circuit 5 are realized by the microwires 7.
  • the shielding housing 4 consists of the wall 8 shaped as a frame and the cover 9.
  • the insulation layer 10 and the solderable metal layer 11 are arranged between the contact surfaces 2 and the lower end of the wall 8.
  • the wall 8 is soldered to the metal layer 11 by means of a solder metal 12.
  • the thin-layer multilevel circuit consists, for example, of the alternating arrangement of conductor tracks made of aluminum layers and insulation layers made of polyimide.
  • the solderable layer applied to the top polyimide layer consists, for example, of vapor-deposited chromium + nickel + gold.
  • a soldering material e.g. PbSn
  • PbSn is galvanically applied to this layer by means of a photomask on certain surfaces, for example on which the components or the frame 8 are to be soldered.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

In electronics a large number of ICs are often arranged close together on a printed circuit board. This is achieved by fixing the IC(s) on an intermediate support (1), for example a ceramic plate, and contacting their terminals with printed conductors on the intermediate support. If the ICs (6) are disposed in a screening box (4), there is the need to run out the printed conductors (5) through the wall (8) of the screening box in an insulating manner. It is proposed, as a readily achievable solution, to arrange the printed conductors on the surface on the intermediate support and to provide, between the base of the screening box wall and the printed conductors, an insulating layer (10) and a solderable metal layer (11). <IMAGE>

Description

Die Erfindung betrifft eine Vorrichtung zur isolierten Herausführung von Leiterbahnen aus einem Abschirmgehäuse, in dem auf einem Zwischenträger eine Dünnschicht-Mehrebenenschaltung mit wenigstens einer darauf befestigten integrierten Schaltung angeordnet ist.The invention relates to a device for the isolated routing of conductor tracks from a shielding housing, in which a thin-layer multilevel circuit with at least one integrated circuit mounted thereon is arranged on an intermediate carrier.

Eine solche Vorrichtung ist bekannt (Druckschrift: "Thin Film Polyimide Multichip Modules" der Fa. Advanced Packaging Systems S. 26). Bei der bekannten Vorrichtung ist auf einem Zwischenträger, beispielsweise einer Keramikplatte, eine Dünnschicht-Mehrebenenschaltung angeordnet, auf welcher wenigstens eine integrierte Schaltung befestigt ist. Die elektrischen Anschlüsse der integrierten Schaltung sind über Mikrodrähte mit Dünnschichtleitern auf der Mehrebenenschaltung verbunden. Die Dünnschicht-Mehrebenenschaltung ist in einem Abschirmgehäuse angeordnet, dessen Wand auf dem Zwischenträger befestigt ist. Um elektrisch leitende Verbindungen zwischen der Dünnschicht-Mehrebenenschaltung und den am Rand des Zwischenträgers gelegenen Anschlußkontakten zu schaffen, sind unterhalb der Wand des Abschirmgehäuses verlaufende, im Zwischenträger eingebettete Leitungen vorgesehen.Such a device is known (publication: "Thin Film Polyimide Multichip Modules" from Advanced Packaging Systems p. 26). In the known device, a thin-layer multilevel circuit is arranged on an intermediate carrier, for example a ceramic plate, on which at least one integrated circuit is fastened. The electrical connections of the integrated circuit are connected via micro wires to thin-film conductors on the multi-level circuit. The thin-film multilevel circuit is arranged in a shielding housing, the wall of which is fastened to the intermediate carrier. In order to create electrically conductive connections between the thin-film multilevel circuit and the connection contacts located at the edge of the intermediate carrier, lines running beneath the wall of the shielding housing and embedded in the intermediate carrier are provided.

Diese bekannte Art der Herausführung der leitenden Verbindungen aus dem Inneren des Abschirmgehäuses zum Rand des Zwischenträgers macht erhebliche fertigungstechnische Schwierigkeiten, weil diese in dem Zwischenträger eingebetteten Leiterbahnen nur dadurch erzeugt werden können, daß dieser als Dickschicht-Mehrebenenschaltung mit Keramikisolationsschichten hergestellt wird. Die Durchführbarkeit dieses Herstellungsverfahrens wird durch die Breite der Leiterbahnen begrenzt.This known way of leading the conductive connections out of the interior of the shielding housing to the edge of the intermediate carrier causes considerable manufacturing difficulties because these conductor tracks embedded in the intermediate carrier can only be produced by producing them as a thick-layer multilevel circuit with ceramic insulation layers. The feasibility of this manufacturing process is limited by the width of the conductor tracks.

Das der Erfindung zugrundeliegende technische Problem besteht darin, die bekannte Vorrichtung in der Weise zu verbessern, daß die Herausführung der leitenden Verbindungen einfacher zu bewerkstelligen ist.The technical problem on which the invention is based is to improve the known device in such a way that the routing of the conductive connections is easier to accomplish.

Dieses technische Problem ist erfindungsgemäß dadurch gelöst, daß die Leiterbahnen auf der Oberfläche des Zwischenträgers angeordnet sind und zwischen dem Fußpunkt der Abschirmgehäusewand und den Leiterbahnen eine Isolationsschicht und eine lötbare Metallschicht angeordnet sind.This technical problem is solved according to the invention in that the conductor tracks are arranged on the surface of the intermediate carrier and an insulation layer and a solderable metal layer are arranged between the base point of the shielding housing wall and the conductor tracks.

Diese Lösung hat einerseits den Vorteil, daß die die Herausführungen bildenden Leiterbahnen nicht in den Zwischenträger eingebettet werden müssen. Andererseits ist es nicht notwendig, die Isolationsschicht und die lötbare Metallschicht in eigenen Verfahrensschritten herzustellen. Sie können vielmehr im gleichen Arbeitsgang bei der Herstellung der entsprechenden leitenden Schichten und Isolationsschichten der Dünnschicht-Mehrebenenschaltung mit hergestellt werden.On the one hand, this solution has the advantage that the conductor tracks forming the leads do not have to be embedded in the intermediate carrier. On the other hand, it is not necessary to produce the insulation layer and the solderable metal layer in separate process steps. Rather, they can be produced in the same operation in the production of the corresponding conductive layers and insulation layers of the thin-layer multilevel circuit.

Die Erfindung ist nachstehend anhand der Figur erläutert, welche einen Längsschnitt durch ein Ausführungsbeispiel der erfindungsgemäßen Vorrichtung zeigt. In der Figur ist der Zwischenträger 1 zu erkennen, welcher auf einer - nicht gezeigten - gedruckten Schaltung befestigt und dessen Kontaktflächen 2 über Anschlußbeine 3 mit Leiterbahnen der gedruckten Schaltung elektrisch leitend verbunden sind.The invention is explained below with reference to the figure, which shows a longitudinal section through an embodiment of the device according to the invention. In the figure, the intermediate carrier 1 can be seen, which is attached to a printed circuit (not shown) and its contact surfaces 2 above Legs 3 are connected to conductors of the printed circuit in an electrically conductive manner.

Auf dem Zwischenträger 1 ist innerhalb des Abschirmgehäuses 4 die Dünnschicht-Mehrebenenschaltung 5 angeordnet, auf welcher die integrierte Schaltung 6 befestigt ist. Die elektrisch leitenden Verbindungen zwischen der integrierten Schaltung 6 und der Dünnschicht-Mehrebenenschaltung 5 sind durch die Mikrodrähte 7 verwirklicht.The thin-film multilevel circuit 5, on which the integrated circuit 6 is fastened, is arranged on the intermediate carrier 1 within the shielding housing 4. The electrically conductive connections between the integrated circuit 6 and the thin-layer multilevel circuit 5 are realized by the microwires 7.

Das Abschirmgehäuse 4 besteht aus der als Rahmen geformten Wand 8 und dem Deckel 9.The shielding housing 4 consists of the wall 8 shaped as a frame and the cover 9.

Zwischen den Kontaktflächen 2 und dem unteren Ende der Wand 8 sind die Isolationsschicht 10 und die lötbare Metallschicht 11 angeordnet. Die Wand 8 ist mittels eines Lötmetalls 12 mit der Metallschicht 11 verlötet.The insulation layer 10 and the solderable metal layer 11 are arranged between the contact surfaces 2 and the lower end of the wall 8. The wall 8 is soldered to the metal layer 11 by means of a solder metal 12.

Die Dünnschicht-Mehrebenenschaltung besteht beispielsweise aus der abwechselnden Anordnung von Leiterbahnen aus Aluminiumschichten und Isolationsschichten aus Polyimid. Die auf der obersten Polyimidschicht aufgebrachte lötbare Schicht besteht beispielsweise aus aufgedampftem Chrom + Nickel + Gold. Auf diese Schicht wird mittels einer Photomaske auf bestimmte Flächen, beispielsweise an denen die Bauelemente oder der Rahmen 8 angelötet werden sollen, ein Lötwerkstoff (z.B. PbSn) galvanisch aufgebracht.The thin-layer multilevel circuit consists, for example, of the alternating arrangement of conductor tracks made of aluminum layers and insulation layers made of polyimide. The solderable layer applied to the top polyimide layer consists, for example, of vapor-deposited chromium + nickel + gold. A soldering material (e.g. PbSn) is galvanically applied to this layer by means of a photomask on certain surfaces, for example on which the components or the frame 8 are to be soldered.

Claims (1)

Vorrichtung zur isolierten Herausführung von Leiterbahnen aus einem Abschirmgehäuse, in dem auf einem Zwischenträger eine Dünnschicht-Mehrebenenschaltung mit wenigstens einer darauf befestigten integrierten Schaltung angeordnet ist,
dadurch gekennzeichnet,
daß die Leiterbahnen auf der Oberfläche des Zwischenträgers angeordnet sind und zwischen dem Fußpunkt der Abschirmgehäusewand und den Leiterbahnen eine Isolationsschicht und eine lötbare Metallschicht angeordnet ist.
Device for the isolated routing of conductor tracks out of a shielding housing, in which a thin-layer multilevel circuit with at least one integrated circuit mounted thereon is arranged on an intermediate carrier,
characterized,
that the conductor tracks are arranged on the surface of the intermediate carrier and an insulation layer and a solderable metal layer is arranged between the base point of the shielding housing wall and the conductor tracks.
EP92114206A 1991-09-21 1992-08-20 Insulating sealing device for lead-in layers of a protection housing Withdrawn EP0534133A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4131534 1991-09-21
DE4131534A DE4131534A1 (en) 1991-09-21 1991-09-21 DEVICE FOR THE INSULATED LEAD OUT OF PATHWAYS FROM A SHIELDING HOUSING

Publications (1)

Publication Number Publication Date
EP0534133A1 true EP0534133A1 (en) 1993-03-31

Family

ID=6441206

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92114206A Withdrawn EP0534133A1 (en) 1991-09-21 1992-08-20 Insulating sealing device for lead-in layers of a protection housing

Country Status (2)

Country Link
EP (1) EP0534133A1 (en)
DE (1) DE4131534A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007045511B4 (en) * 2007-09-24 2015-03-12 Continental Automotive Gmbh Module for integrated control electronics with simplified design

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522455A1 (en) * 1995-06-21 1997-01-02 Telefunken Microelectron Electromagnetic compatibility screening of electronic components esp. integrated circuits in motor vehicles
DE102013202037A1 (en) * 2013-02-07 2014-08-07 Olympus Winter & Ibe Gmbh Hermetic bushing, method of making a hermetic bushing, circuit board and surgical instrument

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2010429A1 (en) * 1969-02-28 1970-09-10 Hawker Siddeley Dynamics Ltd., Hatfield, Hertfordshire (Grossbritannien) Electrical circuit arrangement with a hermetic seal
DE3304215A1 (en) * 1983-01-20 1984-07-26 LGZ Landis & Gyr Zug AG, Zug Ceramic housing for a hybrid circuit
EP0266210A2 (en) * 1986-10-29 1988-05-04 Kabushiki Kaisha Toshiba Electronic apparatus comprising a ceramic substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2010429A1 (en) * 1969-02-28 1970-09-10 Hawker Siddeley Dynamics Ltd., Hatfield, Hertfordshire (Grossbritannien) Electrical circuit arrangement with a hermetic seal
DE3304215A1 (en) * 1983-01-20 1984-07-26 LGZ Landis & Gyr Zug AG, Zug Ceramic housing for a hybrid circuit
EP0266210A2 (en) * 1986-10-29 1988-05-04 Kabushiki Kaisha Toshiba Electronic apparatus comprising a ceramic substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007045511B4 (en) * 2007-09-24 2015-03-12 Continental Automotive Gmbh Module for integrated control electronics with simplified design

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DE4131534A1 (en) 1993-04-01

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