EP0524712A2 - Logic circuit - Google Patents

Logic circuit Download PDF

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Publication number
EP0524712A2
EP0524712A2 EP92301172A EP92301172A EP0524712A2 EP 0524712 A2 EP0524712 A2 EP 0524712A2 EP 92301172 A EP92301172 A EP 92301172A EP 92301172 A EP92301172 A EP 92301172A EP 0524712 A2 EP0524712 A2 EP 0524712A2
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EP
European Patent Office
Prior art keywords
flip
flop
signal
input
output
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92301172A
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German (de)
French (fr)
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EP0524712A3 (en
Inventor
Tomoaki Nakao
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Sharp Corp
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Sharp Corp
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Publication of EP0524712A2 publication Critical patent/EP0524712A2/en
Publication of EP0524712A3 publication Critical patent/EP0524712A3/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register

Definitions

  • the present invention relates to a logic circuit which includes at least one synchronous flip-flop.
  • the present inventor knows a four-bit shift register as one example of a CMOS (Complementary Metal-Oxide Semiconductor) logic circuit including synchronous flip-flops which are synchronized with clock signals.
  • This four-bit shift register is arranged to have four synchronous D-type flip-flops F1, F2, F3 and F4.
  • the flip-flops F1, F2, F3 and F4 are sequentially connected to each other. That is, the flip-flop F1 is serially connected to the flip-flop F2.
  • the flip-flop F2 is connected serially to the flip-flop F3.
  • the flip-flop F3 is serially connected to the flip-flop F4.
  • Each of synchronous flip-flops is connected to inverters. The inverters supply a clock signal to each flip-flop.
  • each of the flip-flops In an initial state that each of the flip-flops outputs a low-level signal, when a data signal which is input to the flip-flop F1 rises to a high level, at first, the flip-flop F1 latches the high-level data signal at the leading edge of the clock signal and outputs a high-level output signal H1. The flip-flop F2 latches the high-level signal H1 sent by the flip-flop F1 at the next leading edge of the clock signal and outputs a high-level output signal H2. Likewise, the remaining flip-flops F3 and F4 serve to output their high-level output signals H3 and H4 in the same process as above.
  • those flip-flops F1 to F4 serve to sequentially output the low-level signals L1 to L4 as being synchronized with the clock signals. That is to say, the data signal input to the flip-flop F1 is shifted to the next flip-flops as being synchronized with each leading edge of the clock signals so that the flip-flops F1 to F4 serve to output parallel signals in sequence.
  • the aforementioned shift register is arranged to inevitably receive a clock signal even when the data signal input to each flip-flop has the same logic level as the output signal of each flip-flop, therefore, in case that no flip-flops are required to change their states.
  • the clock signals input to the flip-flops result in flowing a charge and discharge current in internal circuits of the flip-flops, thereby consuming power. It means that such the logic circuit is arranged so that a clock signal is input to the flip-flops of the logic circuit if not necessary, resulting in flowing the idle current in the logic circuit.
  • the shift register needs an inverter arranged to have a CMOS transistor of a large driving capacity, for supplying clock signals to the flip-flops F1 to F4 of the shift register.
  • CMOS transistor having a large driving capacity entails flow of a large through current in internal circuits of the flip-flops when the clock signal is reversed. It is another disadvantage factor of increasing the idle current, that is, of increasing the power consumption.
  • the object of the invention can be achieved by a logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external, including: at least one synchronous flip-flop being synchronized with the clock signal, the flip-flop for latching the input signal; and a unit for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.
  • the controlling unit operates to control the clock signal being input from the external to the flip-flops based on the difference between the logic levels of the output signal of the flip-flop and the input signal newly latched by the flip-flop.
  • the clock signal is prevented from being input to the flip-flops. It results in being able to reduce an idle current flown through the internal circuit of the flip-flop, and to lower the power consumption.
  • the controlling unit serves to supply the clock signal to each flip-flop. Hence, no inverter having a large driving capacity is required, resulting in reducing a through current flown through the inverter when the clock signal is reversed.
  • Fig. 1 shows a circuit diagram showing a typical inverter composed of a digital circuit of CMOS arrangement
  • Fig. 2 shows a timing chart of an example of an input signal.
  • the current consumed in the digital circuit of CMOS arrangement is, in large, divided into a through current and a charge and discharge current.
  • the through current means a current flowing between a power supply and a grounding terminal GND when the two MOS transistors Pch and Nch are switched on at the same time for quite a short time as a result of reversing the input signal ("L (low)” to "H (high)” or "H” to “L”) as shown in Fig. 2.
  • the charge and discharge current means a current flowing when a parasitic capacitance is charged or discharged between a gate electrode of the MOS transistor and the other electrode. It is also generated depending on the change of the electric potential of the input signal.
  • Fig. 3 shows an example of a flip-flop circuit of CMOS arrangement.
  • the present invention is arranged to remove unnecessary reversing of the signal CLOCK, resulting in suppressing the through current and the charge and discharge current to a minimum.
  • Fig. 4 shows a four-bit shift register of CMOS arrangement according to an embodiment of the invention.
  • This shift register is configured to have four synchronous flip-flops 31, 32, 33, 34 which are synchronized with clock signals, NAND gates 51, 52, 53, 54 and exclusive OR gates 61, 62, 63, 64.
  • Each flip flop provides a combination circuit including one exclusive OR gate and one NAND circuit.
  • the two inputs of the exclusive OR gate 61 are respectively connected to a data signal terminal and an output terminal.
  • the output of the exclusive OR gate 61 is connected to one of the input terminals of the NAND gate 51.
  • the other input terminal of the NAND gate 51 is connected to an output terminal of an inverter 35 for supplying a clock signal.
  • the output terminal of the NAND gate 51 is connected to a clock-signal input terminal CKT of the flip-flop 31.
  • each one input of the exclusive OR gates 62, 63, 64 is connected to each data-signal input terminal D of the flip-flops 32, 33, 34.
  • Each of the other inputs of the exclusive OR gates 62, 63, 64 is connected to each of the output terminals Q of the flip-flops 32, 33, 34.
  • Each of the outputs of the exclusive OR gates 62, 63, 64 is connected to each one input of the NAND gates 52, 53, 54.
  • Each of the other inputs of the NAND gates 52, 53, 54 is connected together to the output of the inverter 35.
  • the outputs of the NAND gates 52, 53, 54 are respectively connected to the clock-signal input terminals CKT of the flip-flops 32, 33, 34.
  • the exclusive OR gate 61 serves to supply a high-level output signal N1 to the NAND gate 51, because the two signals input to the exclusive OR gate 61 stay at different logic levels.
  • the clock signal which has been reversed by the inverter 35 is, again, reversed as a clock signal CK1 by the NAND gate 51 and then is input to the flip-flop 31.
  • the flip-flop 31 latches the high-level data signal as being synchronized with a timing T1 corresponding to the first leading edge of the clock signal and then outputs the high-level output signal Q1.
  • the high-level data signal is kept being input to the flip-flop 31.
  • the exclusive OR gate 61 outputs a low-level output signal N1.
  • the clock signal is blocked by the NAND gate 51, so that it is not supplied to the flip-flop 31. That is, in case that the output signal Q1 is at the same logic level as the new input data signal, the clock signal is blocked by the NAND gate 51, so that it is not allowed to be supplied to the flip-flop 31.
  • each of the flip-flops 32 to 34 receives a data signal at the data-signal input terminal D and outputs the corresponding signal of Q2 to Q4 having the same logic level as the input data signal.
  • the exclusive OR gates 62, 63, 64 serve to respectively output the corresponding low-level output signals N2, N3, N4.
  • the clock signal is blocked by the NAND gates 52, 53, 54. It results in being able to prevent flow of an idle charge and discharge current through the internal circuit of each flip-flop.
  • the shift register has another advantage of reducing the current consumption.
  • clock signals CK1 to CK4 are respectively supplied from the NAND gates 51, 52, 53, 54 to the flip-flops 31 to 34.
  • no inverter is required for supplying clock signals to a lot of flip-flops. It results in eliminating the through current in the CMOS transistor composing the inverter when the clock signal is reversed.
  • the foregoing embodiment has been described with respect to the logic circuit including four synchronous flip-flops, four NAND gates and four exclusive OR gates, however, the number of the flip-flop, the NAND gate and the exclusive OR gate is not limited by four. As the number of the flip-flop, the NAND gate and the exclusive OR gate, one, two, three or N which is the number larger than four can be taken.

Abstract

A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external, includes at least one synchronous flip-flop (31, 32, 33, 34) being synchronized with the clock signal, the flip-flop for latching the input signal, and a unit (51, 52, 53, 54, 61, 62, 63, 64) for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a logic circuit which includes at least one synchronous flip-flop.
    • 2. Description of the Related Art
  • The present inventor knows a four-bit shift register as one example of a CMOS (Complementary Metal-Oxide Semiconductor) logic circuit including synchronous flip-flops which are synchronized with clock signals. This four-bit shift register is arranged to have four synchronous D-type flip-flops F1, F2, F3 and F4. The flip-flops F1, F2, F3 and F4 are sequentially connected to each other. That is, the flip-flop F1 is serially connected to the flip-flop F2. The flip-flop F2 is connected serially to the flip-flop F3. The flip-flop F3 is serially connected to the flip-flop F4. Each of synchronous flip-flops is connected to inverters. The inverters supply a clock signal to each flip-flop. In an initial state that each of the flip-flops outputs a low-level signal, when a data signal which is input to the flip-flop F1 rises to a high level, at first, the flip-flop F1 latches the high-level data signal at the leading edge of the clock signal and outputs a high-level output signal H1. The flip-flop F2 latches the high-level signal H1 sent by the flip-flop F1 at the next leading edge of the clock signal and outputs a high-level output signal H2. Likewise, the remaining flip-flops F3 and F4 serve to output their high-level output signals H3 and H4 in the same process as above.
  • Conversely, when the data signal lowers to a low level, those flip-flops F1 to F4 serve to sequentially output the low-level signals L1 to L4 as being synchronized with the clock signals. That is to say, the data signal input to the flip-flop F1 is shifted to the next flip-flops as being synchronized with each leading edge of the clock signals so that the flip-flops F1 to F4 serve to output parallel signals in sequence.
  • The aforementioned shift register is arranged to inevitably receive a clock signal even when the data signal input to each flip-flop has the same logic level as the output signal of each flip-flop, therefore, in case that no flip-flops are required to change their states. The clock signals input to the flip-flops result in flowing a charge and discharge current in internal circuits of the flip-flops, thereby consuming power. It means that such the logic circuit is arranged so that a clock signal is input to the flip-flops of the logic circuit if not necessary, resulting in flowing the idle current in the logic circuit.
  • The shift register needs an inverter arranged to have a CMOS transistor of a large driving capacity, for supplying clock signals to the flip-flops F1 to F4 of the shift register. Such a CMOS transistor having a large driving capacity entails flow of a large through current in internal circuits of the flip-flops when the clock signal is reversed. It is another disadvantage factor of increasing the idle current, that is, of increasing the power consumption.
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a logic circuit which is capable of lowering the power consumption by means of reducing an idle current flown through the logic circuit.
  • The object of the invention can be achieved by a logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external, including:
       at least one synchronous flip-flop being synchronized with the clock signal, the flip-flop for latching the input signal; and
       a unit for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.
  • In operation, the controlling unit operates to control the clock signal being input from the external to the flip-flops based on the difference between the logic levels of the output signal of the flip-flop and the input signal newly latched by the flip-flop. Preferably, when those logic levels are equal to each other, that is, in case that no flip-flops are required to change their states, the clock signal is prevented from being input to the flip-flops. It results in being able to reduce an idle current flown through the internal circuit of the flip-flop, and to lower the power consumption. Further, the controlling unit serves to supply the clock signal to each flip-flop. Hence, no inverter having a large driving capacity is required, resulting in reducing a through current flown through the inverter when the clock signal is reversed.
  • Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
    • Fig. 1 is a circuit diagram showing a typical inverter composed of a digital circuit of CMOS arrangement;
    • Fig. 2 is a timing chart showing an input signal;
    • Fig. 3 is a circuit diagram showing a typical flip-flop circuit of CMOS arrangement;
    • Fig. 4 is a circuit diagram showing a shift register according to an embodiment of the present invention; and
    • Fig. 5 is a timing chart showing operation of the shift register shown in Fig. 4.
    DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In order to give a help of understanding the present invention, before describing embodiments, a general operation of a digital circuit will be described.
  • Fig. 1 shows a circuit diagram showing a typical inverter composed of a digital circuit of CMOS arrangement, and Fig. 2 shows a timing chart of an example of an input signal.
  • The current consumed in the digital circuit of CMOS arrangement is, in large, divided into a through current and a charge and discharge current. In the inverter as shown in Fig. 1, for example, the through current means a current flowing between a power supply and a grounding terminal GND when the two MOS transistors Pch and Nch are switched on at the same time for quite a short time as a result of reversing the input signal ("L (low)" to "H (high)" or "H" to "L") as shown in Fig. 2.
  • The charge and discharge current means a current flowing when a parasitic capacitance is charged or discharged between a gate electrode of the MOS transistor and the other electrode. It is also generated depending on the change of the electric potential of the input signal.
  • Fig. 3 shows an example of a flip-flop circuit of CMOS arrangement.
  • As shown in Fig. 3, in this circuit, when an input clock signal CLOCK is reversed as shown in Fig. 2 and the two MOS transistors 11 and 12 are switched on at the same time for quite a short time, a through current IA which flows between a power supply and a grounding terminal GND is generated. Also, when the two MOS transistors 13 and 14 are switched on at the same time for quite a short time, a through current IB which flows between a power supply and a grounding terminal GND is generated. Even if an input data signal DATA does not change, since the signal CLOCK is reversed, charge and discharge currents flow for charging or discharging the parasitic capacitance of each of MOS transistors 21 to 28.
  • In this arrangement, even if the input data signal DATA does not change or it is not necessary to apply the signal CLOCK to the flip-flop, when the signal CLOCK is reversed, resulting in flowing the through current or the charge and discharge current, thereby consuming large currents.
  • The present invention is arranged to remove unnecessary reversing of the signal CLOCK, resulting in suppressing the through current and the charge and discharge current to a minimum.
  • An embodiment of the present invention will be described in detail with reference to Figs. 4 and 5.
  • Fig. 4 shows a four-bit shift register of CMOS arrangement according to an embodiment of the invention.
  • This shift register is configured to have four synchronous flip- flops 31, 32, 33, 34 which are synchronized with clock signals, NAND gates 51, 52, 53, 54 and exclusive OR gates 61, 62, 63, 64. Each flip flop provides a combination circuit including one exclusive OR gate and one NAND circuit.
  • The two inputs of the exclusive OR gate 61 are respectively connected to a data signal terminal and an output terminal. The output of the exclusive OR gate 61 is connected to one of the input terminals of the NAND gate 51. The other input terminal of the NAND gate 51 is connected to an output terminal of an inverter 35 for supplying a clock signal. The output terminal of the NAND gate 51 is connected to a clock-signal input terminal CKT of the flip-flop 31.
  • The other combination circuits employ the same arrangement. That is to say, each one input of the exclusive OR gates 62, 63, 64 is connected to each data-signal input terminal D of the flip- flops 32, 33, 34. Each of the other inputs of the exclusive OR gates 62, 63, 64 is connected to each of the output terminals Q of the flip- flops 32, 33, 34. Each of the outputs of the exclusive OR gates 62, 63, 64 is connected to each one input of the NAND gates 52, 53, 54. Each of the other inputs of the NAND gates 52, 53, 54 is connected together to the output of the inverter 35. The outputs of the NAND gates 52, 53, 54 are respectively connected to the clock-signal input terminals CKT of the flip- flops 32, 33, 34.
  • In turn, the description will be directed to the operation of the logic circuit with reference to a timing chart of Fig. 5.
  • As shown in Fig. 5, in the timing chart, it is assumed that the output signals Q1, Q2, Q3, Q4 of the flip- flops 31, 32, 33, 34 stay at a low level. When a high-level data signal is input to the flip-flop 31, the exclusive OR gate 61 serves to supply a high-level output signal N1 to the NAND gate 51, because the two signals input to the exclusive OR gate 61 stay at different logic levels. Hence, the clock signal, which has been reversed by the inverter 35 is, again, reversed as a clock signal CK1 by the NAND gate 51 and then is input to the flip-flop 31. As a result, the flip-flop 31 latches the high-level data signal as being synchronized with a timing T1 corresponding to the first leading edge of the clock signal and then outputs the high-level output signal Q1.
  • At the next timing T2 of the clock signal, the high-level data signal is kept being input to the flip-flop 31. In this case, since the output signal Q1 is at a high level, the exclusive OR gate 61 outputs a low-level output signal N1. Hence, the clock signal is blocked by the NAND gate 51, so that it is not supplied to the flip-flop 31. That is, in case that the output signal Q1 is at the same logic level as the new input data signal, the clock signal is blocked by the NAND gate 51, so that it is not allowed to be supplied to the flip-flop 31. Hence, it results in being able to prevent flow of an idle charge and discharge current through an internal circuit of the flip-flop 31.
  • The flip-flops 32 to 34 operate in the same manner. That is, each of the flip-flops 32 to 34 receives a data signal at the data-signal input terminal D and outputs the corresponding signal of Q2 to Q4 having the same logic level as the input data signal. However, in case that the newly input data signal has the same logic level as the output signal of the flip-flop, the exclusive OR gates 62, 63, 64 serve to respectively output the corresponding low-level output signals N2, N3, N4. Hence, the clock signal is blocked by the NAND gates 52, 53, 54. It results in being able to prevent flow of an idle charge and discharge current through the internal circuit of each flip-flop.
  • The shift register has another advantage of reducing the current consumption. In this shift register, clock signals CK1 to CK4 are respectively supplied from the NAND gates 51, 52, 53, 54 to the flip-flops 31 to 34. Unlike the typical shift register described above, no inverter is required for supplying clock signals to a lot of flip-flops. It results in eliminating the through current in the CMOS transistor composing the inverter when the clock signal is reversed.
  • The foregoing embodiment has been described with respect to the logic circuit including four synchronous flip-flops, four NAND gates and four exclusive OR gates, however, the number of the flip-flop, the NAND gate and the exclusive OR gate is not limited by four. As the number of the flip-flop, the NAND gate and the exclusive OR gate, one, two, three or N which is the number larger than four can be taken.
  • Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Claims (4)

  1. A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external, characterized in that said circuit comprises:
       at least one synchronous flip-flop (31, 32, 33, 34) being synchronized with the clock signal, said flip-flop for latching the input signal; and
       means (51, 52, 53, 54, 61, 62, 63, 64) for controlling an input of the clock signal to said flip-flop based on a difference between logic levels of an output signal of said flip-flop and an input signal newly latched by said flip-flop.
  2. A logic circuit according to claim 1, characterized in that said controlling means includes at least one NAND gate (51, 52, 53, 54) and at least one exclusive OR gate (61, 62, 63, 64), said NAND gate and said exclusive OR gate being connected to said flip-flop.
  3. A logic circuit according to claim 2, characterized in that each of said at least one exclusive OR gate has two inputs and an output, each of said at least one NAND gate has two inputs and an output, each of said at least one flip-flop has two inputs and an output, one of said two inputs of said exclusive OR gate for receiving the input signal, the other of said two inputs of said exclusive OR gate being connected to said output of said flip-flop, one of said two inputs of said NAND gate for receiving the clock signal, the other of said two inputs of said NAND gate being connected to said output of said exclusive OR gate, one of said two inputs of said flip-flop being connected to said output of said NAND gate, and the other of said two inputs of said flip-flop receiving the input signal.
  4. A logic circuit for outputting a signal corresponding to an input data signal under the control of an externally supplied clock signal, characterized in that said circuit comprises:
       at least one synchronous flip-flop (31, 32, 33, 34) synchronized with the clock signal for latching the input signal, and
       means (51, 52, 53, 54, 61, 62, 63, 64) for controlling the input of the clock signal to said flip-flop in accordance with a comparison between logic levels of an output signal of said flip-flop and the data signal currently input to said flip-flop.
EP19920301172 1991-07-25 1992-02-13 Logic circuit Withdrawn EP0524712A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3186585A JPH0528789A (en) 1991-07-25 1991-07-25 Logical circuit
JP186585/91 1991-07-25

Publications (2)

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EP0524712A2 true EP0524712A2 (en) 1993-01-27
EP0524712A3 EP0524712A3 (en) 1993-06-30

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EP0524712A3 (en) 1993-06-30
JPH0528789A (en) 1993-02-05

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