EP0517623B1 - Transistor with a predetermined current gain in a bipolar integrated circuit - Google Patents
Transistor with a predetermined current gain in a bipolar integrated circuit Download PDFInfo
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- EP0517623B1 EP0517623B1 EP92420176A EP92420176A EP0517623B1 EP 0517623 B1 EP0517623 B1 EP 0517623B1 EP 92420176 A EP92420176 A EP 92420176A EP 92420176 A EP92420176 A EP 92420176A EP 0517623 B1 EP0517623 B1 EP 0517623B1
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- transistor
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- integrated circuit
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- 239000000758 substrate Substances 0.000 claims description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
Definitions
- the present invention relates to the field of circuits bipolar integrated and more specifically training in a bipolar integrated circuit of transistors presenting gains predetermined relative.
- the present invention will be more particularly exposed in the case of bipolar integrated circuits with insulation by junction.
- Figure 1 shows the basic component of a circuit classic bipolar integrated with junction isolation in the case where the substrate is of type P and where the various elements are formed in type N boxes.
- the integrated circuit is formed from a substrate 1 of monocrystalline semiconductor of a first type of conductivity, for example of P-type silicon. Above this substrate is formed a layer of the opposite type of conductivity, N, generally by epitaxy. It is this layer N which is divided into boxes 2 by deep diffusions of the first type of conductivity 3 joining the substrate 1 from the surface of the wafer. Commonly, the bottom of the box comprises a buried region 4 of the second type of conductivity with a high doping level. An NPN transistor formed in the box 2 comprises a collector region which corresponds to the box 2. A collector contact C is made on this region 2 via an overdoped area 6.
- a region in a P-type bowl 7 which will correspond to the base of the NPN transistor. Inside the base region, an emitter N + region 8 is formed. A base contact B is formed on the region 7. An emitter metallization E is formed on the emitter region 8.
- the doping levels, the junction depths and the concentration gradients at the emitter-base and base-collector junctions determine the characteristics of the NPN transistor obtained and in particular its current gain and its breakdown voltage BV CEO .
- NPN transistors having current gains different from those represented in FIG. 1 it will be necessary to modify one of their characteristics, for example the doping of their base or of their emitter, but then these second transistors will not have not, in different manufacturing batches, gains determined with precision compared to the first transistors.
- NPN transistors modified from first have already been made in the prior art, for example as described in JP-A-57 106 160 (Hitachi), FR-A-2 101 228 (IBM) or FR-A-2 282 721 (RCA).
- IBM patent a normal transistor and a transistor with very low current gain are gathered in the same box and the transistor at very low gain is intended to operate as a diode, this diode possibly being connected by its anode to the base of the transistor normal. None of these documents describes a new determined gain transistor consisting of two transistors interconnected elementaries.
- An object of the present invention is to provide, in a bipolar integrated circuit comprising first transistors "normal" bipolar, second bipolar transistors with respect to the former a determined gain ratio regardless of variations in manufacturing parameters and of the temperature.
- the present invention provides to form in the same well a first bipolar transistor "normal” elementary and a second bipolar transistor elementary with very heavily doped base, bases and emitters of these two transistors being interconnected.
- a bipolar transistor having, with respect to the transistors normal bipolar of the circuit, a current gain of 1 / k + 1, we provides that, in a given well, the elementary transistor very heavily doped base has an emitter surface k times higher than that of the normal elementary transistor.
- the present invention provides a bipolar integrated circuit with boxes of a first type of conductivity formed in a substrate of the second type of conductivity, comprising in first boxes first transistors whose box constitutes the collector inside from which a base region of the second type of conductivity is formed itself containing an emitter region of the first type conductivity.
- This integrated circuit includes, in at least one second collector box, a second transistor consisting of a third elementary transistor comprising regions with the same doping as the first transistors and a fourth elementary transistor having a base region at high doping level compared to that of the bases of the first transistors and an emitter region of the same doping level than that of the first transistors, the transmitters and the bases third and fourth transistors being interconnected and constituting respectively the transmitter and the base of the second transistor.
- the present invention provides a circuit integrated bipolar comprising in insulated boxes forming collector of the first transistors and a second transistor presenting with respect to the former a current gain in a ratio 1 / k + 1, this second transistor being constituted by the parallel connection of a third and a fourth transistor elementary formed in the same collector box, the third transistor being identical to the first and the fourth transistor having a base very strongly doped by compared to the former and a transmitter of the same doping, the surface emitter of the fourth transistor being k times larger than that of the third.
- the boxes are insulated by junction and the bottom of each box includes a buried layer of the first type of conductivity at high level of doping.
- the bases fourth transistors are about a thousand times more doped per unit area than the bases of the first transistors.
- the bases third and fourth transistors are adjacent.
- FIG. 2 represents an NPN transistor, E'B'C ', with predetermined gain according to the present invention.
- a second base region 11 and a second emitter region 12 are provided to form a second elementary emitter transistor E 2 , base B 2 and collector C '.
- the doping levels of the base and emitter layers 7 and 8 of the elementary transistor E 1 B 1 C ' are strictly identical to those of the transistor of FIG. 1.
- the base region 11 is strongly doped with respect to the base region 7.
- the emitter region 12 has the same doping level as the emitter region 8.
- the bases B 1 and B 2 are interconnected, either externally or by metallizations on the component, to form the base B 'of the predetermined gain transistor and the emitter regions E 1 and E 2 are interconnected to form the emitter E' of the predetermined gain transistor.
- the ratio k between the area of the emitter region 8 and the area of the emitter region 12 is determined from the way exposed below to fix the gain of the transistor.
- the current gain of a transistor equal to the ratio between the collector current and the base current is therefore equal to the ratio of the Gummel numbers of the transmitter and the base (it will be high if this ratio is high).
- the gain is not equal but directly related to the ratio of the numbers of Gummel. This note does not affect the explanations below where we consider transistors with the same emitter doping.
- the base current will be the same because the number of Gummel of transmitters is the same.
- the collector current will be very low, for example much lower than the base current because the Gummel number of the second base is very large. The second transistor therefore has a very low current gain.
- a new transistor was thus produced having a gain determined relative to that of the "normal" transistors, the new gain being fixed by the ratio between the emitter surfaces, a parameter which is adjustable in a simple and reliable manner in an integrated circuit since it only depends on the surface of masks and not on technological parameters.
- the two elementary transistors E 2 B 2 C 'and E 1 B 1 C' are produced in the same box, these two transistors will see their parameters vary in the same way as a function of temperature variations and the ratio between the gain of the transistor according to the invention and the gain of the conventional transistor will remain constant with temperature variations.
- the present invention proposes a new type of bipolar component constituting a gain transistor determined and adjustable compared to the other transistors of the circuit. We can if we wish to multiply in the same bipolar integrated circuit of separate gain transistors this which allows those skilled in the art to create new types of circuits in a simple way.
- Figures 4 and 5 show in section and in view of above a variant of the present invention.
- the regions of base 7 and 11, instead of being separate, are adjacent.
- the transistor E 1 B 1 C ' has a gain of the order of 50 to 500 and the transistor E 2 B 2 C' a gain of less than 0.1.
- the ratio between the amounts of dopant in the bases 11 and 8 can reach values of the order of 1000.
- the present invention is capable of many variants which will appear to those skilled in the art. Especially, all the improvements usually applied to NPN transistor structures may be used.
- all the improvements usually applied to NPN transistor structures may be used.
- box structures bipolar with junction isolation have been shown here, the invention would also apply to boxes insulated by dielectric.
- each of the elements has been described and shown in simplified form. So there will generally be isolation layers not shown and possibly overdoped regions of resumption of contact ...
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Description
La présente invention concerne le domaine des circuits intégrés bipolaires et plus particulièrement la formation dans un circuit intégré bipolaire de transistors présentant des gains relatifs prédéterminés.The present invention relates to the field of circuits bipolar integrated and more specifically training in a bipolar integrated circuit of transistors presenting gains predetermined relative.
La présente invention sera plus particulièrement exposée dans le cas de circuits intégrés bipolaires à isolement par jonction.The present invention will be more particularly exposed in the case of bipolar integrated circuits with insulation by junction.
Dans un circuit intégré, on utilise de très nombreux composants identiques assemblés de diverses façons en divers circuits. Tous les composants sont fabriqués à l'identique pour que les caractéristiques des circuits obtenus à partir de ces composants soient déterminables. En effet, dans un circuit intégré classique, si, par exemple, on utilise deux types distincts de transistors NPN, tous les transistors d'un type donné auront des caractéristiques déterminées mais les relations entre les caractéristiques de transistors du premier type et de transistors du deuxième type seront généralement sujettes à variation en fonction des variations de la technologie de fabrication (notamment variation des niveaux de dopage des diverses couches et des profondeurs de diffusion liées aux recuits). In an integrated circuit, we use very many identical components assembled in various ways in various circuits. All components are manufactured identically for that the characteristics of the circuits obtained from these components are determinable. Indeed, in an integrated circuit classic, if, for example, we use two distinct types of NPN transistors, all transistors of a given type will have specific characteristics but the relationships between characteristics of transistors of the first type and of transistors of the second type will generally be subject to variation according to variations in manufacturing technology (in particular variation of the doping levels of the various layers and diffusion depths linked to annealing).
La figure 1 représente le composant de base d'un circuit intégré bipolaire classique à isolement par jonction dans le cas où le substrat est de type P et où les divers éléments sont formés dans des caissons de type N.Figure 1 shows the basic component of a circuit classic bipolar integrated with junction isolation in the case where the substrate is of type P and where the various elements are formed in type N boxes.
Le circuit intégré est formé à partir d'un substrat 1
en semiconducteur monocristallin d'un premier type de conductivité,
par exemple du silicium de type P. Au-dessus de ce substrat
est formée une couche du type de conductivité opposé, N,
généralement par épitaxie. C'est cette couche N qui est divisée
en caissons 2 par des diffusions profondes du premier type de
conductivité 3 rejoignant le substrat 1 à partir de la surface
de la plaquette. Couramment, le fond du caisson comprend une
région enterrée 4 du deuxième type de conductivité à fort niveau
de dopage. Un transistor NPN formé dans le caisson 2 comprend
une région de collecteur qui correspond au caisson 2. Un contact
de collecteur C est pris sur cette région 2 par l'intermédiaire
d'une zone surdopée 6. A partir de la surface du caisson, est
formée par implantation/diffusion une région en cuvette 7 de
type P qui correspondra à la base du transistor NPN. A l'intérieur
de la région de base, est formée une région N+ d'émetteur
8. Un contact de base B est formé sur la région 7. Une métallisation
d'émetteur E est formée sur la région d'émetteur 8.The integrated circuit is formed from a
Les niveaux de dopage, les profondeurs de jonction et les gradients de concentration au niveau des jonctions émetteur-base et base-collecteur déterminent les caractéristiques du transistor NPN obtenu et notamment son gain en courant et sa tension de claquage BVCEO. Normalement, pour fabriquer des transistors NPN présentant des gains en courant différents de ceux représentés en figure 1, il faudra modifier l'une de leurs caractéristiques, par exemple le dopage de leur base ou de leur émetteur, mais alors ces deuxièmes transistors n'auront pas, dans des lots de fabrication différents, des gains déterminés avec précision par rapport aux premiers transistors. The doping levels, the junction depths and the concentration gradients at the emitter-base and base-collector junctions determine the characteristics of the NPN transistor obtained and in particular its current gain and its breakdown voltage BV CEO . Normally, to manufacture NPN transistors having current gains different from those represented in FIG. 1, it will be necessary to modify one of their characteristics, for example the doping of their base or of their emitter, but then these second transistors will not have not, in different manufacturing batches, gains determined with precision compared to the first transistors.
De tels transistors NPN modifiés par rapport aux premiers ont déjà été réalisés dans l'art antérieur, par exemple comme cela est décrit dans JP-A-57 106 160 (Hitachi), FR-A-2 101 228 (IBM) ou FR-A-2 282 721 (RCA). Dans le brevet IBM, un transistor normal et un transistor à très faible gain en courant sont rassemblés dans un même caisson et le transistor à très faible gain est destiné à fonctionner en diode, cette diode étant éventuellement reliée par son anode à la base du transistor normal. Aucun de ces documents ne décrit un nouveau transistor à gain déterminé constitué de deux transistors élémentaires interconnectés.Such NPN transistors modified from first have already been made in the prior art, for example as described in JP-A-57 106 160 (Hitachi), FR-A-2 101 228 (IBM) or FR-A-2 282 721 (RCA). In the IBM patent, a normal transistor and a transistor with very low current gain are gathered in the same box and the transistor at very low gain is intended to operate as a diode, this diode possibly being connected by its anode to the base of the transistor normal. None of these documents describes a new determined gain transistor consisting of two transistors interconnected elementaries.
Un objet de la présente invention est de prévoir, dans un circuit intégré bipolaire comprenant des premiers transistors bipolaires "normaux", des deuxièmes transistors bipolaires présentant par rapport aux premiers un rapport de gain déterminé indépendamment des variations des paramètres de fabrication et de la température.An object of the present invention is to provide, in a bipolar integrated circuit comprising first transistors "normal" bipolar, second bipolar transistors with respect to the former a determined gain ratio regardless of variations in manufacturing parameters and of the temperature.
Pour atteindre cet objet, la présente invention prévoit de former dans un même caisson un premier transistor bipolaire élémentaire "normal" et un deuxième transistor bipolaire élémentaire à base très fortement dopée, les bases et les émetteurs de ces deux transistors étant interconnectés. Pour obtenir un transistor bipolaire présentant, par rapport aux transistors bipolaires normaux du circuit, un gain en courant de 1/k+1, on prévoit que, dans un caisson donné, le transistor élémentaire à base très fortement dopée présente une surface d'émetteur k fois plus élevée que celle du transistor élémentaire normal.To achieve this object, the present invention provides to form in the same well a first bipolar transistor "normal" elementary and a second bipolar transistor elementary with very heavily doped base, bases and emitters of these two transistors being interconnected. To get a bipolar transistor having, with respect to the transistors normal bipolar of the circuit, a current gain of 1 / k + 1, we provides that, in a given well, the elementary transistor very heavily doped base has an emitter surface k times higher than that of the normal elementary transistor.
Plus particulièrement, la présente invention prévoit un circuit intégré bipolaire à caissons d'un premier type de conductivité formés dans un substrat du deuxième type de conductivité, comprenant dans des premiers caissons des premiers transistors dont le caisson constitue le collecteur à l'intérieur duquel est formée une région de base du deuxième type de conductivité contenant elle-même une région d'émetteur du premier type de conductivité. Ce circuit intégré comprend, dans au moins un deuxième caisson formant collecteur, un deuxième transistor constitué d'un troisième transistor élémentaire comprenant des régions de même dopage que les premiers transistors et d'un quatrième transistor élémentaire ayant une région de base à niveau de dopage élevé devant celui des bases des premiers transistors et une région d'émetteur de même niveau de dopage que celui des premiers transistors, les émetteurs et les bases des troisième et quatrième transistors étant interconnectés et constituant respectivement l'émetteur et la base du second transistor.More particularly, the present invention provides a bipolar integrated circuit with boxes of a first type of conductivity formed in a substrate of the second type of conductivity, comprising in first boxes first transistors whose box constitutes the collector inside from which a base region of the second type of conductivity is formed itself containing an emitter region of the first type conductivity. This integrated circuit includes, in at least one second collector box, a second transistor consisting of a third elementary transistor comprising regions with the same doping as the first transistors and a fourth elementary transistor having a base region at high doping level compared to that of the bases of the first transistors and an emitter region of the same doping level than that of the first transistors, the transmitters and the bases third and fourth transistors being interconnected and constituting respectively the transmitter and the base of the second transistor.
Ainsi, la présente invention prévoit un circuit
intégré bipolaire comprenant dans des caissons isolés formant
collecteur des premiers transistors et un deuxième transistor
présentant par rapport aux premiers un gain en courant dans un
rapport 1/k+1, ce deuxième transistor étant constitué par la
connexion en parallèle d'un troisième et d'un quatrième transistor
élémentaire formés dans un même caisson de collecteur, le
troisième transistor étant identique aux premiers et le
quatrième transistor ayant une base très fortement dopée par
rapport aux premiers et un émetteur de même dopage, la surface
d'émetteur du quatrième transistor étant k fois plus grande que
celle du troisième.Thus, the present invention provides a circuit
integrated bipolar comprising in insulated boxes forming
collector of the first transistors and a second transistor
presenting with respect to the former a current gain in a
Selon un mode de réalisation de l'invention, les caissons sont isolés par jonction et le fond de chaque caisson comprend une couche enterrée du premier type de conductivité à haut niveau de dopage.According to one embodiment of the invention, the boxes are insulated by junction and the bottom of each box includes a buried layer of the first type of conductivity at high level of doping.
Selon un mode de réalisation de l'invention, les bases des quatrièmes transistors sont environ mille fois plus dopées par unité de surface que les bases des premiers transistors.According to one embodiment of the invention, the bases fourth transistors are about a thousand times more doped per unit area than the bases of the first transistors.
Selon un mode de réalisation de l'invention, les bases des troisième et quatrième transistors sont adjacentes. According to one embodiment of the invention, the bases third and fourth transistors are adjacent.
Ces objets, caractéristiques et avantages ainsi que
d'autres de la présente invention seront exposés en détail dans
la description suivante de modes de réalisation particuliers
faite en relation avec les dessins joints parmi lesquels :
Dans les figures 1, 2, 4 et 5, les diverses couches ne sont pas représentées à l'échelle, leurs dimensions étant arbitrairement agrandies ou rétrécies pour améliorer la lisibilité des figures, comme cela est classique dans le domaine de la représentation des composants semiconducteurs. De plus, les formes des couches ne correspondent pas aux formes réelles. Notamment, les divers bords et coins de couches représentés comme rectangulaires sont en fait arrondis par suite des diverses étapes de diffusion et de recuit. En outre, dans ces figures, les régions ou zones identiques ou équivalentes sont désignées par les mêmes références numériques.In Figures 1, 2, 4 and 5, the various layers do not are not shown to scale, their dimensions being arbitrarily enlarged or shrunk to improve readability figures, as is classic in the field of representation of semiconductor components. Moreover, the layer shapes do not match actual shapes. In particular, the various edges and corners of layers represented as rectangular are actually rounded as a result of various stages of diffusion and annealing. Furthermore, in these figures, identical or equivalent regions or areas are designated by the same reference numerals.
La figure 2 représente un transistor NPN, E'B'C', à
gain prédéterminé selon la présente invention. Une structure
E1B1C' équivalente à la stucture EBC de la figure 1, constitue
un premier transistor élémentaire. En outre, dans le même
caisson, sont prévues une deuxième région de base 11 et une
deuxième région d'émetteur 12 pour former un deuxième transistor
élémentaire d'émetteur E2, de base B2 et de collecteur C'. FIG. 2 represents an NPN transistor, E'B'C ', with predetermined gain according to the present invention. A structure E 1 B 1 C ′ equivalent to the structure EBC of FIG. 1, constitutes a first elementary transistor. In addition, in the same box, a
Les niveaux de dopage des couches de base et d'émetteur
7 et 8 du transistor élémentaire E1B1C' sont strictement
identiques à celles du transistor de la figure 1. Par contre, la
région de base 11 est fortement dopée par rapport à la région de
base 7. La région d'émetteur 12 présente le même niveau de
dopage que la région d'émetteur 8. Les bases B1 et B2 sont
interconnectées, ou bien de façon externe ou bien par des métallisations
sur le composant, pour former la base B' du transistor
à gain prédéterminé et les régions d'émetteur E1 et E2 sont
interconnectées pour former l'émetteur E' du transistor à gain
prédéterminé.The doping levels of the base and
Le rapport k entre la surface de la région d'émetteur
8 et la surface de la région d'émetteur 12 est déterminé de la
façon exposée ci-après pour fixer le gain du transistor.The ratio k between the area of the
On va d'abord rappeler les mécanismes qui fixent le gain en courant d'un transistor.We will first recall the mechanisms that fix the current gain of a transistor.
Quand une tension VBE est appliquée entre base et émetteur d'un transistor, il se crée deux flux de porteurs.
- L'émetteur injecte dans la base un flux de porteurs inversement proportionnel au nombre de Gummel de cette base (le nombre de Gummel est le nombre d'atomes dopants introduits par unité de surface dans chaque région du transistor). Dans un transistor présentant des valeurs de dopage classiques tel que celui de la figure 1, pratiquement tous ces porteurs traversent la base et constituent le courant de collecteur.
- La base injecte dans l'émetteur un flux de porteurs inversement proportionnel au nombre de Gummel de l'émetteur. Ces porteurs constituent la quasi-totalité du courant de base.
- The transmitter injects into the base a flux of carriers inversely proportional to the number of Gummels of this base (the number of Gummels is the number of doping atoms introduced per unit area in each region of the transistor). In a transistor exhibiting conventional doping values such as that of FIG. 1, practically all of these carriers pass through the base and constitute the collector current.
- The base injects into the transmitter a flow of carriers inversely proportional to the Gummel number of the transmitter. These carriers constitute almost all of the basic current.
Le gain en courant d'un transistor, égal au rapport entre le courant de collecteur et le courant de base est donc égal au rapport des nombres de Gummel de l'émetteur et de la base (il sera élevé si ce rapport est élevé). En fait, il s'agit là d'une explication simplifiée et des facteurs correcteurs doivent être appliqués, notamment pour tenir compte des forts dopages d'émetteur. En conséquence il faut noter que le gain n'est pas égal mais directement lié au rapport des nombres de Gummel. Cette remarque n'affecte pas les explications ci-après où l'on considère des transistors de même dopage d'émetteur.The current gain of a transistor, equal to the ratio between the collector current and the base current is therefore equal to the ratio of the Gummel numbers of the transmitter and the base (it will be high if this ratio is high). In fact, it is there a simplified explanation and corrective factors must be applied, in particular to take account of strong transmitter doping. Consequently, it should be noted that the gain is not equal but directly related to the ratio of the numbers of Gummel. This note does not affect the explanations below where we consider transistors with the same emitter doping.
Si l'on compare le transistor élémentaire B2E2C' au transistor élémentaire B1E1C', pour une même tension base-émetteur, et de mêmes surfaces d'émetteurs, le courant de base sera le même car le nombre de Gummel des émetteurs est le même. Toutefois, pour le transistor élémentaire B2E2C', le courant collecteur sera très faible, par exemple nettement inférieur au courant de base car le nombre de Gummel de la seconde base est très grand. Le deuxième transistor présente donc un gain en courant très faible.If we compare the elementary transistor B 2 E 2 C 'to the elementary transistor B 1 E 1 C', for the same base-emitter voltage, and the same emitter surfaces, the base current will be the same because the number of Gummel of transmitters is the same. However, for the elementary transistor B 2 E 2 C ′, the collector current will be very low, for example much lower than the base current because the Gummel number of the second base is very large. The second transistor therefore has a very low current gain.
Si l'on considère le transistor E'B'C' constitué de
l'association en parallèle des transistors E1B1C' et E2B2C', et
que l'on injecte un courant IB dans la borne de base B', ce
courant se répartira également entre les deux transistors
puisque les émetteurs de ces deux transistors ont le même nombre
de Gummel. Ainsi il circulera un courant de base moitié dans le
transistor E1B1C' qui donc présentera un courant collecteur
moitié de celui qu'il aurait en l'absence du transistor E2B2C'.
Comme le courant de collecteur du transistor E2B2C' est pratiquement
nul, le gain en courant du transistor E'B'C' de la
figure 2 est donc divisé par 2 par rapport à celui du transistor
EBC de la figure 1. Plus généralement, si le rapport entre les
surfaces des régions d'émetteur 8 et 12 est égal à k, le gain du
transistor E'B'C' sera égal à 1/k+1 fois le gain du transistor
EBC de la figure 1.If we consider the transistor E'B'C 'consisting of the association in parallel of the transistors E 1 B 1 C' and E 2 B 2 C ', and that we inject a current I B in the terminal of base B ', this current will be equally distributed between the two transistors since the emitters of these two transistors have the same Gummel number. Thus a basic current will flow half in the transistor E 1 B 1 C 'which will therefore present a collector current half of that which it would have in the absence of the transistor E 2 B 2 C'. As the collector current of the transistor E 2 B 2 C 'is practically zero, the current gain of the transistor E'B'C' of FIG. 2 is therefore divided by 2 compared to that of the EBC transistor of FIG. 1. More generally, if the ratio between the surfaces of the
On a ainsi réalisé un nouveau transistor présentant un gain déterminé par rapport à celui des transistors "normaux", le nouveau gain étant fixé par le rapport entre les surfaces d'émetteur, paramètre qui est réglable de façon simple et fiable en circuit intégré puisqu'il dépend seulement de la surface de masques et non de paramètres technologiques. En outre, puisque les deux transistors élémentaires E2B2C' et E1B1C' sont réalisés dans un même caisson, ces deux transistors verront leurs paramètres varier de la même façon en fonction des variations de température et le rapport entre le gain du transistor selon l'invention et le gain du transistor classique restera constant avec les variations de température.A new transistor was thus produced having a gain determined relative to that of the "normal" transistors, the new gain being fixed by the ratio between the emitter surfaces, a parameter which is adjustable in a simple and reliable manner in an integrated circuit since it only depends on the surface of masks and not on technological parameters. In addition, since the two elementary transistors E 2 B 2 C 'and E 1 B 1 C' are produced in the same box, these two transistors will see their parameters vary in the same way as a function of temperature variations and the ratio between the gain of the transistor according to the invention and the gain of the conventional transistor will remain constant with temperature variations.
Ainsi, la présente invention propose un nouveau type de composant bipolaire constituant un transistor de gain déterminé et ajustable par rapport aux autres transistors du circuit. On pourra si on le souhaite multiplier dans un même circuit intégré bipolaire des transistors de gains distincts ce qui permet à l'homme de l'art de créer de nouveaux types de circuits de façon simple.Thus, the present invention proposes a new type of bipolar component constituting a gain transistor determined and adjustable compared to the other transistors of the circuit. We can if we wish to multiply in the same bipolar integrated circuit of separate gain transistors this which allows those skilled in the art to create new types of circuits in a simple way.
Les figures 4 et 5 représentent en coupe et en vue de
dessus une variante de la présente invention. Les régions de
base 7 et 11, au lieu d'être disjointes, sont adjacentes.Figures 4 and 5 show in section and in view of
above a variant of the present invention. The regions of
A titre d'exemple de niveaux de dopage, on pourra prévoir,
pour les diverses régions d'un transistor selon l'invention
les niveaux de dopage ou valeurs de résistance (r) en ohms
par carré et profondeur de jonction (x) en micromètres, les
valeurs suivantes :
Avec des valeurs de cet ordre, le transistor E1B1C' a un gain de l'ordre de 50 à 500 et le transistor E2B2C' un gain inférieur à 0,1.With values of this order, the transistor E 1 B 1 C 'has a gain of the order of 50 to 500 and the transistor E 2 B 2 C' a gain of less than 0.1.
Le rapport entre les quantités de dopant dans les
bases 11 et 8 pourra atteindre des valeurs de l'ordre de 1000.The ratio between the amounts of dopant in the
Bien entendu, la présente invention est susceptible de nombreuses variantes qui apparaítront à l'homme de l'art. Notamment, tous les perfectionnements habituellement appliqués aux structures de transistors NPN pourront être utilisés. Par exemple, alors que seules des structures classiques de caissons bipolaires à isolement par jonction ont été représentées ici, l'invention s'appliquerait également à des caissons isolés par diélectrique. De plus, chacun des éléments a été décrit et représenté de façon simplifiée. Ainsi, il existera généralement des couches superficielles d'isolement non représentées et éventuellement des régions surdopées de reprise de contact...Of course, the present invention is capable of many variants which will appear to those skilled in the art. Especially, all the improvements usually applied to NPN transistor structures may be used. By example, while only conventional box structures bipolar with junction isolation have been shown here, the invention would also apply to boxes insulated by dielectric. In addition, each of the elements has been described and shown in simplified form. So there will generally be isolation layers not shown and possibly overdoped regions of resumption of contact ...
Claims (5)
- A bipolar integrated circuit with wells (2) of a first conductivity type, formed in a substrate (1) of the second conductivity type, comprising, in first wells, first transistors (EBC), the well of which constitutes the collector inside which is formed a base region (7) of the second conductivity type containing in turn an emitter region (8) of the first conductivity type, characterized in that it comprises, in at least a second well forming a collector, a second transistor (E'B'C') constituted by a third elementary transistor (E1B1C') comprising regions of the same doping level as the first transistors and a fourth elementary transistor (E2B2C') having a base region (11) with a high doping level with respect to that of the bases of the first transistors and an emitter region (12) having the same doping level as that of said first transistors, the emitters and bases of the third and fourth elementary transistors being interconnected and constituting the emitter and the base of the second transistor, respectively.
- A bipolar integrated circuit according to claim 1, characterized in that, the emitter surface of said fourth transistor is k times larger than that of said third transistor, whereby the second transistor (E'B'C) has a current gain that is 1/K+1 times the current gain of the first transistors.
- A bipolar integrated circuit according to claim 1 or 2, wherein said wells are isolated by junction and the bottom of each said well comprises a buried layer of the first conductivity type having a high doping level.
- A bipolar integrated circuit according to any of claims 1 to 3, wherein the bases of said fourth transistors are a thousand times more doped per surface unit than the bases of said first transistors.
- A bipolar integrated circuit according to any of claims 1 to 4, wherein the bases of the third and fourth transistors are adjacent.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9106896A FR2677171B1 (en) | 1991-05-31 | 1991-05-31 | PREDETERMINED CURRENT GAIN TRANSISTOR IN A BIPOLAR INTEGRATED CIRCUIT. |
| FR9106896 | 1991-05-31 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0517623A2 EP0517623A2 (en) | 1992-12-09 |
| EP0517623A3 EP0517623A3 (en) | 1994-08-10 |
| EP0517623B1 true EP0517623B1 (en) | 1998-05-06 |
Family
ID=9413563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP92420176A Expired - Lifetime EP0517623B1 (en) | 1991-05-31 | 1992-05-26 | Transistor with a predetermined current gain in a bipolar integrated circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5481132A (en) |
| EP (1) | EP0517623B1 (en) |
| JP (1) | JP3313398B2 (en) |
| DE (1) | DE69225355T2 (en) |
| FR (1) | FR2677171B1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE516226C2 (en) * | 1995-04-10 | 2001-12-03 | Forskarpatent I Linkoeping Ab | Bipolar transistors with extra base-collector and base-emitter structures |
| JPH0945702A (en) * | 1995-05-19 | 1997-02-14 | Toshiba Corp | Semiconductor device |
| JPH10270567A (en) * | 1997-03-21 | 1998-10-09 | Oki Electric Ind Co Ltd | Transistor protective element |
| JP2001060668A (en) * | 1999-07-01 | 2001-03-06 | Intersil Corp | BiCMOS PROCESS IMPROVED BY RESISTOR WITH SMALL TEMPERATURE COEFFICIENT OF RESISOTOR (TCRL) |
| US6798024B1 (en) * | 1999-07-01 | 2004-09-28 | Intersil Americas Inc. | BiCMOS process with low temperature coefficient resistor (TCRL) |
| US7064416B2 (en) * | 2001-11-16 | 2006-06-20 | International Business Machines Corporation | Semiconductor device and method having multiple subcollectors formed on a common wafer |
| JP4179292B2 (en) * | 2005-02-21 | 2008-11-12 | サンケン電気株式会社 | Semiconductor device |
| DE102005027368A1 (en) * | 2005-06-14 | 2006-12-28 | Atmel Germany Gmbh | Semiconductor protection structure for electrostatic discharge |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3393349A (en) * | 1964-04-30 | 1968-07-16 | Motorola Inc | Intergrated circuits having isolated islands with a plurality of semiconductor devices in each island |
| US3504203A (en) * | 1966-05-19 | 1970-03-31 | Sprague Electric Co | Transistor with compensated depletion-layer capacitance |
| DE1764241C3 (en) * | 1968-04-30 | 1978-09-07 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithically integrated semiconductor circuit |
| US3573573A (en) * | 1968-12-23 | 1971-04-06 | Ibm | Memory cell with buried load impedances |
| US3770519A (en) * | 1970-08-05 | 1973-11-06 | Ibm | Isolation diffusion method for making reduced beta transistor or diodes |
| DE2137976C3 (en) * | 1971-07-29 | 1978-08-31 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithic memory and method of manufacture |
| IN141922B (en) * | 1974-08-19 | 1977-05-07 | Rca Corp | |
| US4258379A (en) * | 1978-09-25 | 1981-03-24 | Hitachi, Ltd. | IIL With in and outdiffused emitter pocket |
| JPS57106160A (en) * | 1980-12-24 | 1982-07-01 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1991
- 1991-05-31 FR FR9106896A patent/FR2677171B1/en not_active Expired - Fee Related
-
1992
- 1992-05-26 DE DE69225355T patent/DE69225355T2/en not_active Expired - Fee Related
- 1992-05-26 EP EP92420176A patent/EP0517623B1/en not_active Expired - Lifetime
- 1992-05-29 JP JP13868592A patent/JP3313398B2/en not_active Expired - Fee Related
-
1993
- 1993-11-18 US US08/154,379 patent/US5481132A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69225355D1 (en) | 1998-06-10 |
| EP0517623A3 (en) | 1994-08-10 |
| JPH05198584A (en) | 1993-08-06 |
| JP3313398B2 (en) | 2002-08-12 |
| FR2677171A1 (en) | 1992-12-04 |
| DE69225355T2 (en) | 1998-11-19 |
| FR2677171B1 (en) | 1994-01-28 |
| EP0517623A2 (en) | 1992-12-09 |
| US5481132A (en) | 1996-01-02 |
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