EP0517415A1 - Personalcomputer mit verbessertem Speicherzugriff und Verfahren - Google Patents

Personalcomputer mit verbessertem Speicherzugriff und Verfahren Download PDF

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Publication number
EP0517415A1
EP0517415A1 EP92304748A EP92304748A EP0517415A1 EP 0517415 A1 EP0517415 A1 EP 0517415A1 EP 92304748 A EP92304748 A EP 92304748A EP 92304748 A EP92304748 A EP 92304748A EP 0517415 A1 EP0517415 A1 EP 0517415A1
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EP
European Patent Office
Prior art keywords
data
banks
bus
high speed
pages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92304748A
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English (en)
French (fr)
Inventor
Jorge Eduardo Lenta
Esmaeil Tashakori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0517415A1 publication Critical patent/EP0517415A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Definitions

  • This invention relates to a personal computer having enhanced memory access performance.
  • the invention contemplates that such enhanced performance will be attained by distributing memory locations used in accordance with a particular scheme, in which consecutive pages of data are placed in memory in different physical banks.
  • 'IBM' is a registered trade mark of International Business Machines Corporation.
  • Personal computer systems can usually be defined as a desk top, floor standing, or portable microcomputer that consists of a system unit having a single system processor and associated volatile and non-volatile memory, a display monitor, a keyboard, one or more diskette drives, a fixed disk storage, and an optional printer.
  • One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to electrically connect these components together.
  • Such personal computer systems are IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM/2 Models 25, 30, L40SX, 50, 55, 65, 70, 80, 90 and 95. ('Personal System/2' is a trade mark of International Business Machines Corporation).
  • the first family usually referred to as Family I Models, use a bus architecture exemplified by the IBM PERSONAL COMPUTER AT and other "IBM compatible" machines.
  • the second family referred to as Family II Models, use IBM's MICRO CHANNEL bus architecture exemplified by IBM's PERSONAL SYSTEM/2 Models 50 through 95.
  • 'MICRO CHANNEL' is a trade mark of International Business Machines Corporation.
  • the Family I models typically have used the popular INTEL 8088 or 8086 microprocessor as the system processor. ('INTEL' is a trade mark of Intel Corporation). These processors have the ability to address one megabyte of memory.
  • the Family II models typically use the high speed INTEL 80286, 80386, and 80486 microprocessors which can operate in a real mode to emulate the slower speed INTEL 8086 microprocessor or a protected mode which extends the addressing range from 1 megabyte to 4 Gigabytes for some models.
  • the real mode feature of the 80286, 80386, and 80486 processors provide hardware compatibility with software written for the 8086 and 8088 microprocessors.
  • DRAM dynamic random access memory
  • processors in high performance personal computers such as some of those mentioned above are capable of processing data more quickly than data can be accessed from conventional dynamic random access memory (DRAM) using conventional data storage technology.
  • DRAM is organised in banks and pages, with each bank being made up of a number of pages. For example only, a one megabyte DRAM will conventionally have pages of two kilobytes.
  • DRAM has been used in page mode and with successive pages stored at successive locations in a given bank until that bank is filled and storage must move to another bank. In such a mode, when a page of memory is accessed by a read or write operation, bytes of data stored in the same page can be accessed in the shortest permissible time interval.
  • the present invention provides a personal computer system comprising: a high speed data bus; a microprocessor coupled directly to the high speed data bus; volatile memory coupled directly to the high speed data bus and organised in banks and pages for receiving data to be written thereto and for storing therein data to be read therefrom; and a bus interface controller coupled directly to the high speed data bus for providing communications between the high speed data bus and an input/output data bus and for signalling row and column addresses to the volatile memory, the signals determining the physical locations in the banks and rows of data written thereto, stored therein and read therefrom; characterised in that the bus interface controller directs that logically successive pages of data are stored in physically separate banks.
  • the present invention provides a method of operating a personal computer which has a high speed data bus, a microprocessor coupled directly to the high speed data bus, volatile memory coupled directly to the high speed data bus and organised in banks and pages for receiving data to be written thereto and for storing therein data to be read therefrom, and a bus interface controller coupled directly to the high speed data bus, the method comprising the steps of: signalling row and column addresses to the volatile memory from the bus interface controller for determining the physical location in the banks and rows of data written thereto, stored therein and read therefrom; and directing that logically successive pages of data are stored in physically separate banks.
  • the number of wait state cycles imposed on CPU operation by memory functions is reduced thereby enhancing data handling performance of a personal computer.
  • DRAM addressing is structured in such a way that consecutive pages of memory are distributed to different banks of DRAM. Occurrences of a requirement of two wait state cycles of the CPU for a page miss bank hit are therefore reduced.
  • a microcomputer embodying the present invention is there shown and generally indicated at 10 ( Figure 1).
  • the computer 10 may have an associated monitor 11, keyboard 12 and printer or plotter 14.
  • the computer 10 has a cover 15 which cooperates with a chassis 19 in defining an enclosed, shielded volume for receiving electrically powered data processing and storage components for processing and storing digital data, as shown in Figure 2.
  • At least certain of these components are mounted on a multilayer planar 20 or motherboard which is mounted on the chassis 19 and provides a means for electrically interconnecting the components of the computer 10 including those identified above and such other associated elements as floppy disk drives, various forms of direct access storage devices, accessory cards or boards, and the like.
  • the chassis 19 has a base and a rear panel ( Figure 2) and defines at least one open bay for receiving a data storage device such as a disk drive for magnetic or optical disks, a tape backup drive, or the like.
  • a data storage device such as a disk drive for magnetic or optical disks, a tape backup drive, or the like.
  • an upper bay 22 is adapted to receive peripheral drives of a first size (such as those known as 3.5 inch drives).
  • a floppy disk drive, a removable media direct access storage device capable of receiving a diskette inserted thereinto and using the diskette to receive, store and deliver data as is generally known, may be provided in the upper bay 22.
  • FIG. 3 there is shown a block diagram of a personal computer system illustrating the various components of the computer system such as the system 10 in accordance with the present invention, including components mounted on the planar 20 and the connection of the planar to the I/O slots and other hardware of the personal computer system.
  • the system processor 32 Connected to the planar is the system processor 32. While any appropriate microprocessor can be used as the CPU 32, one suitable microprocessor is the 80386 which is sold by INTEL.
  • the CPU 32 is connected by a high speed CPU local bus 34 to a bus interface control unit 35, to volatile random access memory (RAM) 36 here shown as Single Inline Memory Modules (SIMMs) and to BIOS ROM 38 in which is stored instructions for basic input/output operations to the CPU 32.
  • RAM volatile random access memory
  • SIMMs Single Inline Memory Modules
  • BIOS ROM 38 includes the BIOS that is used to interface between the I/O devices and the operating system of the microprocessor 32. Instructions stored in ROM 38 can be copied into RAM 36 to decrease the execution time of BIOS.
  • system processor could be an Intel 80286 or 80486 microprocessor.
  • the CPU local bus 34 (comprising data, address and control components) also provides for the connection of the microprocessor 32 with a math coprocessor 39 and a Small Computer Systems Interface (SCSI) controller 40.
  • the SCSI controller 40 may, as is known to persons skilled in the arts of computer design and operation, be connected or connectable with Read Only Memory (ROM) 41, RAM 42, and suitable external devices of a variety of types as facilitated by the I/O connection indicated to the right in the Figure.
  • ROM Read Only Memory
  • RAM 42 Random Access Memory
  • suitable external devices of a variety of types as facilitated by the I/O connection indicated to the right in the Figure.
  • the SCSI controller 40 functions as a storage controller in controlling storage memory devices such as fixed or removable media electromagnetic storage devices (also known as hard and floppy disk drives), electro-optical, tape and other storage devices.
  • the bus interface controller (BIC) 35 couples the CPU local bus 34 with an I/O bus 44.
  • the BIC 35 is coupled with an optional feature bus such as a MICRO CHANNEL bus having a plurality of I/O slots for receiving MICRO CHANNEL adapter cards 45 which may be further connected to an I/O device or memory (not shown).
  • the I/O bus 44 includes address, data, and control components.
  • Coupled along the I/O bus 44 are a variety of I/O components such as a video signal processor 46 which is associated with video RAM (VRAM) for storing graphic information (indicated at 48) and for storing image information (indicated at 49). Video signals exchanged with the processor 46 may be passed through a Digital to Analog Converter (DAC) 50 to a monitor or other display device. Provision is also made for connecting the VSP 46 directly with what is here referred to as a natural image input/output, which may take the form of a video recorder/player, camera, etc.
  • the I/O bus 44 is also coupled with a Digital Signal Processor (DSP) 51 which has associated instruction RAM 52 and data RAM 54 available to store software instructions for the processing of signals by the DSP 51 and data involved in such processing.
  • DSP Digital Signal Processor
  • the DSP 51 provides for processing of audio inputs and outputs by the provision of an audio controller 55, and for handling of other signals by provision of an analog interface controller 56.
  • the I/O bus 44 is coupled with a input/output controller 58 with associated Electrical Erasable Programmable Read Only Memory (EEPROM) 59 by which inputs and outputs are exchanged with conventional peripherals including floppy disk drives, a printer or plotter 14, keyboard 12, a mouse or pointing device (not shown), and by means of a serial port.
  • EEPROM Electrical Erasable Programmable Read Only Memory
  • DRAM in the SIMMs 36 is arranged generally as indicated in Figure 4. As shown there, data bytes may be stored in two banks with specific locations accessed for read or write functions by memory address signals selecting rows (row address signals or RAS) and columns (column address signals or CAS). Such arrangement of DRAM is well known to persons appropriately skilled in computer arts and will not be described here in greater detail.
  • the RAS and CAS are generated in a memory controller. In the embodiment illustrated, the memory control function is one function of the bus interface controller 35. Logic within the BIC 35 issues RAS and CAS to the SIMMs 36 and determines the physical locations within memory at which data is stored.
  • the present invention contemplates a manner of physical organisation which is shown in Figure 6. While the Figure 6 illustration and the discussion to follow use a two bank distribution for simplicity, it will be understood that the distribution may extend over whatever number of banks are available. In particular, sequential physical memory pages are placed across multiple memory banks, in order to increase the probability of page miss occurring across different banks. Thus, in Figure 6, successive pages 1, 2, 3, etc. alternate in physical location between banks 0 and 1. Where three or more banks are available, physical locations would be rotated among the banks available. Either of these arrangements is here referred to as interleave mode.
  • the distribution of physical pages across multiple banks contemplated by this invention compels a substantially higher likelihood of bank miss than of page miss bank hit situations. With this higher likelihood comes a reduced requirement of wait state cycles, thereby enhancing overall data handling performance of the personal computer 10.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Input (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP92304748A 1991-06-07 1992-05-27 Personalcomputer mit verbessertem Speicherzugriff und Verfahren Withdrawn EP0517415A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71440491A 1991-06-07 1991-06-07
US714404 1991-06-07

Publications (1)

Publication Number Publication Date
EP0517415A1 true EP0517415A1 (de) 1992-12-09

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EP92304748A Withdrawn EP0517415A1 (de) 1991-06-07 1992-05-27 Personalcomputer mit verbessertem Speicherzugriff und Verfahren

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EP (1) EP0517415A1 (de)
JP (1) JPH05134925A (de)
CA (1) CA2065992A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2393269A (en) * 2002-09-18 2004-03-24 Thales Plc Method and apparatus for data distribution
GB2495533A (en) * 2011-10-13 2013-04-17 St Microelectronics Res & Dev Distributing buffer data evenly across different memory devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924375A (en) * 1987-10-23 1990-05-08 Chips And Technologies, Inc. Page interleaved memory access
EP0380855A2 (de) * 1989-02-03 1990-08-08 Digital Equipment Corporation Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher
EP0427425A2 (de) * 1989-11-03 1991-05-15 Compaq Computer Corporation Seitenspeicher-Steuerschaltung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335438A (en) * 1976-09-14 1978-04-01 Fujitsu Ltd Page interleave memory system
JPS6043756A (ja) * 1983-08-19 1985-03-08 Nec Corp メモリ管理方式

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924375A (en) * 1987-10-23 1990-05-08 Chips And Technologies, Inc. Page interleaved memory access
EP0380855A2 (de) * 1989-02-03 1990-08-08 Digital Equipment Corporation Speicherkonfiguration zur Verwendung für Schnittstellenbildung zwischen einer Systemsteuereinheit für ein Multiprozessorsystem und dem Hauptspeicher
EP0427425A2 (de) * 1989-11-03 1991-05-15 Compaq Computer Corporation Seitenspeicher-Steuerschaltung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRICAL DESIGN NEWS vol. 35, no. 7, 29 March 1990, NEWTON,MA,USA pages 166 - 168; NAGI MEKHIEL: 'DRAM control scheme speeds memory access' *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2393269A (en) * 2002-09-18 2004-03-24 Thales Plc Method and apparatus for data distribution
GB2393269B (en) * 2002-09-18 2006-01-11 Thales Plc Method and apparatus for data distribution
GB2495533A (en) * 2011-10-13 2013-04-17 St Microelectronics Res & Dev Distributing buffer data evenly across different memory devices
US9164903B2 (en) 2011-10-13 2015-10-20 Stmicroelectronics (Research & Development) Limited Memory manager

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Publication number Publication date
JPH05134925A (ja) 1993-06-01
CA2065992A1 (en) 1992-12-08

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