EP0483455A1 - Arbitrierungsschema für Einzelanforderungen auf einem gemeinsamen Bus - Google Patents

Arbitrierungsschema für Einzelanforderungen auf einem gemeinsamen Bus Download PDF

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Publication number
EP0483455A1
EP0483455A1 EP91109957A EP91109957A EP0483455A1 EP 0483455 A1 EP0483455 A1 EP 0483455A1 EP 91109957 A EP91109957 A EP 91109957A EP 91109957 A EP91109957 A EP 91109957A EP 0483455 A1 EP0483455 A1 EP 0483455A1
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EP
European Patent Office
Prior art keywords
code
bus
aggregate
contending
module
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EP91109957A
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English (en)
French (fr)
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EP0483455B1 (de
Inventor
Dennis M. Kalajainen
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Definitions

  • the invention disclosed broadly relates to bus communication systems and more particularly relates to the arbitration of control of the bus by contending devices desiring access to a common bus for the transfer of data.
  • a bus acquisition system is disclosed in US-A-4,736,366 (Rickard) and a bus transceiver is disclosed in US-A-4,756,006 (Rickard), both patents owned by the common assignee of this invention. The teachings of these two patents are herein incorporated by reference.
  • a typical communication system may have up to 32 communicating modules which compete for a common bus.
  • One hundred twenty-eight logical priority levels can be ascribed to the 32 modules.
  • the arbitration sequence which takes place upon the data bus, requires eight bus cycles to resolve the winner's logical and physical ID. There are times when only one module is in contention for the bus. Even though it is common for only one module to be vying for the bus at any given time, that module must suffer a full eight-cycle latency of arbitration sequence.
  • a better technique to achieve low latency arbitration would be to add two cycles at the beginning of the arbitration sequence to determine if one or more modules are contending for control of the bus. If only one module is contending for the bus, it is not necessary to continue to the eight-cycle arbitration sequence, but give that module immediate access to the bus.
  • the present invention is a method for determining arbitration within a common bus communication system, wherein the module ID is written in true and complement form. All modules determine the number of contending modules by calculating a check code after receiving an aggregate (wire-OR) idle bus code from the bus. If the number of contenders is equal to one, then the winner of the vie has been determined and the arbitration is complete. If the number of contenders is greater than one, then the vie sequence continues to determine the eventual winner.
  • a communications unit 10 employs a common data bus 12 and has a plurality of communication modules 14.
  • Each communication module 14 has a physical ID from zero to 31 and contains a bus interface unit (BIU) 16, a central processing unit (CPU) 18 and a memory unit 20.
  • the BIU 16 does the interfacing between the bus 12 and the communication module 14.
  • the central processor 18 controls the communication module, directing the storage of data in memory unit 20 and sending it out on the common bus through the BIU 16.
  • an arbitration code is employed to decide which contender vying for the bus 12 receives control of the bus 12.
  • a standard method for achieving this would be to force each contending module 14 to output a code of zero through 31 corresponding to its unique 5-bit physical ID. Five bits are needed to represent a number from zero to 31. The codes for each module are wire-OR'ed on the bus (low active) resulting in an aggregate arbitration code. Then the 32-bit aggregate code could be checked for the number of bits that are active. If only one bit is active, bus tenure can be transferred to the corresponding module 14. If greater than one bit is active, then normal arbitration techniques would be employed. However, checking this code for the number of active bits requires a large amount of logic. The logic is usually open-collector bipolar having large drive and sink current requirements. A large number of comparators are needed. Since the entire 32-bit data bus is required to source the code, error detection is difficult, if not impossible.
  • a better code for each contender would be as follows: for each logic 0 in the physical ID, output '01' on the bus, and for each logic 1 in the physical ID, output '10' on the bus.
  • a check code can be derived from the aggregate arbitration code satisfying the following equations:
  • check code contains any zeros, then more than one module 14 is contending for the bus. Normal arbitration sequences will be required to determine the bus control. If the check code contains all ones, then the bus control can be transferred to the single competing module 14. Table 3 shows the result of a two request arbitration. Table 4 shows the result of a single request arbitration. Note that the check code is equal to all ones in Table 4.
  • Fig. 2 Shown in Fig. 2 is a clock step sequence for the two-cycle arbitration code.
  • step A all contending modules assert their idle bus code of true and complement of their physical location ID.
  • step B all modules determine the number of contending modules by calculating the check code after receiving the aggregate wire-OR idle bus code from the bus. If the number of contenders is equal to one, then the winner of the vie has been determined and the vie is complete. Therefore, the bus state in step C is HO which stands for heading zero of the first message. The winner begins to transfer its message.
  • Fig. 3 there is shown an arbitration vie resulting in more than one contender.
  • a bus state is V1 (vie 1).
  • the vie sequence continues to determine the eventual winner. Six more cycles are required.
  • Another feature of the invention is that since the code is compact, it can be duplicated or triplicated on a 32-bit data bus to allow error detection or correction, respectively. That is, only 10 bits are required for the single request arbitration code. In a 32-bit data bus, the arbitration code can be replicated three times. This is not possible with the 1-of-32 code approach since all available data bus lines are used to source the code. An additional error detection can be achieved by the generation of an error code.
  • the error code equations are:
  • Error code correction can be done by a voting of two out of three of the triplicated idle bus arbitration logical implementation. Shown in Fig. 4 are the 10-bit arbitration codes put in 10 bits 0-9. In Fig. 4, the three bits for bit 9 are first AND'ed together, then OR'ed together to form the triple modular redundant unit 22, which are AND'ed together to form the bit error correction code. These significant bits are OR'ed together to produce the error code which must equal zero if no error has occurred.
  • the single request arbitration code has applications to many different bus protocols. It can be implemented to provide extensions and enhancements to the current common bus protocols.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Detection And Correction Of Errors (AREA)
EP91109957A 1990-10-29 1991-06-18 Arbitrierungsschema für Einzelanforderungen auf einem gemeinsamen Bus Expired - Lifetime EP0483455B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US605287 1990-10-29
US07/605,287 US5132967A (en) 1990-10-29 1990-10-29 Single competitor arbitration scheme for common bus

Publications (2)

Publication Number Publication Date
EP0483455A1 true EP0483455A1 (de) 1992-05-06
EP0483455B1 EP0483455B1 (de) 1996-08-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP91109957A Expired - Lifetime EP0483455B1 (de) 1990-10-29 1991-06-18 Arbitrierungsschema für Einzelanforderungen auf einem gemeinsamen Bus

Country Status (4)

Country Link
US (1) US5132967A (de)
EP (1) EP0483455B1 (de)
JP (1) JP2654281B2 (de)
DE (1) DE69121665D1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773500A1 (de) * 1995-11-07 1997-05-14 Sun Microsystems, Inc. Zweimode-Arbitrierungsverfahren für Rechnersysteme mit null bis zwei Latenzzyklen

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274636A (en) * 1992-04-20 1993-12-28 Chrysler Corporation Automatic multiplex data link system, symbol encoder decoder therefor
FR2692057B1 (fr) * 1992-06-09 1996-11-22 Alsthom Gec Reseau locaal, notamment pour un systeme de commande et d'auto-surveillance d'un appareil electrique.
US5335226A (en) * 1992-06-18 1994-08-02 Digital Equipment Corporation Communications system with reliable collision detection method and apparatus
US5764927A (en) * 1995-09-29 1998-06-09 Allen Bradley Company, Inc. Backplane data transfer technique for industrial automation controllers
US6058449A (en) * 1997-07-31 2000-05-02 Motorola, Inc. Fault tolerant serial arbitration system
US6993612B2 (en) * 2000-12-07 2006-01-31 Micron Technology, Inc. Arbitration method for a source strobed bus
US7020156B2 (en) * 2000-12-15 2006-03-28 American Standard International Inc. Multiple device communications
US20070027485A1 (en) * 2005-07-29 2007-02-01 Kallmyer Todd A Implantable medical device bus system and method
US7712010B2 (en) * 2006-06-15 2010-05-04 International Business Machines Corporation Systems, methods and computer program products for utilizing a spare lane for additional checkbits
JP4774347B2 (ja) * 2006-08-18 2011-09-14 富士通株式会社 ノード装置、制御装置、制御方法及び制御プログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402040A (en) * 1980-09-24 1983-08-30 Raytheon Company Distributed bus arbitration method and apparatus
EP0220536A2 (de) * 1985-10-31 1987-05-06 International Business Machines Corporation Verfahren zur Bestimmung der Zugriffsberechtigung mehrerer eindeutig identifizierbarer Prozessoren zu einer gemeinsamen Informationsquelle

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US4554628A (en) * 1981-08-17 1985-11-19 Burroughs Corporation System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn't bid again until all stored bids win
US4470112A (en) * 1982-01-07 1984-09-04 Bell Telephone Laboratories, Incorporated Circuitry for allocating access to a demand-shared bus
US4734909A (en) * 1982-03-08 1988-03-29 Sperry Corporation Versatile interconnection bus
US4503535A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for recovery from failures in a multiprocessing system
US4814974A (en) * 1982-07-02 1989-03-21 American Telephone And Telegraph Company, At&T Bell Laboratories Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
EP0179936B1 (de) * 1984-10-31 1990-01-03 Ibm Deutschland Gmbh Verfahren und Einrichtung zur Steuerung einer Sammelleitung
US4736366A (en) * 1986-02-13 1988-04-05 International Business Machines Corporation Bus acquisition system
US4756006A (en) * 1986-02-26 1988-07-05 International Business Machines Corporation Bus transceiver
JPS63132365A (ja) * 1986-11-22 1988-06-04 Nec Corp バス調停制御方式
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
US4901226A (en) * 1987-12-07 1990-02-13 Bull Hn Information Systems Inc. Inter and intra priority resolution network for an asynchronous bus system
US4878173A (en) * 1988-05-16 1989-10-31 Data General Corporation Controller burst multiplexor channel interface
US4965793A (en) * 1989-02-03 1990-10-23 Digital Equipment Corporation Method and apparatus for interfacing a system control unit for a multi-processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402040A (en) * 1980-09-24 1983-08-30 Raytheon Company Distributed bus arbitration method and apparatus
EP0220536A2 (de) * 1985-10-31 1987-05-06 International Business Machines Corporation Verfahren zur Bestimmung der Zugriffsberechtigung mehrerer eindeutig identifizierbarer Prozessoren zu einer gemeinsamen Informationsquelle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773500A1 (de) * 1995-11-07 1997-05-14 Sun Microsystems, Inc. Zweimode-Arbitrierungsverfahren für Rechnersysteme mit null bis zwei Latenzzyklen

Also Published As

Publication number Publication date
EP0483455B1 (de) 1996-08-28
JPH04273563A (ja) 1992-09-29
DE69121665D1 (de) 1996-10-02
US5132967A (en) 1992-07-21
JP2654281B2 (ja) 1997-09-17

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