EP0474366A2 - Graphisches Anzeigesystem enthaltend einen Video-Direktzugriffsspeicher mit geteiltem Schieberegister und ein Laufzähler - Google Patents

Graphisches Anzeigesystem enthaltend einen Video-Direktzugriffsspeicher mit geteiltem Schieberegister und ein Laufzähler Download PDF

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Publication number
EP0474366A2
EP0474366A2 EP91307222A EP91307222A EP0474366A2 EP 0474366 A2 EP0474366 A2 EP 0474366A2 EP 91307222 A EP91307222 A EP 91307222A EP 91307222 A EP91307222 A EP 91307222A EP 0474366 A2 EP0474366 A2 EP 0474366A2
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European Patent Office
Prior art keywords
data
register
random access
access memory
storage
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EP91307222A
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French (fr)
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EP0474366B1 (de
EP0474366A3 (en
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Andre J. Guillemaud
Anthony M. Balistreri
Karl M. Guttag
Richard D. Simpson
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Texas Instruments Inc
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Texas Instruments Inc
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Priority claimed from US07/563,469 external-priority patent/US5517609A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the present invention pertains to graphics display and processing systems for producing a graphics display generally and particularly using a semiconductor memory in the form of a random access memory with a split serial register arrangement.
  • time required for accessing a row is approximately twice as long as the time required for accessing a column.
  • page mode it is desirable to access a row and hold it while several of the columns are accessed along that row. This is referred to as "page mode" operation. If all of the columns across the array are accessed during a single row access, time saved may be as much as 50-70 percent. Such time saving may be achieved during memory write or during memory read operations. For any specific system design there may be trade-offs between memory write time and memory read time to achieve operating efficiency.
  • Suppliers of devices which may be used in such applications prefer to manufacture devices that include several optional features so that designers and users will apply each type of device in many different applications. This enables one device design effort to result in large manufacturing runs and low costs per device.
  • line oriented operation the graphics processor generates and stores data in sequential order as it will appear line-by-line on the display.
  • Storage of data in the video random access memory and read out from storage to the display are accomplished in serial order bit-by-bit and line-by-line. Read out from the split serial register to the display is timed to correlate with the display sweep signal.
  • Prior video random access memory device designs have features which are very desirable and are in wide spread use in line oriented systems.
  • a tile oriented display is divided into a grid of equal size and shape areas, called tiles.
  • the size and shape of the tiles are factors which are among the factors to be chosen by the system designer or user. For instance, the tiles may be squares or rectangles. If rectangles, they may be oriented with the long dimension either laying horizontally or standing vertically.
  • currently available video random access memory devices lack sufficient flexibility for efficient use in some possible system applications. More specifically, the data representing a single tile must be stored in different rows of the storage cells of the random access memory array.
  • the start point address of a data access run can be defined by information loaded into the start point register
  • the access run of the data readout ended at the midpoint of the split serial register when reading from the low-half or at the very end of the split serial register when reading from the high-half. This aspect of operating with a split serial register is a significant problem or limitation for some graphics processing systems designs.
  • the end point for an access run in the low-half of the split serial register would be at bit 255 and the end point for an access run in the high-half of the split serial register would be at bit 511. Since typical useful access runs for a graphics processing system often vary from eight bits to 128 bits, the forcing of access runs to end either at bit 255 or at bit 511, unnecessarily slows the operating speed of the graphics processing system.
  • a graphics display and processing system including a video random access memory with a split serial register having low and high halves of a plurality of storage elements, an access start point address register, and an arrangement for stopping an access run at the end of a desired run length.
  • a method and apparatus define both start and stop points of a data access operation, i.e., the specific run length, for a split serial register of a graphics processing system.
  • the address of the access start point in the split register is loaded into the access start point address register.
  • a run length is loaded into a run length counter. Together that information determines the start and stop point addresses for each access operation of the split serial register.
  • the graphics processing system is able to start and stop read access operations at selected storage elements in the split serial register.
  • the graphics display and processing system operates at a faster speed.
  • the graphics display and processing system has a random access memory arranged with a novel split register and a multiplexer for transferring data from the memory array to the split register. Data stored in either a low half or a high half of the memory array column addresses may be selectively transferred through the multiplexer to either a low half or a high half of the split register addresses.
  • An advantage of this arrangement is that system designers have greater flexibility, or more options, particularly in a tile oriented operation, in deciding where within the memory array to store specific bits of information to be displayed, particularly in a tile oriented operation.
  • a tile of data can be mapped into the storage elements along a single row of the random access memory array. Thereafter the data from the storage elements of the random access memory are transferred into the split register and transmitted in line-by-line sequence to a raster scan display.
  • FIG. 1 there is shown a block diagram of a data processing system 100 including a graphics display arrangement for presenting information.
  • a more complete description of the arrangement and operation of the system of Figure 1 can be found in a patent application serial No. 821,641, filed January 23, 1986, which is incorporated herein by reference.
  • the data processing system 100 includes a host processing system 102, a graphics processor 103, such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor, a video random access memory 105, a data register 107, a video palette 108, a digital to video converter 110, and a video display 112.
  • a graphics processor 103 such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor
  • a video random access memory 105 such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor
  • a video random access memory 105 such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor
  • a data register 107 such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor
  • a data register 107 such as a Texas Instruments Incorporated TMS34010 or TMS34020 Graphics System Processor
  • Host processing system 102 provides the major computational capacity for the data processing system 100. Included in the host processing system 102 are a processor, an input device, a long term storage device, a read only memory, a random access memory and assorted peripheral devices that form a computer system. Arrangement and operation of the host processing system are considered to be conventional. As a result of its processing functions, the host processing system 102 determines the information content of the graphic display to be presented on a screen for the user.
  • Graphics processor 103 provides the major portion of data manipulation for producing the particular graphics display to be presented on the screen.
  • the graphics processor 103 is bi-directionally coupled to the host processing system 102 by way of a host bus 101.
  • graphics processor 103 operates independently from the host processing system 102.
  • the graphics processor 103 is responsive to requests from the host processing system 102.
  • Graphics processor 103 also communicates with memory 105 and the video palette 108 by way of a memory bus 104.
  • Data to be stored in the video random access memory 105 is controlled by the graphics processor 103.
  • the graphics processor may be controlled either in part or wholly by a program stored in the video random access memory 105 or in a read only memory 114. Read only memory 114 may store various types of graphic image data.
  • the graphics processor 103 controls data stored within the video palette 108 and by way of a video control bus 116 the operation of the digital to video converter 110. Through the digital to video converter, the graphics processor 103 can control the line length and the number of lines per frame of the video graphic image. Significantly, the graphics processor 103 determines and controls where graphic display information is stored in the video random access memory 105. Subsequently, during readout from the video random access memory 105, the graphics processor determines the readout sequence from the video random access memory and the split serial register 107, the addresses to be accessed, and control information required to produce the desired graphic image on the display 112.
  • Video random access memory 105 stores the bit mapped graphics data which define the graphics image to be presented to the user. Control of the transfer of the data from the video random access memory 105 through the data register 107, the video palette 108, and the digital to video converter 110 to the display 112 is provided by the graphics processor 103. Video data output from the video random access memory 105 is transferred by way of a video output bus 118 to the data register 107 where it is assembled into a display bit stream.
  • the data register 107 may be a shift register.
  • Storage elements of the data register 107 may be fabricated of either dynamic or static electronic circuits. Alternative choices of storage elements include any bistable electronic, magnetic, optical, or optoelectronic device with sufficient operating speed.
  • the video random access memory 105 there is a bank of several separate random access memory integrated circuits.
  • Storage cells of the video random access memory 105 may be fabricated as either dynamic or static electronic circuits. For a single readout access operation, only one bit of data is readout from a selected storage element of each of the integrated circuits. Thus a group of bits, including one bit from each of the several separate integrated circuits, are read out at once.
  • the data register 107 assembles the display bit stream for transmission by way of a lead 120 to the video palette 108.
  • the video random access memory 105 as an electronic circuit, the invention may also be carried out by a memory fabricated as any bistable electronic, magnetic, optical or optoelectronic device with sufficient speed.
  • the video palette 108 Under control of information from the graphics processor 103, the video palette 108, such as a Texas Instruments TMS34070 Video Palette, converts the data received from the data register 107 into video level signals on a bus 125. This conversion is accomplished through a look-up table.
  • the video level signal output from the video palette 108 may include color, saturation, and brightness information.
  • Digital to video converter 110 receives the digital video signals from the video palette 108 and, under control of signals received by way of the video control bus 116, converts the digital video signals into analog levels which are applied to the video display 112 via an output line 127.
  • the number of pixels per horizontal line and the number of lines per display are determined by the graphics processor 103.
  • the synchronization, retrace, and blanking signals are controlled by the graphics processor 103. Altogether, this group of signals specify the desired video output to the video display 112.
  • Video display 112 produces the specified video image for viewing by the user.
  • the first technique specifies video data in terms of color, hue, brightness, and saturation for each pixel.
  • For the second technique color levels of red, blue and green are specified for each pixel.
  • the video palette 108, the digital to video converter 110, and the video display are designed and fabricated to be compatible with the selected technique.
  • FIG. 2 there is shown a block diagram layout of an integrated circuit video random access memory 105. Included within the memory 105 are four arrays of memory cells 105-1, 105-2, 105-3, 105-4. The cells are arranged in rows and columns. For random access, row and column addresses are applied to the integrated circuit by way of address leads and an address bus. For random access, row and column addresses are decoded respectively by row and column decoders. Data is written from a data bus through the column decoders and sense amplifiers to the selected cells of the memory arrays. For serial readout, the data is read from a selected row of the memory arrays, through transfer gates to the data registers.
  • a serial address counter applies a series of serial data register addresses to the serial data pointers, or decoder. In response to those addresses, sequences of data are transmitted from the serial data registers through a data bus to a serial output buffer. From there the data proceeds to the register 107, the video palette, the digital-to-video signal converter, and to the video display, as shown in Figure 1.
  • the various random access input and output circuits are replicated four times to complete the random access arrangement.
  • a group of common circuits controls the readout operation very effectively.
  • the group of circuits includes an initial tap register, a run count register, a run counter, a comparator, and a serial address counter which applies a series of addresses through another address bus to serial data pointers associated with each serial data register. Operation of these common circuits for serial readout are described at length hereinafter.
  • Video random access memory 105 is an exemplary memory including four memory arrays 105-1, 105-2, 105-3, and 105-4 of rows and columns of storage cells. Typically the four memory arrays are included on one semiconductor chip.
  • Information representing a single pixel for the display includes several bits of data. There is one bit, e.g., B0, stored in each of the arrays for one pixel. All of those bits for the one pixel are stored at the same row address and the same column address so that they can be either written into or read out from the whole memory in one access operation. In any specific design, there usually are as many memory arrays as there are bits in a pixel. If more than four bits are needed per pixel, either more arrays per chip or more chips may be provided.
  • the screen of the video display 112 of Figure 1 can be thought to be organized in either of two ways. Usually in the display, there are a large number of horizontal lines each including a large number of pixels. Another often used, but different, scheme divides the display into a number of tiles. Each tile includes some number of pixels in a contiguous area of the display. The tile areas for a display are uniform in size and therefore include some number of pixels across and some number of pixels in height. For purposes of subsequent discussion, the number of pixels across a tile equals the number of columns in a section of the video random access memory array 105-1 and the number of storage elements in a section of the split register 109-1.
  • the split register 109-1 may be either a shift register or a serial register.
  • split serial register 109-1 Information in one line across a tile is considered to be a segment of the tile. Since there is only one bit per pixel in the memory array 105-1, the number of bits in a segment of the tile in array 105-1 equals the number of columns used in the sections of the memory array and the number of storage elements used in the sections of the split serial register 109-1. The number of pixels in height equals the number of lines in the tile. For a subsequent illustrative example, a tile is thirty-two pixels across and eight pixels high in the display depicted in Figure 12, to be discussed subsequently.
  • the video random access memory array 105-1 is arranged so that the data, representing a tile of the display, is stored as sequential segments of the tile in a single row of the memory array 105-1. An entire tile of data is stored in the single row of the memory array 105-1. Row and column address information, together with the desired display, or pixel information, is generated by the graphics processor 103.
  • the addresses are applied through the bus 104 to an address register 106 for accessing the identified row and column storage locations in the random access memory array 105-1.
  • the display data, to be stored at each address also is applied through the bus 104 and a lead 111 to the random access memory array 105-1.
  • the graphics processor develops the random access address and display data for any tile, that data, in a departure from the prior art, is transmitted through bus 104 and is written into the random access memory 105-1 by making a single row access and thereafter accessing sequentially selected columns where data is to be stored. This enables a random access write-in operation to write in during a single row access as much as a whole tile of data. Since the accessing of a row operation takes approximately twice as long as accessing a column, considerable operational time is saved by making the single row access and performing the several column accesses while the row access remains effective.
  • the memory array 105-1 and the split serial register 109-1 are each divided by address into a low part and a high part. Such divisions greatly facilitate readout from the memory array 105-1 to the video display 112 of Figure 1. Readout from the memory array 105-1 occurs sequentially by line of the display. As the raster scans a line of the display, the appropriate data for each pixel in the sequence is applied to the beam for projection on the display screen.
  • the graphics processor 103 determines the order for addressing the storage cells of the memory array 105-1, the selection made by the multiplexer 130-1, and the order for reading data from the storage elements of the split serial register 109-1 to achieve the desired output sequence of information being forwarded to the video display 112.
  • Rows of the memory are addressed by part rows, e.g., low address half rows and high address half rows.
  • the multiplexer 130-1 determines whether the data read out of either the low-half or the high-half of the memory array is transmitted by bit line to either the low-half or the high-half addresses of the split serial register 109-1. Once the data is stored in the split serial register 109-1, one or more bits of data or segments of tiles can be transmitted from the split serial register 109-1 out to the video display 112.
  • Additional control circuitry which is common to the several memory arrays, is provided for determining the specific portion of data to be transmitted from the split serial register 109-1.
  • the data from the split serial register 109-1 can be read out from a separate tap at each storage element.
  • the taps are represented by a gate circuit 132 which receives a separate output from each storage element of the split serial register 109-1.
  • a counter decoder 135 determines which one of the split serial register storage element outputs is transmitted to the video display 112 during any time slot determined by a readout clock signal CLOCK .
  • the graphics processor 103 loads the address of that initial pixel data into an initial tap, or start point, register 137.
  • the initial tap register 137 loads the initial pixel data address into the counter decoder 135 for enabling the gate circuit 132 to transmit the data from the correct split serial register storage element. Loading of the initial pixel data address may be in parallel to the counter decoder 135.
  • Data read out thereafter generally proceeds sequentially along the storage elements of the split serial register 109-1, however, unlike the prior art, it does not necessarily proceed continuously.
  • One such circumstance arises when the display system is tile oriented and the data representing a tile is stored along a single row of the memory array 105-1, as previously described herein. Then for efficiency, the sequential addressing for reading out the data from the split serial register 109-1 should be interrupted before the end of half the register.
  • interruptions are made by the graphics processor 103 loading a number, or run count, into a run count register 140 for determining the number of sequential addresses of the split serial register 109-1 that are accessed before the interruption, i.e., before the counter decoder 135 and gate circuit 132 jump to a new initial, or start, tap address for subsequent readout.
  • a convenient run length is equal to the number of pixels in a segment.
  • the number in the count register 140 and a run count from a run counter 142 are compared by the comparator 145. When they do not match, the current sequence of addresses continues as the run counter is incremented by the signal CLOCK for each readout operation.
  • the comparator 145 When the two counts do agree, e.g., at the end of a segment, the comparator 145 produces a signal for resetting the run counter 142 and for loading the new initial tap address into the initial tap register 137. As a result, the counter decoder 135 enables the gate circuit 132 to jump to the new initial tap address of the split serial register 109-1 and thereby interrupt the sequential addressing.
  • a tile oriented system it is advantageous for a tile oriented system to run through a sequence of addresses equal to the number of addresses needed for reading out all of the pixels in a segment of a tile from one half of the split serial register 109-1 and then transfer to the other half of the split serial register to read out the pixels in a segment from another tile. Since the tiles typically end before the end of a half of the register, it is advantageous to interrupt the readout operation at the end of the tile rather than at the end of half of the register. A more detailed description of this operation is to be described hereinafter in reference to Figures 5 through 12.
  • FIG 4 there is shown the physical arrangements of the storage cells and bit lines of the memory array 105-1 and of the storage elements of the associated split serial register 109-1.
  • the memory array 105-1 and the split serial register 109-1 both are divided into parts by addresses, a low-half L of the memory array addresses including half of the storage cells and a high-half H of the memory array addresses including the remaining storage cells.
  • the low-half designators L0...L127 are shown below the high-half designators H0...H127 so that, at a glance, the two halves will stand out from each other in Figure 4.
  • the storage cells L of the low-half addresses of the memory array 105-1 are interleaved with the storage cells H of the high-half addresses of the memory array.
  • the storage elements L of the low-half addresses of the split serial register 109-1 are interleaved with the storage elements H of the high-half addresses of the split serial register 109-1.
  • Such interleaving of the storage cells of the two parts of the memory columns and of the storage elements of the two parts of the split serial register 109-1 provides a significant advantage when the memory array 105-1 and the split serial register 109-1 are fabricated as an integrated circuit.
  • the total length and complexity of the bit lines, which are arranged for coupling the storage cells of the memory array 105-1 through the multiplexer 130-1 to the storage elements of the split serial register 109-1 are substantially reduced with respect to the bit line layout, which otherwise is required when the lower and upper halves of the memory array 105-1 and split serial register 109-1 are divided by whole physical sections rather than by the interleaving of the columns and register elements, as shown in Figure 4.
  • Figure 4 additionally illustrates a schematic for a section 130-1.1 of the multiplexer 130-1 which can be used for transferring data from one cell in either half of the addresses of the memory array 105-1 to a storage element in either half of the addresses of the split serial register 109-1.
  • the illustrated section 130-1.1 of the multiplexer 130-1 couples one column address of the high-half or one column address of the low-half of the memory array 105-1 to associated high or low half storage elements of the split serial register 109-1.
  • the complete multiplexer 130-1 uses one of such multiplexer sections 130-1.1 for every pair of bit lines.
  • FIG. 5 there is shown a truth table that describes the logical operation of the section 130-1.1 of the multiplexer 130-1 shown in Figure 4.
  • a one-out-of-four code received from the graphics processor by way of a path 160 of Figure 3, is applied to the control terminals H-H, L-L, L-H and H-L of the illustrative switching devices.
  • one gate of the multiplexer section 130-1.1 is enabled. The other three gates remain disabled.
  • Input control signals are designated low-half-to-low-half, L-L; low-half-to-high-half, L-H; high-half-to-low-half, H-L; and high-half-to-high-half, H-H.
  • Inputs are from the high-half H or low-half L of the memory array, and outputs go to the high-half H or low-half L of the split serial register.
  • multiplexer operations represented by the truth table of Figure 5 is not dependent upon the interleaving of the storage elements in the memory array or in the split serial register, as shown in Figure 4.
  • the described multiplexer operations may be used for coupling the column addresses of other arrangements of split memory arrays to the addresses of the split serial register.
  • the graphics processor 103 of Figures 1 and 3 generates all of the information for the graphic display. Each bit of the data can be generated at any time and in any order. The processor 103 knows which bit is being generated at any time and where that bit is preassigned, or mapped, for storage in the random access memory 105. When randomly writing the bits into the random access memory 105, the order of writing the bits is unimportant except for efficiency considerations, but each bit must be stored in a storage element at its own preassigned, or bit mapped, location in the random access memory.
  • FIG. 6 there is shown a Cartesian coordinate map representing the storage locations in the random access memory array 105-1 presented in Figures 3 and 4. It is noted that the low-half and the high-half of the array are divided in the center rather than by interleaving the columns. This array is shown divided in the center for the purpose of illustrating the concept by a simplified drawing. Our preference in practice, however, is to interleave memory storage elements and the column leads by address, as shown in Figure 4. The interleaved arrangement can handle the high-half, low-half transfer operations in accordance with the subsequent discussion just as well as the illustrated random access memory array 105-1 of Figure 6.
  • the grid of Figure 6 is an 8 x 8 array of squares, each square of which represents the information to be presented as an eighth of a tile to be presented on the graphic display.
  • squares represent segments of data. Each segment is numbered so that the reader can follow numerically identified segments from storage in the memory array through the multiplexer and split serial register to the display, as subsequently discussed. The numbers in the squares identify the information as segments of the tiles.
  • Each segment of data is stored in a section of a row of the memory.
  • Data represented by each one of the numbered squares, or segments includes thirty-two bits of data (i.e., 32 columns x 1 row) which are stored as shown in the memory array 105-1.
  • a tile of the display image is represented by all of the bits stored in the memory cells along a single row of the random access memory array 105-1, e.g., row 1. It was noted previously that relating to the display of Figure 12, the tiles are thirty-two bits wide by eight bits high and are oriented in vertical columns in the display, as discussed subsequently with respect to Figure 12.
  • the graphics processor creates the information for the display image by tiles and stores that information into the memory array.
  • all of the data included in each row of the memory array is equivalent to a full tile.
  • the graphics processor 103 creates all of the data making up a single tile, the graphics processor only accesses a single selected row in the memory array 105-1 one time. While that selected row is accessed, the columns are accessed one at a time until all of the new data, related to the one tile, is stored in the accessed row of the random access memory.
  • the graphics processor 103 writes, or stores, all of the data contained in one tile while accessing only one row of the memory array, considerable system operating efficiency is achieved.
  • Each row access generally takes as much as twice the time needed for each column access.
  • the worst case occurs when only a single column is accessed for each row access.
  • Our arrangement can achieve as much as a seventy percent reduction in operating time with respect to the worst case for writing randomly into the random access memory.
  • the system can commence reading that data from the random access memory for transfer to the split serial register 109-1, the data register 107 and on to the video display 112.
  • data is stored in the memory by segment.
  • the video display uses a well-known raster scanning technique for presenting the graphic information on a display screen or cathode ray tube.
  • the graphics processor 103 scans the random access memory 105 for transferring data to the display. Data from the memory array is transferred through the multiplexer, the split serial register, the data register 107, and the color palette, and is coordinated with the raster beam as it sweeps across one horizontal line after another projecting the graphics information onto the screen at predetermined locations.
  • the sequential order of readout of data from the memory array is fixed by the hardware and firmware of the graphics display system.
  • the first data for display is segment 1, then segment 2, etc., until finally segment 64.
  • data from one half row of the addresses of the data register 107 are being read out to the display 112
  • data from another half row of addresses can be transferred from the memory array 105 to the idle half of the split serial register 109-1.
  • the information sent from the split serial register may be -and often is- less than an entire half register for every half register of data transferred thereto from the memory.
  • Data register 107 is arranged to receive in parallel, the sequential data streams from each of the arrays 105-1, 105-2, 105-3, and 105-4 by way of the output leads 118-1, 118-2, 118-3, and 118-4 of Figure 3.
  • the data register 107 takes in the plural parallel streams of input data, and shifts them out in one interleaved sequence. All of the bits for each pixel are grouped together in the output stream of data. Thus all of the data describing each pixel is applied to the video palette at once.
  • the video palette translates the pixel data into the desired form for application to the digital to video converter. From the digital to video converter, the video signals are applied to the display. At the finish of each line of the screen, the raster retraces, or returns, to the beginning side of the screen, typically, one or more lines lower. During retrace, graphic information is blanked from the beam. Once the retrace is completed, the raster commences sweeping across another line of the screen and projects the graphic display information. Because the raster beam sweeps across the entire screen and then retraces, the data read from the memory array must be presented to the beam modulator of the video display 112 in the proper sequential order for each complete sweep across the screen.
  • Figure 7 there is shown a table representing the operation of sequentially reading the stored data, as presented in Figure 7, from the random access memory of Figures 3 and 4.
  • the leftmost column shows the time slots for reading segments of data from the memory array 105-1.
  • the column labeled the LOW HALF of the register shows which groups of bits, or parts of tiles, are read out of the memory array and into the low-half of the split serial register 107-1 of Figure 4 in preparation for transfer of selected segments to the video display 112 during odd numbered time slots of the readout operation.
  • the column labeled HIGH HALF of the register shows the groups of bits that are read out of the memory array and into the high-half of the addresses of the split serial register 107-1 in preparation for transfer of other selected segments to the display during even numbered time slots.
  • the column labeled MULTIPLEXER presents an indication of the control signal information for operating the multiplexer 130-1 for the transfer of data into the split serial register 107-1 before it is sent to the video display.
  • the letters designate, respectively, the low-half L or high-half H of the addresses of the memory array 105-1 and the split serial register 107-1 and thus designate the multiplexer control signalling used in Figure 4.
  • the initial tap address, to be stored in the initial tap register 137, is the address of the first bit of segment 1. Thirty-two is stored into the run count register 140 so that the sequential read is interrupted when 32 bits are read out from the split serial register. Segments 9, 17 and 25 are not forwarded during time slot 1. Refer now to Figures 6 and 8 for the next step of the sequential readout. While the segments 1, 9, 17, and 25 are residing in the low-half of the register, data from the low-half L of the second row of the memory array 105-1 is transferred through the multiplexer to the high-half H of the split serial register 107-1. The multiplexer 130-1 is set for a low-half L to high-half H transfer (control signal L-H).
  • Bits of segments 2, 10, 18 and 26 are transferred into the high-half of the split serial register 107-1.
  • time slot 2 the 32 bits representing the segment 2 are forwarded to the display device. This is accomplished by storing the appropriate start address and run count while the segments are being transferred into the split serial register.
  • the number 2 is encircled to indicate that the segment 2 is so forwarded to the display in sequence following segment 1.
  • Figures 7-11 for each of the time slots only one segment number is encircled to indicate which tile segment is forwarded in the sequence going to the display. An appropriate start address and run count are stored and used for each time slot.
  • Figures 10 and 11 show additional examples of the data from rows 1 and 2 of the memory being transferred through the multiplexer to the split serial register for sending segments 57 and 58 to the display.
  • FIG 8 there is shown a time line for the sequence of tile segments being forwarded out of the split serial register 107-1 of Figure 3 to the display.
  • the tile segments can be transmitted to the video display 112 of Figure 1 in sequential order 1, 2, 3, . . . 64, as shown in Figure 12.
  • FIG. 13 there is shown a graphic representation of the stored data, from the memory array 105-1, as an image created by the tile segment information presented in raster scan sequence on the video display 112.
  • the numbered segments of the data are presented to the video display in sequential order 1, 2, . . . 64.
  • Each scan of the raster includes eight segments of the data, one segment for each of eight tiles per scan.
  • Each tile is in a separate column on the screen and may be identified by the number in the top row of its column. Thus the tiles are numbered 1, 2 . . . 8. It is noted that all of the data for each tile of the display screen is mapped from a different row of the memory array 105 of Figure 6.
  • Figure 14 shows an alternative arrangement of the serial readout circuits and of the serial readout control circuits for a system using a split shift register. It is noted that features which are the same as the features of Figure 3 are designated with the same numerical identifier. Other numerical identifiers are used with respect to different features.
  • control signals on the leads 160 cause the data from either the low-half or the high-half of the memory to be transferred to either the low-half or the high-half of the split shift register.
  • the split shift register is arranged at every stage with a tap for outputting data.
  • a tap address register 175 is loaded with the address of the tap from which the first bit of a data sequence and subsequent data is to be outputted.
  • the tap address is loaded into the register decoder 192.
  • the register decoder 192 stores the tap address for the duration of the current serial readout operation.
  • a decoded signal is applied to the gate 132-1 to identify and enable the selected tap for reading out data from the associated shift register stage.
  • a shift clock signal applied to the split shift register 191-1 and the run counter 142, shifts data along the stages of the shift register 191-1 and increments the count in the run counter 142.
  • a new bit of data is stored in the shift register stage associated with the selected tap. That new bit is read out through the gate 132-1 and the lead 118-1 for transmission to the video display, not shown.
  • the comparator 145 continuously compares the count in the run counter 142 with the run count value stored in the run count register 140. Whenever they do not match, the comparator produces a low output signal. When they match, however, the comparator produces a high output signal. This high output signal is the signal which resets the run counter 142 to zero and enables the tap address register 175 to send a new tap address to the register decoder 192.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
EP19910307222 1990-08-06 1991-08-06 Graphisches Anzeigesystem enthaltend einen Video-Direktzugriffsspeicher mit geteiltem Schieberegister und ein Laufzähler Expired - Lifetime EP0474366B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US56347290A 1990-08-06 1990-08-06
US563469 1990-08-06
US563472 1990-08-06
US07/563,469 US5517609A (en) 1990-08-06 1990-08-06 Graphics display system using tiles of data

Publications (3)

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EP0474366A2 true EP0474366A2 (de) 1992-03-11
EP0474366A3 EP0474366A3 (en) 1992-11-19
EP0474366B1 EP0474366B1 (de) 1996-07-03

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EP (1) EP0474366B1 (de)
JP (1) JPH06102842A (de)
DE (1) DE69120616T2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0673036A2 (de) * 1994-03-16 1995-09-20 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung mit geteiltem Übertragungsbetrieb
EP0690430A3 (de) * 1994-06-02 1996-07-03 Accelerix Ltd Einchip-Rasterpufferspeicher und Graphikbeschleuniger
US6041010A (en) * 1994-06-20 2000-03-21 Neomagic Corporation Graphics controller integrated circuit without memory interface pins and associated power dissipation
CN101751908B (zh) * 2008-11-28 2011-12-14 旭曜科技股份有限公司 帧存储器存取方法以及显示器驱动装置

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US4825411A (en) * 1986-06-24 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Dual-port memory with asynchronous control of serial data memory transfer
EP0398511A2 (de) * 1989-05-16 1990-11-22 International Business Machines Corporation Video-Direktzugriffsspeicher

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US4825411A (en) * 1986-06-24 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Dual-port memory with asynchronous control of serial data memory transfer
EP0398511A2 (de) * 1989-05-16 1990-11-22 International Business Machines Corporation Video-Direktzugriffsspeicher

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0673036A3 (de) * 1994-03-16 1996-07-17 Toshiba Kk Halbleiterspeicheranordnung mit geteiltem Übertragungsbetrieb.
US5748201A (en) * 1994-03-16 1998-05-05 Kabushiki Kaisha Toshiba Semiconductor memory device having multiple modes that allow the cell array to be divided into a variable number of portions
US5890197A (en) * 1994-03-16 1999-03-30 Kabushiki Kaisha Toshiba Semiconductor memory device having split transfer function
EP0673036A2 (de) * 1994-03-16 1995-09-20 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung mit geteiltem Übertragungsbetrieb
USRE40326E1 (en) 1994-06-02 2008-05-20 Mosaid Technologies Incorporated Single chip frame buffer and graphics accelerator
EP0690430A3 (de) * 1994-06-02 1996-07-03 Accelerix Ltd Einchip-Rasterpufferspeicher und Graphikbeschleuniger
US5694143A (en) * 1994-06-02 1997-12-02 Accelerix Limited Single chip frame buffer and graphics accelerator
USRE37944E1 (en) 1994-06-02 2002-12-31 3612821 Canada Inc. Single chip frame buffer and graphics accelerator
USRE44589E1 (en) 1994-06-02 2013-11-12 Mosaid Technologies Incorporated Single chip frame buffer and graphics accelerator
USRE41565E1 (en) 1994-06-02 2010-08-24 Mosaid Technologies Incorporated Single chip frame buffer and graphics accelerator
US6041010A (en) * 1994-06-20 2000-03-21 Neomagic Corporation Graphics controller integrated circuit without memory interface pins and associated power dissipation
US6920077B2 (en) 1994-06-20 2005-07-19 Neomagic Corporation Graphics controller integrated circuit without memory interface
US6771532B2 (en) 1994-06-20 2004-08-03 Neomagic Corporation Graphics controller integrated circuit without memory interface
CN101751908B (zh) * 2008-11-28 2011-12-14 旭曜科技股份有限公司 帧存储器存取方法以及显示器驱动装置

Also Published As

Publication number Publication date
DE69120616D1 (de) 1996-08-08
EP0474366B1 (de) 1996-07-03
DE69120616T2 (de) 1996-11-28
JPH06102842A (ja) 1994-04-15
EP0474366A3 (en) 1992-11-19

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