EP0389835B1 - Method and circuit arrangement for the reproduction of received video signals - Google Patents

Method and circuit arrangement for the reproduction of received video signals Download PDF

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Publication number
EP0389835B1
EP0389835B1 EP90104310A EP90104310A EP0389835B1 EP 0389835 B1 EP0389835 B1 EP 0389835B1 EP 90104310 A EP90104310 A EP 90104310A EP 90104310 A EP90104310 A EP 90104310A EP 0389835 B1 EP0389835 B1 EP 0389835B1
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Prior art keywords
frame
memory
received
frames
pixels
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German (de)
French (fr)
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EP0389835A3 (en
EP0389835A2 (en
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Bernhard Dohmann
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/587Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence

Definitions

  • the invention is based on a method according to the preamble of claim 1. Such a method is known from "Signal Processing, Vol. 11, 1986, December, No. 4, Amsterdam; pages 387 to 404; M. Bierling and R. Thoma : Motion compensating field interpolation using a hierarchically structured displacement estimator ".
  • the data rate of a digital video signal according to the CCIR recommendation 601 is 216 Mbit / s.
  • the simultaneous use of various methods for data reduction is therefore necessary.
  • One of these methods is the reduction of the temporal resolution by the fact that individual images are transmitted at longer time intervals than usual.
  • the recording itself can certainly take place at a customary frame rate, for example to counteract a reduction in the local resolution in the case of moving picture contents, but only the nth picture, for example every sixth picture, is transmitted from the recorded pictures.
  • EP-A-0 160 547 discloses a motion-adaptive interpolation method for image signals.
  • An image memory is controlled via a motion detector.
  • a memory for the motion vectors is controlled by a selector that selects the most frequently occurring motion vectors.
  • the object of the present invention is to provide a method and a circuit arrangement with which an interpolation between the received images can be carried out in a favorable manner and the reproduction of edges which separate stationary and moving image areas from one another is improved.
  • the inventive method with the features of main claim 11 has the advantage that both the local changes (movements) and the changes in brightness between two successively transmitted images are taken into account in the interpolation in an advantageous manner.
  • the transmitted digital signal is supplied at a data rate of 64 kbit / s at 1.
  • various data reduction methods have been used. One of these methods consists in reducing the motion resolution, with only every sixth field being transmitted. In the preceding coding, however, motion vectors were determined which describe the movement of image areas (so-called blocks) according to size and direction. These motion vectors are transmitted together with the other data.
  • the signals supplied at 1 are decoded in a decoder 2.
  • the decoder 2 outputs the respective data (brightness and possibly color) for each of the picture elements and an address characterizing the position of the respective picture element within the picture. These digital signals are output as an n- or m-bit wide data stream and are designated in the figure with DATA and ADR-WR.
  • the decoder 2 also separates the motion vectors MV from the input signals arriving at 1 - also as data MV-DATA and as associated addresses MV-ADR. Both the image data DATA and the motion vectors are initially stored in memories. For this purpose, three image memories 3, 4, 5 are provided for the image data and two memories 6, 7 are provided for the motion vectors, each of which can hold all image data or motion vectors of an image.
  • RAM Read-write memories
  • DI data inputs DI
  • DO data outputs DO
  • address inputs A are used as memories 3 to 7.
  • Memory of this type available as building blocks cannot generally be written and read at the same time, which is why three image memories 3, 4, 5 and two memories 6, 7 are provided for motion vectors in the exemplary embodiment.
  • the invention can also be implemented with two image memories and one memory for motion vectors.
  • the memories 3 to 7 are addressed by the decoder 2, while for the reading out the addressing takes place with the aid of addresses ADR-RD which are generated in an address generator 8.
  • addresses ADR-RD which are generated in an address generator 8.
  • multiplexers 9, 10, 11, 12, 13 are connected upstream of the address inputs A of the memories 3 to 7, which are also controlled by the address generator 8.
  • the decoder 2 also sends a start pulse PSP (picture start pulse) to a higher-level control circuit 14.
  • the control circuit 14 controls the address generator 8 and a data control circuit 15, with the aid of which the data read from the image memories 3 to 5 are fed to a further image memory 16 after appropriate processing.
  • the image memory 16 finally contains, in digital form, the information which is supplied to the picture tube 18 as a video signal via a digital / analog converter 17. Therefore, the memory 16 in hereinafter referred to as video memory (VRAM).
  • VRAM video memory
  • Various addresses can be supplied to the video memory 16 for writing and reading, for which purpose a multiplexer 19 is connected upstream of the address input A, the inputs of which are connected on the one hand to the address generator 8 and on the other hand to the picture tube control circuit 20.
  • This also controls other processes on the picture tube 18, such as horizontal and vertical deflection and beam blanking.
  • the picture tube control circuit 20 is able to exchange data with the superordinate control circuit 14.
  • An oscillator 21 is provided for clocking the picture tube control circuit 20.
  • the picture elements moved in this way can also change their brightness in addition to their position in the picture, not only the described local interpolation is carried out when deriving the intermediate pictures, but also an interpolation of the signal values.
  • the data of a picture element of two successive pictures are read out from one of the picture memories 3 to 5, the addresses differing from one another by the motion vector.
  • An intermediate value is formed in the data control circuit 15 from both data, which represent the signal value of the respective picture element or the gray value, which is written into the video memory 16.
  • three image memories 3 to 5 are provided for storing the image data, one of which is written with new image data, while image data for the image data from the other two Interpolation can be read out.
  • image data for the image data from the other two Interpolation can be read out.
  • two memories 6, 7 are required, one of which works in the write mode and the other in the read mode.
  • a received image B h-1 with an object 24, the image B h subsequently received and an interpolated intermediate image are shown in FIG. 2.
  • the display was limited to an interpolated intermediate image.
  • From the image B h-1 of the image capture to B h receiving the object 24 has moved by the motion vector MV.
  • the object 24 has become darker, which is indicated by tighter hatching.
  • To generate the intermediate image the object 24 has the same addresses with which it is in the image memory was registered, read out. However, it is written into the video memory 16 (FIG. 1) with addresses that have been changed by MV / 2.
  • the brightness values are interpolated between the image Bh-1 and the image Bh .
  • FIG. 3 which, as a block diagram, represents those parts of the circuit arrangement according to FIG. 1 that contribute to the interpolation process.
  • the parts which are required for writing to memories 3 to 7 (FIG. 1) have been omitted - as have the multiplexers which are used to switch between write and read operations.
  • FIG. 3 also does not show the cyclically interchanged reading out of the memories and the associated switchover devices, but merely represents a kind of snapshot in which 6 motion vectors are read from the memory and image data from two successively received images are read out from the memories 3, 4.
  • the addresses ADR-RD generated by the picture tube control circuit 20 form the basis for all the addresses used for reading out in the circuit arrangement according to FIG Read out from the image memory 3 and used directly from the memory 6 - in In the case of the memory 6, however, only some of the higher-order binary positions, since there is only one motion vector for a group of picture elements (block).
  • the image memory 4 is supplied with addresses which are derived by adding the addresses ADR-RD with the motion vectors read from the memory 6.
  • An adder 27 is provided for this. The addition is done separately for both directions.
  • An interpolation control circuit 28 controls both local and amplitude interpolation.
  • the image start pulse PSP and a signal M for identifying stationary or moving image areas are fed to this circuit.
  • the latter is obtained with the aid of a comparator 29, to which signal 0 is supplied on the one hand and the respective motion vector is supplied on the other.
  • a multiplier 30 and an adder 31 serve for local interpolation, the output signals of which can be supplied to the video memory 16 as addresses ADR-WR via the multiplexer 19.
  • the amplitude interpolation takes place with the aid of two multipliers 32, 33, which are connected to the data outputs of the image memories 3 and 4 and whose output signals can be fed to the data input of the video memory 16 via an adder 34.
  • An adder 35 and a changeover switch 36 are switched on in the supply of the addresses from the picture tube control circuit 20 to the multiplexer 19.
  • a further memory 37 and a further multiplexer 38 are also provided.
  • a motion vector the size of, for example, six picture elements and that the brightness of the pixel under consideration changes from 40 to 100% of the maximum value changes.
  • the penultimate image is stored in the image memory 3 and the image last received is stored in the image memory 4.
  • the first picture to be displayed on the picture tube 18 and accordingly to be written into the video memory 16 corresponds to the picture stored in the picture memory 3. Addresses corresponding to the addresses for reading out from the image memory 3 are therefore required to generate the addresses for writing into the video memory 16.
  • a coefficient a k generated by the interpolation control circuit 28 is set to 0, so that the motion vector in the multiplier 30 is multiplied by 0 and the addresses ADR-RD are passed on unchanged by the adder 31.
  • the interpolation control circuit 28 also forms two mutually complementary coefficients b k and b kN .
  • k is the ordinal number of one of the images to be displayed from a received image
  • N is the number of images to be displayed per received image.
  • the received image thus written into the video memory 16 is read unchanged from the video memory 16 and fed to the picture tube 18 via the digital / analog converter 17.
  • the vertical component of the addresses ADR-RD 2 is added, as a result of which the readout from the video memory 16 leads by two lines over the write-in. This avoids changes in the memory content always taking place after reading, even if they are noticeable as a result of the movement interpolation below the line defined by the addresses ADR-RD.
  • FIGS. 4 and 5 schematically show partial areas of transmitted and displayed images.
  • the time is plotted horizontally, while the position of the respective picture elements is shown in the vertical or horizontal direction in the vertical.
  • FIG. 5 shows a view of the corresponding screen image, the chronological sequence also being shown.
  • the partial area shown it comprises two objects 127, 128 which are not hatched in front of one shaded background 129 are visible. Together with the image B h data is transmitted motion vectors. Because the objects 127, 128 move in the foreground are MV 127, MV 128 equal to 0, while for those picture elements representing the background 129, the h transferred to the image B motion vectors are the same 0th
  • the image B h-1 is written into the image memory 3 during reception.
  • the position of the objects 127, 128 has changed due to the movement.
  • the object 127 has moved 6 picture elements to the right and six picture elements downwards, while the object 128 has been shifted by six picture elements to the right and six picture elements upwards.
  • the image B is completely transferred and h in the frame memory 4 (Fig. 1) is stored.
  • a further image B h + 1 which is not shown in FIGS. 4 and 5, is then transmitted and stored in the image memory 5.
  • the image memory 4 is switched from write to read mode, so that images B h-1 and B h are simultaneously available for further processing and are correspondingly read out from image memories 3 and 4 in the circuit arrangement according to FIG. 3 can.
  • the image B 1 to be displayed is obtained by interpolating the amplitude values of the respective image points of the images B h-1 and B h and by shifting the respective image elements.
  • the representations in FIGS. 4 and 5 only consider the displacement of the picture elements, but not their amplitude interpolation in detail. The latter is only indicated in FIG. 4 as the composition of a picture element 132 from picture elements of pictures B h-1 and B h by corresponding arrows 133, 134.
  • the released picture elements to describe the background with background information of the image B h This is shown in Fig. 4 by dashed arrows.
  • the background information is written into the memory cells of the video memory 16, the content of which is shifted, is carried out with a corresponding design of the interpolation control circuit 28 and with the aid of the memory 37 and the multiplexer 38. Background information from the image Bh is only then transferred into a memory cell written if the memory cell has not already been addressed for writing a shifted picture element and if there is a motion vector for the picture element in question.
  • This information is stored in the memory 37. Since the size of the motion vector is limited in narrowband image transmission systems, it is sufficient to store one binary position for the image elements of a few lines, for example 4. This is shown schematically in FIG. 6, the number of picture elements per line being limited to 12 for the sake of clarity. For example, due to the continuous addressing by the picture tube control circuit 20, the picture element 143 addressed, a 1 is written into another memory cell of the memory 37 corresponding to the fraction of the motion vector. This only happens in the directions of the motion vectors shown in FIG. 6. In the example considered below, a 1 is written into the memory cell 44. When processing the following line, line 0 of memory 37 is no longer required and is used as the fourth line by appropriate addressing, etc.
  • For each picture element it is first checked whether this picture element or the corresponding memory cell has already been addressed during the previous lines. This is recognized by a 1 in the corresponding memory cell of the memory 37, whereupon the background information is not written into the memory cell of the video memory 16.
  • the information present in the corresponding memory cell of the image memory 3 is written into another memory cell in accordance with the above-mentioned interpolation rules.
  • the evaluation of the information as to whether addressing has taken place and whether there is a motion vector can be carried out with the logic circuit shown in FIG. 7. This is fed via an input 51, the binary position respectively read from the memory 37, and via an input 52, the output signal of the comparator 29 (FIG. 3), which states that a motion vector is present.
  • the binary position read out from the memory 37 is inverted with the aid of an inverter 53 and supplied to an AND circuit 54 together with the signal from the input 52 the output 55 of which a signal is present which controls the writing of the respective memory cell with background information.
  • the output signal of the inverter 53 has a logic level of 1. Furthermore, the other input of the AND circuit 54 has logic level 1 applied when there is movement. This results in logic level 1 at output 55, which means that the corresponding memory cell is written with the background information.
  • the interpolation control circuit 28 can advantageously be implemented by a logic switching mechanism in which, among other things, a link according to FIG. 7 is stored as a table. Further tables then contain the different coefficients a k , b k and b kN as well as a series of control signals, for example for the multiplexers.
  • the control for writing to the video memory 16, in particular the decision as to whether background information should be written into a memory cell can also be carried out with the program shown in FIG. 8 when using a microprocessor in the interpolation control circuit.
  • the program branches at 58. If the query yields a 1, this means that addressing has already taken place, so that the program leaves the corresponding cell of the video memory 16 unchanged. However, the content of the memory cell of the memory 37 which has just been queried is deleted. However, if the query yielded a 0, a further branch 59 takes place after branch 58, depending on the presence of movement. If the motion vector is greater than 0, the corresponding one is used Memory cell of the video memory 16 written background information. However, if there is no movement, the memory cell content of the previous image is written into the memory cell in program part 62. (Only an interpolation of the gray values is carried out).
  • the switchover clock for the multiplexer 19 is shown in line a, 0 being the left position of the multiplexer 19, in which one write address per clock is supplied by the adder 31.
  • addresses are supplied by the changeover switch 36.
  • a read address is first supplied, in which the line component is increased by 2 compared to the address ADR-RD.
  • the changeover switch 36 is moved by a corresponding control signal from the interpolation control circuit 28 into the left position, so that the unchanged address ADR-RD is fed to the address input of the video memory 16.
  • Line b of FIG. 9 shows a clock signal with which an input register of the digital / analog converter 17 is clocked.
  • the content of the memory cell addressed by the address ADDR-RD + 2 is read out for the edges of the clock signal highlighted by the arrows.
  • Line c of FIG. 9 shows a write signal WR which is supplied to a corresponding input of the video memory 16 by the interpolation control circuit 28.
  • the signal WR consists of two interleaved pulse series, of which the pulses WR1 are only supplied to the video memory 16 if the relevant memory cell is written with a background.
  • the Address ADR-RD at the memory cell and the multipliers 32, 33 are controlled by the interpolation control circuit 28 in such a way that the background information is read out from the image memory 4 and supplied to the video memory 16.
  • the address ADR-WR is located at the address input of the video memory 16, so that a different memory cell is written according to the movement to be interpolated, or the same if the motion vector is 0.
  • the result that is obtained with the aid of multipliers 32, 33 and adder 34 is present at the data input DI of video memory 16.
  • the read address ADDR-RD + 2 is present at the address input of the video memory 16, so that a picture element located two lines lower is read out. This enables an undisturbed reading of the image previously written into the video memory 16 without being disturbed by processes when the new image is being written.

Description

Die Erfindung geht aus von einem Verfahren gemäß dem Oberbegriff des Patentanspruchs 1. Ein solches Verfahren ist bekannt aus "Signal Processing, Vol. 11, 1986, Dezember, No. 4, Amsterdam; Seiten 387 bis 404; M. Bierling and R. Thoma: Motion compensating field interpolation using a hierarchically structured displacement estimator".The invention is based on a method according to the preamble of claim 1. Such a method is known from "Signal Processing, Vol. 11, 1986, December, No. 4, Amsterdam; pages 387 to 404; M. Bierling and R. Thoma : Motion compensating field interpolation using a hierarchically structured displacement estimator ".

Zur Übertragung von bewegten Bildern werden sehr große Kanalkapazitäten benötigt. So beträgt beispielsweise die Datenrate eines digitalen Videosignals nach der CCIR-Empfehlung 601 216 Mbit/s. Zur Übertragung von bewegten Bildern mit Hilfe von Übertragungskanälen mit wesentlich geringerer Datenrate, wie beispielsweise dem ISDN-64 Netz, ist daher die gleichzeitige Anwendung verschiedener Verfahren zur Datenreduktion erforderlich. Eines dieser Verfahren ist die Verringerung der zeitlichen Auflösung dadurch, daß Einzelbilder in größeren zeitlichen Abständen als üblich übertragen werden. Dabei kann die Aufnahme selbst durchaus mit einer üblichen Bildfrequenz erfolgen, um beispielsweise einer Verringerung der örtlichen Auflösung bei bewegten Bildinhalten entgegenzuwirken, von den aufgenommenen Bildern wird jedoch nur jeweils das n-te Bild, beispielsweise jedes sechste Bild übertragen.Very large channel capacities are required to transmit moving images. For example, the data rate of a digital video signal according to the CCIR recommendation 601 is 216 Mbit / s. To transmit moving images with the aid of transmission channels with a significantly lower data rate, such as the ISDN-64 network, the simultaneous use of various methods for data reduction is therefore necessary. One of these methods is the reduction of the temporal resolution by the fact that individual images are transmitted at longer time intervals than usual. In this case, the recording itself can certainly take place at a customary frame rate, for example to counteract a reduction in the local resolution in the case of moving picture contents, but only the nth picture, for example every sixth picture, is transmitted from the recorded pictures.

Bei der Wiedergabe derart übertragener Signale ist es zur Vermeidung von Flimmern durch zu geringe Bildwiederholfrequenz bekannt, jedes übertragene Bild n-mal zu wiederholen. Dadurch werden jedoch Bewegungen ruckartig wiedergegeben, was besonders unangenehm ist. Es sind deshalb bereits Vorschläge bekannt geworden, die darzustellenden Bilder durch Interpolation aus den empfangenen Bildern abzuleiten.When reproducing signals transmitted in this way, it is known to avoid flickering due to an image refresh rate which is too low, to repeat each transmitted image n times. However, this will cause movements to be jerky, which is particularly uncomfortable. For this reason, proposals have already become known for deriving the images to be displayed from the received images by interpolation.

Bei dem Verfahren gemäß Signal Processing, Vol. 11, 1986, Dec., No. 4, Amsterdam, NL, Seiten 387-404, von M. Bierling und R. Thoma, erfolgt eine örtliche und zeitliche Interpolation von Zwischenbildern unter Berücksichtigung der Bewegung. Unbewegter Hintergrund wird dort aus einem der zwei empfangenen Bilder extrapoliert. Aus der EP-A-0 160 547 ist ein bewegungsadaptives Interpolationsverfahren für Bildsignale bekannt. Über einen Bewegungsdetektor wird ein Bildspeicher gesteuert. Ein Speicher für die Bewegungsvektoren wird über einen Selektor gesteuert, der die am häufigsten auftretenden Bewegungsvektoren auswählt.In the method according to Signal Processing, Vol. 11, 1986, Dec., No. 4, Amsterdam, NL, pages 387-404, by M. Bierling and R. Thoma, there is a spatial and temporal interpolation of intermediate images taking into account the movement. The unmoving background is extrapolated from one of the two received images. EP-A-0 160 547 discloses a motion-adaptive interpolation method for image signals. An image memory is controlled via a motion detector. A memory for the motion vectors is controlled by a selector that selects the most frequently occurring motion vectors.

Aufgabe der vorliegenden Erfindung ist es, ein Verfahren sowie eine Schaltungsanordnung anzugeben, mit welcher in günstiger Weise eine Interpolation zwischen den empfangenen Bildern durchgeführt werden kann und die Wiedergabe von Kanten, welche ruhende und bewegte Bildbereiche voneinander trennen, verbessert ist.The object of the present invention is to provide a method and a circuit arrangement with which an interpolation between the received images can be carried out in a favorable manner and the reproduction of edges which separate stationary and moving image areas from one another is improved.

Das erfindungsgemäße Verfahren mit den Merkmalen des Hauptanspruchs 11 hat den Vorteil, daß bei der Interpolation in vorteilhafter Weise sowohl die örtlichen Änderungen (Bewegungen) als auch die Änderungen der Helligkeit zwischen zwei aufeinanderfolgend übertragenen Bildern berücksichtigt werden.The inventive method with the features of main claim 11 has the advantage that both the local changes (movements) and the changes in brightness between two successively transmitted images are taken into account in the interpolation in an advantageous manner.

Diejenigen Bildelemente der darzustellenden Bilder, welche nicht durch Verschieben jeweils eines Bildelementes des empfangenen Bildes mit Information versehen sind, für die jedoch ein Bewegungsvektor des entsprechenden Bildelements des empfangenen Bildes vorliegt, werden mit Information aus dem jeweils folgenden empfangenen Bild versehen.Those picture elements of the pictures to be displayed which are not shifted by moving one picture element of the received image are provided with information, but for which there is a motion vector of the corresponding picture element of the received image, are provided with information from the following received image.

Da die Wiedergabe von Kanten, welche ruhende und bewegte Bildbereiche voneinander trennen, erheblich verbessert ist, ist die Wiedergabe von Hintergrundinformation, welche durch die Bewegung eines Objekts an dessen rückwärtiger Kante frei wird, ermöglicht.Since the reproduction of edges which separate resting and moving image areas from one another is considerably improved, the reproduction of background information which is released by the movement of an object at its rear edge is made possible.

Durch die in den abhängigen Ansprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen der im Hauptanspruch angegebenen Erfindung möglich. Insbesondere werden vorteilhafte Schaltungsanordnungen angegeben, die eine Durchführung des erfindungsgemäßen Verfahrens mit marktgängigen digitalen Bausteinen ermöglichen. Dabei wird in vorteilhafter Weise die Ansteuerung der verschiedenen Speicher bei der Darstellung des freiwerdenden Hintergrundes ermöglicht.The measures listed in the dependent claims allow advantageous developments and improvements of the invention specified in the main claim. In particular, advantageous circuit arrangements are specified which enable the method according to the invention to be carried out using commercially available digital components. In this case, the various memories can be activated in an advantageous manner in the representation of the background which becomes free.

Ausführungsbeispiele der Erfindung sind in der Zeichnung anhand mehrerer Figuren dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigt:

Fig. 1
ein Blockschaltbild einer Schaltungsanordnung zur Wiedergabe von übertragenen Videosignalen, wobei eine Bewegungsinterpolation vorgesehen ist,
Fig. 2
eine schematische Darstellung eines Bildes in mehreren Bewegungsphasen,
Fig. 3
als Blockschaltbild eine Schaltungsanordnung zur Bewegungsinterpolation,
Fig. 4
ein Zeitdiagramm zur Darstellung von bewegten Objekten,
Fig. 5
die gleichen bewegten Objekte als schematische Darstellung mehrerer überlagerter Schirmbilder,
Fig. 6
eine schematische Darstellung eines Speichers für die Information, ob einzelne Bildelemente durch Bewegungsinterpolation entstanden sind,
Fig. 7
eine Logikschaltung zur Steuerung des Schreibvorgangs in einem Videospeicher,
Fig. 8
ein Flußdiagramm und
Fig. 9
ein Zeitdiagramm verschiedener Steuersignale für einen Videospeicher.
Exemplary embodiments of the invention are shown in the drawing using several figures and are explained in more detail in the following description. It shows:
Fig. 1
2 shows a block diagram of a circuit arrangement for the reproduction of transmitted video signals, wherein motion interpolation is provided,
Fig. 2
1 shows a schematic representation of an image in several movement phases,
Fig. 3
a circuit arrangement for motion interpolation as a block diagram,
Fig. 4
a time diagram for the representation of moving objects,
Fig. 5
the same moving objects as a schematic representation of several superimposed screen images,
Fig. 6
1 shows a schematic representation of a memory for the information as to whether individual picture elements have arisen through motion interpolation,
Fig. 7
a logic circuit for controlling the writing process in a video memory,
Fig. 8
a flow chart and
Fig. 9
a timing diagram of various control signals for a video memory.

Gleiche Teile sind in den Figuren mit gleichen Bezugszeichen versehen.Identical parts are provided with the same reference symbols in the figures.

Der Schaltungsanordnung nach Fig. 1 wird bei 1 das übertragene digitale Signal mit einer Datenrate von 64 kbit/s zugeführt. Wie eingangs erwähnt, sind dabei verschiedene Datenreduktionsverfahren angewendet worden. Eines dieser Verfahren besteht in einer Reduzierung der Bewegungsauflösung, wobei nur jedes sechste Teilbild übertragen wird. Bei der vorangegangenen Codierung wurden jedoch Bewegungsvektoren ermittelt, welche die Bewegung von Bildbereichen (sogenannten Blöcken) nach Größe und Richtung beschreiben. Diese Bewegungsvektoren werden zusammen mit den übrigen Daten übertragen.1, the transmitted digital signal is supplied at a data rate of 64 kbit / s at 1. As mentioned at the beginning, various data reduction methods have been used. One of these methods consists in reducing the motion resolution, with only every sixth field being transmitted. In the preceding coding, however, motion vectors were determined which describe the movement of image areas (so-called blocks) according to size and direction. These motion vectors are transmitted together with the other data.

Die bei 1 zugeführten Signale werden in einem Decoder 2 decodiert. Von den im wesentlichen bekannten Funktionen des Decoders 2 sind nur die im folgenden erläuterten im Zusammenhang mit der vorliegenden Erfindung von Bedeutung. Innerhalb von 120 ms werden vom Decoder 2 nacheinander für jedes der Bildelemente die jeweiligen Daten (Helligkeit und gegebenenfalls Farbe) und eine die Position des jeweiligen Bildelements innerhalb des Bildes kennzeichnende Adresse ausgegeben. Diese digitalen Signale werden als n- bzw. m-bit breiter Datenstrom ausgegeben und sind in der Figur mit DATA und ADR-WR bezeichnet. Von dem Decoder 2 werden ferner aus den bei 1 ankommenden Eingangssignalen die Bewegungsvektoren MV separiert - und zwar ebenfalls als Daten MV-DATA und als zugehörige Adressen MV-ADR. Sowohl die Bilddaten DATA als auch die Bewegungsvektoren werden zunächst in Speichern abgelegt. Dazu sind für die Bilddaten drei Bildspeicher 3, 4, 5 und für die Bewegungsvektoren zwei Speicher 6, 7 vorgesehen, welche jeweils sämtliche Bilddaten bzw. Bewegungsvektoren eines Bildes aufnehmen können.The signals supplied at 1 are decoded in a decoder 2. Of the essentially known functions of the decoder 2, only those explained below are of importance in connection with the present invention. Within 120 ms, the decoder 2 outputs the respective data (brightness and possibly color) for each of the picture elements and an address characterizing the position of the respective picture element within the picture. These digital signals are output as an n- or m-bit wide data stream and are designated in the figure with DATA and ADR-WR. The decoder 2 also separates the motion vectors MV from the input signals arriving at 1 - also as data MV-DATA and as associated addresses MV-ADR. Both the image data DATA and the motion vectors are initially stored in memories. For this purpose, three image memories 3, 4, 5 are provided for the image data and two memories 6, 7 are provided for the motion vectors, each of which can hold all image data or motion vectors of an image.

Als Speicher 3 bis 7 werden Schreib-Lese-Speicher (RAM) mit Dateneingängen DI, Datenausgängen DO und Adresseneingängen A verwendet. Als Bausteine erhältliche Speicher dieser Art sind im allgemeinen nicht gleichzeitig beschreibbar und lesbar, deshalb sind bei dem Ausführungsbeispiel drei Bildspeicher 3, 4, 5 und zwei Speicher 6, 7 für Bewegungsvektoren vorgesehen. Ohne diese Beschränkung kann die Erfindung auch mit zwei Bildspeichern und einem Speicher für Bewegungsvektoren ausgeführt werden.Read-write memories (RAM) with data inputs DI, data outputs DO and address inputs A are used as memories 3 to 7. Memory of this type available as building blocks cannot generally be written and read at the same time, which is why three image memories 3, 4, 5 and two memories 6, 7 are provided for motion vectors in the exemplary embodiment. Without this limitation, the invention can also be implemented with two image memories and one memory for motion vectors.

Zum Einschreiben der Bilddaten und Bewegungsvektoren werden die Speicher 3 bis 7 von dem Decoder 2 adressiert, während zum Auslesen die Adressierung mit Hilfe von Adressen ADR-RD erfolgt, die in einem Adressengenerator 8 erzeugt werden. Den Adresseneingängen A der Speicher 3 bis 7 sind zur Umschaltung zwischen den Schreib- und Leseadressen Multiplexer 9, 10, 11, 12, 13 vorgeschaltet, die ebenfalls vom Adressengenerator 8 gesteuert werden.For writing in the image data and motion vectors, the memories 3 to 7 are addressed by the decoder 2, while for the reading out the addressing takes place with the aid of addresses ADR-RD which are generated in an address generator 8. For switching between the write and read addresses, multiplexers 9, 10, 11, 12, 13 are connected upstream of the address inputs A of the memories 3 to 7, which are also controlled by the address generator 8.

Vom Decoder 2 wird ferner pro Bild ein Startimpuls PSP (Picture start pulse) an eine übergeordnete Steuerschaltung 14 abgegeben. Die Steuerschaltung 14 steuert wiederum den Adressengenerator 8 und eine Datensteuerschaltung 15, mit deren Hilfe die aus den Bildspeichern 3 bis 5 gelesenen Daten einem weiteren Bildspeicher 16 nach entsprechender Verarbeitung zugeleitet werden. Der Bildspeicher 16 enthält schließlich in digitaler Form die Information, welche über einen Digital/Analog-Wandler 17 der Bildröhre 18 als Videosignal zugeführt wird. Deshalb wird der Speicher 16 im folgenden als Videospeicher (VRAM) bezeichnet.The decoder 2 also sends a start pulse PSP (picture start pulse) to a higher-level control circuit 14. The control circuit 14 in turn controls the address generator 8 and a data control circuit 15, with the aid of which the data read from the image memories 3 to 5 are fed to a further image memory 16 after appropriate processing. The image memory 16 finally contains, in digital form, the information which is supplied to the picture tube 18 as a video signal via a digital / analog converter 17. Therefore, the memory 16 in hereinafter referred to as video memory (VRAM).

Dem Videospeicher 16 sind zum Einschreiben und Lesen verschiedene Adressen zuführbar, wozu ein Multiplexer 19 dem Adresseneingang A vorgeschaltet ist, dessen Eingänge einerseits mit dem Adressengenerator 8 und andererseits mit der Bildröhren-Steuerschaltung 20 verbunden sind. Diese steuert ferner weitere Vorgänge an der Bildröhre 18, wie Horizontal- und Vertikalablenkung und Strahlaustastung. Außerdem ist die Bildröhren-Steuerschaltung 20 in der Lage, mit der übergeordneten Steuerschaltung 14 Daten auszutauschen. Zur Taktung der Bildröhren-Steuerschaltung 20 ist ein Oszillator 21 vorgesehen.Various addresses can be supplied to the video memory 16 for writing and reading, for which purpose a multiplexer 19 is connected upstream of the address input A, the inputs of which are connected on the one hand to the address generator 8 and on the other hand to the picture tube control circuit 20. This also controls other processes on the picture tube 18, such as horizontal and vertical deflection and beam blanking. In addition, the picture tube control circuit 20 is able to exchange data with the superordinate control circuit 14. An oscillator 21 is provided for clocking the picture tube control circuit 20.

Während des Empfangs jeweils eines Bildes werden sechs Bilder aus dem Videospeicher 16 ausgelesen und auf dem Schirm der Bildröhre 18 dargestellt. Von diesen sechs Bildern ist bei bewegten Bildern jedoch nur eines dem zuvor empfangenen Bild gleich, die weiteren fünf Bilder werden durch Interpolation zwischen diesem Bild und dem danach empfangenen Bild gewonnen. Dabei wird davon ausgegangen, daß zwischen einem und dem folgenden empfangenen Bild eine Bewegung entsprechend dem zusammen mit dem einen empfangenen Bild übertragenen Bewegungsvektor stattgefunden hat. Ein derart bewegtes Bildelement wird in den nicht empfangenen darzustellenden Bildern (Zwischenbildern) von Bild zu Bild entsprechend dem jeweiligen Anteil am Bewegungsvektor verschoben in den Videospeicher 16 eingeschrieben. Nach dem Einschreiben des empfangenen Bildes in den Videospeicher 16 werden dementsprechend die Adressen für das folgende darzustellende Zwischenbild um 1/6 der Größe des Bewegungsvektors MV verändert. Beim folgenden Zwischenbild werden die Adressen zum Einschreiben in den Videospeicher 16 um 2/6 geändert usw.. Dieses erfolgt jeweils für eine horizontale und eine vertikale Komponente MVX und MVY des Bewegungsvektors.During the reception of one image, six images are read out from the video memory 16 and displayed on the screen of the picture tube 18. In the case of moving images, however, only one of these six images is the same as the image previously received; the other five images are obtained by interpolation between this image and the image received afterwards. It is assumed that between one and the following received image there has been a movement corresponding to the motion vector transmitted together with the one received image. A picture element that is moved in this way is written into the video memory 16, shifted from picture to picture in the non-received pictures to be displayed (intermediate pictures) in accordance with the respective proportion of the motion vector. After the received image has been written into the video memory 16, the addresses for the following intermediate image to be displayed are accordingly changed by 1/6 the size of the motion vector MV. In the following intermediate image, the addresses for writing into the video memory 16 are changed by 2/6, etc. This is done for a horizontal and a vertical component MVX and MVY of the motion vector.

Da die derart bewegten Bildelemente außer ihrer Lage im Bild auch ihre Helligkeit ändern können, wird bei der Ableitung der Zwischenbilder nicht nur die beschriebene örtliche Interpolation, sondern auch noch eine Interpolation der Signalwerte vorgenommen. Dazu werden aus einem der Bildspeicher 3 bis 5 jeweils die Daten eines Bildelementes zweier aufeinanderfolgender Bilder ausgelesen, wobei sich die Adressen um den Bewegungsvektor voneinander unterscheiden. In der Daten-Steuerschaltung 15 wird aus beiden Daten, welche den Signalwert des jeweiligen Bildelementes bzw. den Grauwert darstellen, ein Zwischenwert gebildet, der in den Videospeicher 16 eingeschrieben wird.Since the picture elements moved in this way can also change their brightness in addition to their position in the picture, not only the described local interpolation is carried out when deriving the intermediate pictures, but also an interpolation of the signal values. For this purpose, the data of a picture element of two successive pictures are read out from one of the picture memories 3 to 5, the addresses differing from one another by the motion vector. An intermediate value is formed in the data control circuit 15 from both data, which represent the signal value of the respective picture element or the gray value, which is written into the video memory 16.

Damit die beschriebenen Interpolationsvorgänge durchgeführt werden können, während gleichzeitig ein weiteres Bild decodiert und gespeichert wird, sind für die Speicherung der Bilddaten drei Bildspeicher 3 bis 5 vorgesehen, von denen jeweils einer mit neuen Bilddaten beschrieben wird, während aus den zwei anderen Bildspeichern Bilddaten für die Interpolation ausgelesen werden. Zur Zwischenspeicherung der Bewegungsvektoren sind lediglich zwei Speicher 6, 7 erforderlich, von denen jeweils einer im Schreib- und der andere im Lesebetrieb arbeitet.So that the interpolation processes described can be carried out while a further image is being decoded and stored at the same time, three image memories 3 to 5 are provided for storing the image data, one of which is written with new image data, while image data for the image data from the other two Interpolation can be read out. To temporarily store the motion vectors, only two memories 6, 7 are required, one of which works in the write mode and the other in the read mode.

Zur weiteren Erläuterung der bewegungsabhängigen Interpolation sind in Fig. 2 ein empfangenes Bild Bh-1 mit einem Objekt 24, das danach empfangene Bild Bh sowie ein interpoliertes Zwischenbild dargestellt. Der Einfachheit halber wurde die Darstellung auf ein interpoliertes Zwischenbild beschränkt. Von der Aufnahme des Bildes Bh-1 bis zur Aufnahme des Bildes Bh hat sich das Objekt 24 um den Bewegungsvektor MV bewegt. Ferner ist das Objekt 24 dunkler geworden, was mit einer engeren Schraffur angedeutet ist. Zur Erzeugung des Zwischenbildes wird das Objekt 24 mit den gleichen Adressen, mit denen es in den Bildspeicher eingeschrieben wurde, ausgelesen. Es wird jedoch mit Adressen, welche um MV/2 verändert sind, in den Videospeicher 16 (Fig. 1) eingeschrieben. Außerdem erfolgt eine Interpolation der Helligkeitswerte zwischen dem Bild Bh-1 und dem Bild Bh. Ergänzend sei noch erwähnt, daß die dargestellte Interpolation nur zufriedenstellend erfolgt, wenn die Bewegungsvektoren hinreichend genau mit der tatsächlichen Bewegung des Bildes übereinstimmen. Eine geeignete Schaltungsanordnung zur Schätzung von Bewegung in einem aufgenommenen Bild, bei welcher Bewegungsvektoren erzeugt werden, ist in der Patentanmeldung P 38 34 477.7 der Anmelderin beschrieben.To further explain the motion-dependent interpolation, a received image B h-1 with an object 24, the image B h subsequently received and an interpolated intermediate image are shown in FIG. 2. For the sake of simplicity, the display was limited to an interpolated intermediate image. From the image B h-1 of the image capture to B h receiving the object 24 has moved by the motion vector MV. Furthermore, the object 24 has become darker, which is indicated by tighter hatching. To generate the intermediate image, the object 24 has the same addresses with which it is in the image memory was registered, read out. However, it is written into the video memory 16 (FIG. 1) with addresses that have been changed by MV / 2. In addition, the brightness values are interpolated between the image Bh-1 and the image Bh . In addition, it should be mentioned that the interpolation shown is only satisfactory if the motion vectors match the actual motion of the image with sufficient accuracy. A suitable circuit arrangement for estimating motion in a recorded image, in which motion vectors are generated, is described in the applicant's patent application P 38 34 477.7.

Bei den weiteren Erläuterungen wird auf Fig. 3 Bezug genommen, welche als Blockschaltbild diejenigen Teile der Schaltungsanordnung nach Fig. 1 darstellt, die zum Interpolationsvorgang beitragen. Der Übersichtlichkeit halber wurden diejenigen Teile, welche für das Beschreiben der Speicher 3 bis 7 (Fig. 1) erforderlich sind, fortgelassen - ebenso wie die Multiplexer, die zur Umschaltung zwischen Schreib- und Lesebetrieb dienen. Schließlich zeigt Fig. 3 auch nicht das zyklisch vertauschte Auslesen aus den Speichern und die dazugehörigen Umschalteinrichtungen, sondern stellt lediglich eine Art Momentaufnahme dar, bei welcher aus dem Speicher 6 Bewegungsvektoren und aus den Speichern 3, 4 Bilddaten zweier aufeinanderfolgend empfangener Bilder ausgelesen werden.In the further explanations, reference is made to FIG. 3, which, as a block diagram, represents those parts of the circuit arrangement according to FIG. 1 that contribute to the interpolation process. For the sake of clarity, the parts which are required for writing to memories 3 to 7 (FIG. 1) have been omitted - as have the multiplexers which are used to switch between write and read operations. Finally, FIG. 3 also does not show the cyclically interchanged reading out of the memories and the associated switchover devices, but merely represents a kind of snapshot in which 6 motion vectors are read from the memory and image data from two successively received images are read out from the memories 3, 4.

Die Grundlage für alle bei der Schaltungsanordnung nach Fig. 3 zum Auslesen verwendeten Adressen stellen die von der Bildröhren-Steuerschaltung 20 erzeugten Adressen ADR-RD dar. Diese umfassen jeweils eine Vertikal- und eine Horizontalkomponente, die entsprechend dem Zeilenraster inkrementiert werden, und werden zum Auslesen aus dem Bildspeicher 3 und aus dem Speicher 6 direkt verwendet - im Falle des Speichers 6 jedoch nur einige der höherwertigen Binärstellen, da für eine Gruppe von Bildelementen (Block) nur ein Bewegungsvektor vorliegt. Dem Bildspeicher 4 werden Adressen zugeführt, welche durch Addition der Adressen ADR-RD mit den aus dem Speicher 6 ausgelesenen Bewegungsvektoren abgeleitet werden. Dazu ist ein Addierer 27 vorgesehen. Die Addition erfolgt jeweils für beide Richtungen getrennt.The addresses ADR-RD generated by the picture tube control circuit 20 form the basis for all the addresses used for reading out in the circuit arrangement according to FIG Read out from the image memory 3 and used directly from the memory 6 - in In the case of the memory 6, however, only some of the higher-order binary positions, since there is only one motion vector for a group of picture elements (block). The image memory 4 is supplied with addresses which are derived by adding the addresses ADR-RD with the motion vectors read from the memory 6. An adder 27 is provided for this. The addition is done separately for both directions.

Eine Interpolations-Steuerschaltung 28 steuert sowohl die örtliche als auch die amplitudenmäßige Interpolation. Dieser Schaltung werden der Bildstartimpuls PSP sowie ein Signal M zur Kennzeichnung von ruhenden bzw. bewegten Bildbereichen zugeführt. Letzteres wird mit Hilfe eines Komparators 29 gewonnen, welchem einerseits das Signal 0 und andererseits der jeweilige Bewegungsvektor zugeführt wird. Zur örtlichen Interpolation dienen ein Multiplizierer 30 sowie ein Addierer 31, dessen Ausgangssignale als Adressen ADR-WR über den Multiplexer 19 dem Videospeicher 16 zuführbar sind. Die amplitudenmäßige Interpolation erfolgt mit Hilfe von zwei Multiplizierern 32, 33, die an die Datenausgänge der Bildspeicher 3 und 4 angeschlossen sind und deren Ausgangssignale über einen Addierer 34 dem Dateneingang des Videospeichers 16 zuführbar sind.An interpolation control circuit 28 controls both local and amplitude interpolation. The image start pulse PSP and a signal M for identifying stationary or moving image areas are fed to this circuit. The latter is obtained with the aid of a comparator 29, to which signal 0 is supplied on the one hand and the respective motion vector is supplied on the other. A multiplier 30 and an adder 31 serve for local interpolation, the output signals of which can be supplied to the video memory 16 as addresses ADR-WR via the multiplexer 19. The amplitude interpolation takes place with the aid of two multipliers 32, 33, which are connected to the data outputs of the image memories 3 and 4 and whose output signals can be fed to the data input of the video memory 16 via an adder 34.

In die Zuleitung der Adressen von der Bildröhren-Steuerschaltung 20 zum Multiplexer 19 ist ein Addierer 35 sowie ein Umschalter 36 eingeschaltet. Außerdem ist ein weiterer Speicher 37 und weiterer Multiplexer 38 vorgesehen.An adder 35 and a changeover switch 36 are switched on in the supply of the addresses from the picture tube control circuit 20 to the multiplexer 19. A further memory 37 and a further multiplexer 38 are also provided.

Für die folgende Beschreibung der Funktion der Schaltungsanordnung nach Fig. 3 sei angenommen, daß ein Bewegungsvektor der Größe von beispielsweise sechs Bildelementen vorliegt und daß sich die Helligkeit des betrachteten Bildpunktes von 40 auf 100 % des Maximalwertes ändert. In dem Bildspeicher 3 ist das vorletzte, in dem Bildspeicher 4 das zuletzt empfangene Bild abgelegt. Das erste auf der Bildröhre 18 darzustellende und dementsprechend in den Videospeicher 16 einzuschreibende Bild entspricht dem im Bildspeicher 3 abgelegten Bild. Zur Erzeugung der Adressen zum Einschreiben in den Videospeicher 16 werden daher Adressen benötigt, die den Adressen zum Auslesen aus dem Bildspeicher 3 entsprechen. Dazu wird ein von der Interpolations-Steuerschaltung 28 erzeugter Koeffizient ak auf 0 gesetzt, so daß der Bewegungsvektor im Multiplizierer 30 mit 0 multipliziert wird und die Adressen ADR-RD unverändert vom Addierer 31 weitergeleitet werden.For the following description of the function of the circuit arrangement according to FIG. 3, it is assumed that there is a motion vector the size of, for example, six picture elements and that the brightness of the pixel under consideration changes from 40 to 100% of the maximum value changes. The penultimate image is stored in the image memory 3 and the image last received is stored in the image memory 4. The first picture to be displayed on the picture tube 18 and accordingly to be written into the video memory 16 corresponds to the picture stored in the picture memory 3. Addresses corresponding to the addresses for reading out from the image memory 3 are therefore required to generate the addresses for writing into the video memory 16. For this purpose, a coefficient a k generated by the interpolation control circuit 28 is set to 0, so that the motion vector in the multiplier 30 is multiplied by 0 and the addresses ADR-RD are passed on unchanged by the adder 31.

Von der Interpolations-Steuerschaltung 28 werden ferner zwei zueinander komplementäre Koeffizienten bk und bk-N gebildet. Dabei ist k die Ordnungszahl eines der von einem empfangenen Bild abzuleitenden darzustellenden Bilder, während N die Anzahl der darzustellenden Bilder pro empfangenen Bild bedeutet. Zum Auslesen des dem empfangenen Bild gleichenden ersten darzustellenden Bildes wird bk = 1 gesetzt, während bk-N = 0 ist.The interpolation control circuit 28 also forms two mutually complementary coefficients b k and b kN . Here, k is the ordinal number of one of the images to be displayed from a received image, while N is the number of images to be displayed per received image. To read out the first image to be displayed, which is the same as the received image, b k = 1 is set, while b kN = 0.

Das somit in den Videospeicher 16 eingeschriebene empfangene Bild wird unverändert aus dem Videospeicher 16 ausgelesen und über den Digital/Analog-Wandler 17 der Bildröhre 18 zugeführt. Mit Hilfe der Addierschaltung 35 wird der vertikalen Komponente der Adressen ADR-RD 2 hinzuaddiert, wodurch das Auslesen aus dem Videospeicher 16 um zwei Zeilen gegenüber dem Einschreiben voreilt. Damit wird vermieden, daß Änderungen des Speicherinhalts stets nach dem Auslesen erfolgen, selbst wenn sie sich infolge der Bewegungsinterpolation unterhalb der durch die Adressen ADR-RD jeweils festgelegten Zeile bemerkbar machen.The received image thus written into the video memory 16 is read unchanged from the video memory 16 and fed to the picture tube 18 via the digital / analog converter 17. With the aid of the adder circuit 35, the vertical component of the addresses ADR-RD 2 is added, as a result of which the readout from the video memory 16 leads by two lines over the write-in. This avoids changes in the memory content always taking place after reading, even if they are noticeable as a result of the movement interpolation below the line defined by the addresses ADR-RD.

Nach dem Einschreiben des empfangenen Bildes in den Videospeicher 16 werden die Daten für ein erstes Zwischenbild ermittelt und in den Videospeicher 16 eingeschrieben. Dieses erfolgt derart, daß von der Interpolations-Steuerschaltung Koeffizienten a1 = 1/6, b1 = 5/6 und b1-N = 1/6 den Multiplizierern 30, 32, 33 zugeführt werden. Unter der eingangs erwähnten Annahme, daß MV = 6 ist, wird den Adressen ADR-RD der Wert 1 im Addierer 31 hinzuaddiert. Die aus dem Bildspeicher 3 ausgelesenen Bilddaten werden mit 5/6 und die aus dem Bildspeicher 4 ausgelesenen Bilddaten mit 1/6 multipliziert. Die Ergebnisse der Multiplikation werden im Addierer 34 addiert und dem Dateneingang des Videospeichers 16 zugeführt. Von darzustellendem Bild zu darzustellendem Bild werden ak und bk-N jeweils um 1/6 erhöht, während bk um 1/6 vermindert wird.After the received image has been written into the video memory 16, the data for a first intermediate image are determined and written into the video memory 16. This is done in such a way that coefficients a 1 = 1/6, b 1 = 5/6 and b 1-N = 1/6 are supplied to the multipliers 30, 32, 33 by the interpolation control circuit. Under the assumption mentioned at the beginning that MV = 6, the value 1 in the adder 31 is added to the addresses ADR-RD. The image data read out from the image memory 3 are multiplied by 5/6 and the image data read out from the image memory 4 by 1/6. The results of the multiplication are added in the adder 34 and fed to the data input of the video memory 16. From the image to be displayed to the image to be displayed, a k and b kN are each increased by 1/6, while b k is decreased by 1/6.

Im folgenden wird die Ableitung der darzustellenden Bilder anhand der Figuren 4 und 5 nochmals erläutert - insbesondere im Hinblick darauf, daß bei der Bewegtbildübertragung meistens bewegte und stehende Bildbestandteile vorhanden sind. Dieses ist beispielsweise der Fall, wenn sich eine im Vordergrund befindliche Person gegenüber dem Hintergrund bewegt.In the following, the derivation of the images to be displayed will be explained again with the aid of FIGS. 4 and 5 - in particular with regard to the fact that moving and stationary image components are usually present during the moving image transmission. This is the case, for example, when a person in the foreground moves against the background.

Die Figuren 4 und 5 zeigen schematisch Teilbereiche von übertragenen und darzustellenden Bildern. In Fig. 4 ist in der Waagerechten die Zeit aufgetragen, während in der Senkrechten die Lage der jeweiligen Bildelemente in horizontaler oder vertikaler Richtung dargestellt ist. Demgegenüber stellt Fig. 5 eine Ansicht des entsprechenden Schirmbildes dar, wobei der zeitliche Ablauf ebenfalls dargestellt ist. In dem ersten in Fig. 4 dargestellten Zeitabschnitt von t = 0 bis t = 120 ms wird ein erstes Bild Bh-1 empfangen. Es umfaßt in dem dargestellten Teilbereich zwei Objekte 127, 128, die schraffiert vor einem nicht schraffiert dargestellten Hintergrund 129 sichtbar sind. Zusammen mit den Daten des Bildes Bh werden Bewegungsvektoren übertragen. Da sich die Objekte 127, 128 im Vordergrund bewegen, sind MV127, MV128 ungleich 0, während für diejenigen Bildelemente, welche den Hintergrund 129 darstellen, die mit dem Bild Bh übertragenen Bewegungsvektoren gleich 0 sind.FIGS. 4 and 5 schematically show partial areas of transmitted and displayed images. In Fig. 4, the time is plotted horizontally, while the position of the respective picture elements is shown in the vertical or horizontal direction in the vertical. In contrast, FIG. 5 shows a view of the corresponding screen image, the chronological sequence also being shown. A first image Bh-1 is received in the first time period shown in FIG. 4 from t = 0 to t = 120 ms. In the partial area shown, it comprises two objects 127, 128 which are not hatched in front of one shaded background 129 are visible. Together with the image B h data is transmitted motion vectors. Because the objects 127, 128 move in the foreground are MV 127, MV 128 equal to 0, while for those picture elements representing the background 129, the h transferred to the image B motion vectors are the same 0th

Das Bild Bh-1 wird während des Empfangs in den Bildspeicher 3 eingeschrieben. Bei dem folgenden Bild Bh hat sich die Lage der Objekte 127, 128 durch die Bewegung verändert. Dabei hat sich das Objekt 127 um 6 Bildelemente nach rechts und sechs Bildelemente nach unten bewegt, während das Objekt 128 um sechs Bildelemente nach rechts und sechs Bildelemente nach oben verschoben ist. Bei t = 240 ms ist das Bild Bh vollständig übertragen und im Bildspeicher 4 (Fig. 1) abgelegt. Danach wird ein weiteres Bild Bh+1 übertragen, das in Fig. 4 und 5 nicht dargestellt ist, und im Bildspeicher 5 abgelegt.The image B h-1 is written into the image memory 3 during reception. In the following image B h , the position of the objects 127, 128 has changed due to the movement. The object 127 has moved 6 picture elements to the right and six picture elements downwards, while the object 128 has been shifted by six picture elements to the right and six picture elements upwards. At t = 240 ms, the image B is completely transferred and h in the frame memory 4 (Fig. 1) is stored. A further image B h + 1 , which is not shown in FIGS. 4 and 5, is then transmitted and stored in the image memory 5.

Während zwischen t = 0 und t = 240 ms empfangene Bilder dargestellt sind, zeigt Fig. 4 zwischen t = 240 ms bis t = 360 ms darzustellende Bilder. Zur Verdeutlichung dessen ist in Fig. 4 bei t = 240 ms eine Doppellinie vorgesehen. Zu diesem Zeitpunkt wird der Bildspeicher 4 vom Schreib- in den Lesebetrieb geschaltet, so daß die Bilder Bh-1 und Bh gleichzeitig zur weiteren Verarbeitung zur Verfügung stehen und aus den Bildspeichern 3 und 4 in der Schaltungsanordnung nach Fig. 3 entsprechend ausgelesen werden können.While images received between t = 0 and t = 240 ms are shown, FIG. 4 shows images to be displayed between t = 240 ms to t = 360 ms. To illustrate this, a double line is provided in FIG. 4 at t = 240 ms. At this time, the image memory 4 is switched from write to read mode, so that images B h-1 and B h are simultaneously available for further processing and are correspondingly read out from image memories 3 and 4 in the circuit arrangement according to FIG. 3 can.

Von t = 240 ms bis t = 360 ms werden sechs darzustellende Bilder abgeleitet, in den Videospeicher 16 (Fig. 3) eingeschrieben, wieder ausgelesen und auf der Bildröhre 18 dargestellt. Dabei entspricht das erste darzustellende Bild B0 dem Bild Bh-1. Wie bereits im Zusammenhang mit Fig. 3 erwähnt, wird es unverändert bezüglich der Amplitudenwerte und der Lage der Bildelemente vom Bildspeicher 3 ausgelesen und in den Videospeicher 16 eingeschrieben, was in Fig. 4 durch einen Pfeil 130 hervorgehoben ist. Das gleiche erfolgt mit dem Bild Bh für ein weiteres Bild B0 (Pfeil 131).From t = 240 ms to t = 360 ms, six images to be displayed are derived, written into the video memory 16 (FIG. 3), read out again and displayed on the picture tube 18. The first image B 0 to be displayed corresponds to image B h-1 . As already mentioned in connection with FIG. 3, it remains unchanged with regard to the amplitude values and the position of the picture elements from the picture memory 3 and written into the video memory 16, which is highlighted in FIG. 4 by an arrow 130. The same is done with the image B h for another image B 0 (arrow 131).

Das darzustellende Bild B1 wird durch Interpolation der Amplitudenwerte der jeweiligen Bildpunkte der Bilder Bh-1 und Bh sowie durch eine Verschiebung der jeweiligen Bildelemente gewonnen. Bei den Darstellungen in den Figuren 4 und 5 wird der Einfachheit halber nur die Verschiebung der Bildelemente betrachtet, nicht jedoch deren Amplituden-Interpolation im einzelnen. Letztere ist in Fig. 4 lediglich als Zusammensetzung eines Bildelementes 132 aus Bildelementen der Bilder Bh-1 und Bh durch entsprechende Pfeile 133, 134 angedeutet.The image B 1 to be displayed is obtained by interpolating the amplitude values of the respective image points of the images B h-1 and B h and by shifting the respective image elements. For the sake of simplicity, the representations in FIGS. 4 and 5 only consider the displacement of the picture elements, but not their amplitude interpolation in detail. The latter is only indicated in FIG. 4 as the composition of a picture element 132 from picture elements of pictures B h-1 and B h by corresponding arrows 133, 134.

Da zwischen aufeinanderfolgenden empfangenen Bildern eine lineare Bewegung angenommen wird, erfolgt die Verschiebung von darzustellendem Bild zu darzustellendem Bild um jeweils 1/6 des Bewegungsvektors - bei der angenommenen Größe der Bewegungsvektoren, also jeweils um ein Bildelement nach rechts und unten bzw. oben. Dementsprechend ist im Bild Bk=1 das Objekt 127 um ein Bildelement nach unten und das Objekt 128 um ein Bildelement nach oben gegenüber deren Lage im darzustellenden Bild Bk=0 verschoben. Da die den Hintergrund 129 betreffenden Bewegungsvektoren gleich 0 sind, erfolgt keine Verschiebung der zugehörigen Bildelemente. Es steht deshalb zunächst auch keine Information für die Bildelemente des Hintergrundes zur Verfügung, welche durch die Bewegung der Objekte frei werden, beispielsweise die Bildelemente 135, 136, 137, 138. Um das Freibleiben des Bildelements 135 zu verdeutlichen, ist mit einem Pfeil 139 in Fig. 4 dargestellt, daß das Bildelement 140 des Hintergrundes lediglich für das entsprechende Bildelement 141 des darzustellenden Bildes Bk=1 "reicht".Since a linear movement is assumed between successive received images, the image to be displayed is shifted by 1/6 of the motion vector at the assumed size of the motion vectors, i.e. by one picture element to the right and down or up. Accordingly, in image B k = 1, object 127 is shifted down by one picture element and object 128 is shifted up by one picture element relative to its position in the picture B k = 0 to be displayed. Since the motion vectors relating to the background 129 are equal to 0, the associated picture elements are not shifted. For this reason, there is initially no information available for the picture elements of the background, which become free due to the movement of the objects, for example picture elements 135, 136, 137, 138. In order to clarify that picture element 135 remains free, an arrow 139 in shows FIG. 4 shows that the picture element 140 of the background "is sufficient" only for the corresponding picture element 141 of the picture to be displayed B k = 1 .

Gemäß einer Weiterbildung der Erfindung ist vorgesehen, die freiwerdenden Bildelemente des Hintergrundes mit Hintergrundinformation des Bildes Bh zu beschreiben. Dieses ist in Fig. 4 durch gestrichelte Pfeile dargestellt. Das Einschreiben der Hintergrundinformation in die Speicherzellen des Videospeichers 16, deren Inhalt verschoben ist, geschieht mit einer entsprechenden Auslegung der Interpolations-Steuerschaltung 28 sowie mit Hilfe des Speichers 37 und des Multiplexers 38. Dabei wird Hintergrundinformation aus dem Bild Bh nur dann in eine Speicherzelle geschrieben, wenn die Speicherzelle nicht bereits zum Einschreiben eines verschobenen Bildelements adressiert wurde und wenn für das betreffende Bildelement ein Bewegungsvektor vorliegt.According to a further development of the invention, the released picture elements to describe the background with background information of the image B h. This is shown in Fig. 4 by dashed arrows. The background information is written into the memory cells of the video memory 16, the content of which is shifted, is carried out with a corresponding design of the interpolation control circuit 28 and with the aid of the memory 37 and the multiplexer 38. Background information from the image Bh is only then transferred into a memory cell written if the memory cell has not already been addressed for writing a shifted picture element and if there is a motion vector for the picture element in question.

Bei Bewegungen nach oben oder nach links kann dazu derart vorgegangen werden, daß zunächst alle Speicherzellen bei Vorliegen eines Bewegungsvektors beschrieben werden und danach die Hintergrundinformation durch die Bildelemente der nach oben bzw. links bewegten Objekte überschrieben wird. Bei Bewegungen nach unten würden bei diesem Verfahren jedoch Speicherzellen mit durch die Interpolation entstandenen Bildelementen mit Hintergrund überschrieben. Deshalb wird überprüft, ob der Inhalt jeweils einer Speicherzelle dem Einschreiben des jeweils darzustellenden Bildes bereits adressiert war.In the case of movements upwards or to the left, it is possible to proceed in such a way that first all memory cells in the presence of a movement vector are written and then the background information is overwritten by the picture elements of the objects moving upwards or to the left. In the case of movements downward, this method would overwrite memory cells with picture elements with the background created by interpolation. It is therefore checked whether the content of each memory cell was already addressed when the image to be displayed was written.

Diese Information ist im Speicher 37 abgelegt. Da bei Schmalband-Bildübertragungssystemen die Größe des Bewegungsvektors begrenzt ist, genügt es, jeweils eine Binärstelle für die Bildelemente einiger Zeilen, beispielsweise 4, zu speichern. Dieses ist in Fig. 6 schematisch dargestellt, wobei die Zahl der Bildelemente pro Zeile der Übersichtlichkeit halber auf 12 begrenzt ist. Wird beispielsweise aufgrund der fortlaufenden Adressierung durch die Bildröhren-Steuerschaltung 20 das Bildelement 143 angesprochen, so wird entsprechend dem Bruchteil des Bewegungsvektors in eine andere Speicherzelle des Speichers 37 eine 1 eingeschrieben. Dieses geschieht nur bei den in Fig. 6 dargestellten Richtungen der Bewegungsvektoren. Bei dem im folgenden betrachteten Beispiel wird in die Speicherzelle 44 eine 1 eingeschrieben. Bei der Bearbeitung der folgenden Zeile wird die Zeile 0 des Speichers 37 nicht mehr benötigt und durch entsprechende Adressierung als vierte Zeile verwendet usw.This information is stored in the memory 37. Since the size of the motion vector is limited in narrowband image transmission systems, it is sufficient to store one binary position for the image elements of a few lines, for example 4. This is shown schematically in FIG. 6, the number of picture elements per line being limited to 12 for the sake of clarity. For example, due to the continuous addressing by the picture tube control circuit 20, the picture element 143 addressed, a 1 is written into another memory cell of the memory 37 corresponding to the fraction of the motion vector. This only happens in the directions of the motion vectors shown in FIG. 6. In the example considered below, a 1 is written into the memory cell 44. When processing the following line, line 0 of memory 37 is no longer required and is used as the fourth line by appropriate addressing, etc.

Die in Fig. 6 dargestellten, jeweils mit einer Binärstelle pro Bildelement im Speicher 37 gespeicherten Zeilen 1 bis 4 wandern dadurch mit dem Schreibvorgang in den Videospeicher 16 mit. Dabei wird bei jedem Bildelement zunächst geprüft, ob dieses Bildelement bzw. die entsprechende Speicherzelle bereits während der vorangegangenen Zeilen adressiert wurde. Dieses wird an einer 1 in der entsprechenden Speicherzelle des Speichers 37 erkannt, worauf von dem Einschreiben der Hintergrundinformation in die Speicherzelle des Videospeichers 16 abgesehen wird. Unmittelbar danach wird bei Vorhandensein eines Bewegungsvektors die in der entsprechenden Speicherzelle des Bildspeichers 3 vorhandene Information nach Maßgabe der obengenannten Interpolationsregeln in eine andere Speicherzelle eingeschrieben.Lines 1 to 4 shown in FIG. 6, each with one binary position per picture element in the memory 37, thereby migrate to the video memory 16 during the writing process. For each picture element, it is first checked whether this picture element or the corresponding memory cell has already been addressed during the previous lines. This is recognized by a 1 in the corresponding memory cell of the memory 37, whereupon the background information is not written into the memory cell of the video memory 16. Immediately afterwards, in the presence of a motion vector, the information present in the corresponding memory cell of the image memory 3 is written into another memory cell in accordance with the above-mentioned interpolation rules.

Die Auswertung der Information, ob eine Adressierung stattgefunden hat und 0b ein Bewegungsvektor vorliegt, kann mit der in Fig. 7 dargestellten Logikschaltung vorgenommen werden. Dieser wird über einen Eingang 51 die jeweils aus dem Speicher 37 ausgelesene Binärstelle und über einen Eingang 52 das Ausgangssignal des Komparators 29 (Fig. 3) zugeführt, welches besagt, daß ein Bewegungsvektor vorliegt. Die aus dem Speicher 37 ausgelesene Binärstelle wird mit Hilfe eines Invertierers 53 invertiert und gemeinsam mit dem Signal vom Eingang 52 einer Und-Schaltung 54 zugeführt, an dessen Ausgang 55 ein Signal ansteht, welches das Beschreiben der jeweiligen Speicherzelle mit Hintergrundinformation steuert.The evaluation of the information as to whether addressing has taken place and whether there is a motion vector can be carried out with the logic circuit shown in FIG. 7. This is fed via an input 51, the binary position respectively read from the memory 37, and via an input 52, the output signal of the comparator 29 (FIG. 3), which states that a motion vector is present. The binary position read out from the memory 37 is inverted with the aid of an inverter 53 and supplied to an AND circuit 54 together with the signal from the input 52 the output 55 of which a signal is present which controls the writing of the respective memory cell with background information.

Hat also beispielsweise keine Adressierung stattgefunden, weist das Ausgangssignal des Invertierers 53 einen logischen Pegel von 1 auf. Ferner ist der andere Eingang der Und-Schaltung 54 mit dem logischen Pegel 1 beaufschlagt, wenn Bewegung vorliegt. Daraus ergibt sich der logische Pegel 1 am Ausgang 55, was bedeutet, daß die entsprechende Speicherzelle mit der Hintergrundinformation beschrieben wird.If, for example, no addressing has taken place, the output signal of the inverter 53 has a logic level of 1. Furthermore, the other input of the AND circuit 54 has logic level 1 applied when there is movement. This results in logic level 1 at output 55, which means that the corresponding memory cell is written with the background information.

Die Interpolations-Steuerschaltung 28 kann in vorteilhafter Weise durch ein logisches Schaltwerk verwirklicht werden, in welchem unter anderem eine Verknüpfung gemäß Fig. 7 als Tabelle abgelegt ist. Weitere Tabellen enthalten dann die verschiedenen Koeffizienten ak, bk und bk-N sowie eine Reihe von Steuersignalen, beispielsweise für die Multiplexer.The interpolation control circuit 28 can advantageously be implemented by a logic switching mechanism in which, among other things, a link according to FIG. 7 is stored as a table. Further tables then contain the different coefficients a k , b k and b kN as well as a series of control signals, for example for the multiplexers.

Die Steuerung zum Beschreiben des Videospeichers 16, insbesondere die Entscheidung, ob in eine Speicherzelle Hintergrundinformation eingeschrieben werden soll, kann bei der Verwendung eines Mikroprozessors in der Interpolations-Steuerschaltung auch mit dem in Fig. 8 dargestellten Programm erfolgen. Nach einer Abfrage 57 der jeweiligen Speicherzelle des Speichers 37 erfolgt eine Verzweigung des Programms bei 58. Hat die Abfrage eine 1 ergeben, bedeutet dieses, daß bereits eine Adressierung stattgefunden hat, so daß das Programm die entsprechende Zelle des Videospeichers 16 unverändert läßt. Der Inhalt der soeben abgefragten Speicherzelle des Speichers 37 wird jedoch gelöscht. Hat die Abfrage jedoch eine 0 ergeben, erfolgt nach der Verzweigung 58 eine weitere Verzweigung 59 in Abhängigkeit vom Vorliegen von Bewegung. Ist der Bewegungsvektor größer als 0, wird in die betreffende Speicherzelle des Videospeichers 16 Hintergrundinformation eingeschrieben. Liegt jedoch keine Bewegung vor, so wird im Programmteil 62 der Speicherzelleninhalt des vorhergehenden Bildes in die Speicherzelle geschrieben. (Es wird nur eine Interpolation der Grauwerte durchgeführt).The control for writing to the video memory 16, in particular the decision as to whether background information should be written into a memory cell, can also be carried out with the program shown in FIG. 8 when using a microprocessor in the interpolation control circuit. After a query 57 of the respective memory cell of the memory 37, the program branches at 58. If the query yields a 1, this means that addressing has already taken place, so that the program leaves the corresponding cell of the video memory 16 unchanged. However, the content of the memory cell of the memory 37 which has just been queried is deleted. However, if the query yielded a 0, a further branch 59 takes place after branch 58, depending on the presence of movement. If the motion vector is greater than 0, the corresponding one is used Memory cell of the video memory 16 written background information. However, if there is no movement, the memory cell content of the previous image is written into the memory cell in program part 62. (Only an interpolation of the gray values is carried out).

Im folgenden wird anhand von Fig. 9 die Steuerung des Videospeichers 16 (Fig. 3) erläutert. Dazu ist in Zeile a der Umschalttakt für den Multiplexer 19 dargestellt, wobei 0 die linke Stellung des Multiplexers 19 bedeutet, in welcher eine Schreibadresse pro Takt vom Addierer 31 zugeführt wird. Während der rechten Stellung des Multiplexers 19, die in Fig. 9 mit dem Pegel 1 gekennzeichnet ist, werden Adressen vom Umschalter 36 zugeführt. Während einer Phase des Umschaltsignals des Multiplexers wird zunächst eine Leseadresse zugeführt, bei welcher die Zeilenkomponente gegenüber der Adresse ADR-RD um 2 erhöht ist. Danach wird bei gleichem Pegel des Multiplexerschaltsignals der Umschalter 36 durch ein entsprechendes Steuersignal von der Interpolations-Steuerschaltung 28 in die linke Stelle bewegt, so daß die unveränderte Adresse ADR-RD dem Adresseneingang des Videospeichers 16 zugeführt wird.The control of the video memory 16 (FIG. 3) is explained below with reference to FIG. 9. For this purpose, the switchover clock for the multiplexer 19 is shown in line a, 0 being the left position of the multiplexer 19, in which one write address per clock is supplied by the adder 31. During the right position of the multiplexer 19, which is marked with the level 1 in FIG. 9, addresses are supplied by the changeover switch 36. During a phase of the switchover signal of the multiplexer, a read address is first supplied, in which the line component is increased by 2 compared to the address ADR-RD. Thereafter, at the same level of the multiplexer switching signal, the changeover switch 36 is moved by a corresponding control signal from the interpolation control circuit 28 into the left position, so that the unchanged address ADR-RD is fed to the address input of the video memory 16.

Zeile b der Fig. 9 zeigt ein Taktsignal, mit welchem ein Eingangsregister des Digital/Analog-Wandlers 17 getaktet wird. Zu den mit den Pfeilen hervorgehobenen Flanken des Taktsignals wird der Inhalt der durch die Adresse ADDR-RD + 2 angesprochenen Speicherzelle ausgelesen.Line b of FIG. 9 shows a clock signal with which an input register of the digital / analog converter 17 is clocked. The content of the memory cell addressed by the address ADDR-RD + 2 is read out for the edges of the clock signal highlighted by the arrows.

Zeile c der Fig. 9 zeigt ein Schreibsignal WR, das einem entsprechenden Eingang des Videospeichers 16 von der Interpolations-Steuerschaltung 28 zugeführt wird. Das Signal WR besteht aus zwei ineinander verschachtelten Impulsreihen, von denen die Impulse WR1 nur dann dem Videospeicher 16 zugeführt werden, wenn die betreffende Speicherzelle mit Hintergrund beschrieben wird. Zu diesem Zeitpunkt liegt die Adresse ADR-RD an der Speicherzelle und die Multiplizierer 32, 33 werden von der Interpolations-Steuerschaltung 28 derart gesteuert, daß aus dem Bildspeicher 4 die Hintergrundinformation ausgelesen und dem Videospeicher 16 zugeführt wird. Während der regelmäßig auftretenden Impulse WR2 liegt die Adresse ADR-WR am Adresseneingang des Videospeichers 16, so daß entsprechend der zu interpolierenden Bewegung eine andere Speicherzelle beschrieben wird bzw. die gleiche, wenn der Bewegungsvektor gleich 0 ist. Dabei liegt am Dateneingang DI des Videospeichers 16 das Ergebnis an, das mit Hilfe der Multiplizierer 32, 33 und des Addierers 34 gewonnen wird.Line c of FIG. 9 shows a write signal WR which is supplied to a corresponding input of the video memory 16 by the interpolation control circuit 28. The signal WR consists of two interleaved pulse series, of which the pulses WR1 are only supplied to the video memory 16 if the relevant memory cell is written with a background. At this point the Address ADR-RD at the memory cell and the multipliers 32, 33 are controlled by the interpolation control circuit 28 in such a way that the background information is read out from the image memory 4 and supplied to the video memory 16. During the regularly occurring pulses WR2, the address ADR-WR is located at the address input of the video memory 16, so that a different memory cell is written according to the movement to be interpolated, or the same if the motion vector is 0. The result that is obtained with the aid of multipliers 32, 33 and adder 34 is present at the data input DI of video memory 16.

Während der danach auftretenden positiven Flanke des in Zeile b dargestellten Auslesesignals liegt am Adresseneingang des Videospeichers 16 die Leseadresse ADDR-RD + 2 an, so daß ein um zwei Zeilen tiefer gelegenes Bildelement ausgelesen wird. Dadurch wird ein ungestörtes Auslesen des zuvor in den Videospeicher 16 eingeschriebenen Bildes möglich, ohne daß es durch Vorgänge beim Einschreiben des neuen Bildes gestört wird.During the subsequent positive edge of the readout signal shown in line b, the read address ADDR-RD + 2 is present at the address input of the video memory 16, so that a picture element located two lines lower is read out. This enables an undisturbed reading of the image previously written into the video memory 16 without being disturbed by processes when the new image is being written.

Claims (11)

  1. Method for the reproduction of received video signals which represent frames of different motion phases of recorded objects, motion vectors being received in addition to the video signals and a plurality of frames being displayed within a frame period of the received video signals,
    - one of the frames to be displayed per received frame corresponding to a received frame, and
    - signals for further frames (intermediate frames) to be displayed being obtained from the signals of two successively received frames in that the pixels of the one received frame are displaced from intermediate frame to intermediate frame by a fraction of that motion vector of the received frame which is applicable to the respective pixel, the fraction being produced from the number of frames to be displayed per received frame, and
    - the amplitudes of the video signals of the pixels of the one received frame and of the pixels, removed by the motion vector, of the following received frame being averaged while taking account of the position of the respective pixel of the frame to be displayed between the corresponding pixels of the received frames,
    characterized in that those pixels (135-138) of the frames (Bh) to be displayed which are not provided with information by displacement of a respective pixel of the received frame (Bh-1), but for which a motion vector of the corresponding pixel of the received frame (Bh-1) exists, are provided with information from corresponding pixels of the respectively following received frame (Bh) if there does not already exist for these pixels (135-138) an item of information that they are overwritten by displaced pixels of the following frame (Bh) for which a motion vector exists.
  2. Circuit arrangement for carrying out the method according to Claim 1, in which
    in each case one frame store (3, 4) is provided for at least two successively received frames and at least one memory (6) is provided for the motion vectors of the one received frame and a further memory (video memory) (16) for storing a respective frame to be displayed is provided, and a respective computing circuit is connected downstream of the memory (6) for the motion vectors, on the one hand, and of the frame stores, on the other hand, the first computing circuit (30, 31) connected downstream of the memory (6) for the motion vectors is designed in such a way that it changes, as a function of the motion vector which is applicable to the respective pixel, the address of the pixel from intermediate frame to intermediate frame by a fraction of the motion vector,
    the second computing circuit (32, 33, 34) arranged downstream of the frame stores (3, 4) is designed in such a way that it in each case averages the signal values which are stored for a pixel in the one store and for a pixel removed by the motion vector in the other store, with weighting which varies from intermediate frame to intermediate frame, and in which
    an output of the first computing circuit (30, 31) is connected to an address input of the video memory (16), and an output of the second computing circuit (32, 33, 34) is connected to a data input of the video memory (16).
  3. Circuit arrangement according to Claim 2, characterized in that
    a further frame store (5) for a further received frame and a further memory (7) for motion vectors of a further received frame are provided,
    the frame stores (3, 4, 5) and the memories (6, 7) for the motion vectors can be changed over with respect to their write and read operation in such a way that the respectively received video signals are written to a respective frame store and the respectively received motion vectors are written to a memory for motion vectors, and
    motion vectors are read out from the other memory and [lacuna] are read out from the two other frame stores.
  4. Circuit arrangement according to Claim 2, characterized in that
    a picture tube control circuit (20) is provided which outputs, in synchronism with a frame written on a screen, addresses for the pixels of the frame,
    the addresses are fed to address inputs of a respective first frame store (3) and of the memory (6) for motion vectors and, after addition of the respective motion vector, to address inputs of a respective second frame store (4).
  5. Circuit arrangement according to Claim 4, characterized in that
    the addresses can further be fed to an adder (31) of the first computing circuit and, via a multiplexer (19) to address inputs of the video memory (16).
  6. Circuit arrangement according to Claim 2, characterized in that
    the first computing circuit comprises a multiplier (30), which is connected on the input side to a data output of the memory (6), and an adder (31) which is connected downstream and the output of which forms the output of the first computing circuit,
    the second computing circuit comprises two multipliers (32, 33), the inputs of which are connected to data outputs of the frame stores (3, 4), and an adder (34) which is connected downstream of the multipliers (32, 33) and the output of which forms the output of the second computing circuit, and
    coefficients which can be changed from intermediate frame to intermediate frame can be fed to the multipliers (30, 32, 33) by an interpolation control circuit (28).
  7. Circuit arrangement according to Claim 2, characterized in that
    a logic circuit (53, 54) is provided which ensures that information is written from the second frame store (4) to the video memory (16) for pixels which are stored in the video memory (16), are not derived by displacement of a pixel read out from the first frame store (3) and for which a motion vector exists.
  8. Circuit arrangement according to Claim 7, characterized in that
    the addresses and the output signals of the first computing circuit (30, 31) have a vertical component and a horizontal component, and
    the horizontal components and a plurality of least-significant bits (LSB), preferably two least-significant bits (LSB), of the vertical components of the addresses and of the output signals of the first computing circuit (30, 31) can be fed for reading and writing to a further memory (37), and
    information is stored in the further memory for identifying those memory cells of the video memory (16) which, when the video memory (16) is addressed for the purpose of writing information from one of the frame stores (3, 4), have already had information written to them during the derivation of the same intermediate frame, which information is derived in accordance with the motion vector, and
    if this information exists, the respective memory cell of the video memory (16) does not have information written to it from the frame store (3, 4).
  9. Circuit arrangement according to Claim 8, characterized in that
    the further memory (37) has a capacity of in each case one bit for the pixels of several lines.
  10. Circuit arrangement according to Claim 2, characterized in that
    the addresses have a vertical component and a horizontal component, and
    the vertical component of the addresses which are fed via the multiplexer (19) to the address inputs of the video memory (16) is increased by the largest possible vertical component of the motion vector divided by the number of frames to be displayed per received frame, with the result that the writing, as a function of the motion vector, to the video memory (16) in each case takes place only to memory locations which have already been read out for the purpose of displaying the frame.
  11. Method for the reproduction of received video signals which represent frames of different motion phases of recorded objects, motion vectors being received in addition to the video signals and a plurality of frames being displayed within a frame period of the received video signals, one of the frames to be displayed per received frame corresponding to a received frame, and signals for further frames (intermediate frames) to be displayed being derived from the signals of two successively received frames by means of local and amplitude interpolation while taking account of the brightness values, the motion vectors and the position of pixels of the respective intermediate frame between the pixels, assigned to one another by the motion vectors, of a received frame and of a following received frame, characterized in that those pixels (135-138) of the frames (Bh) to be displayed which are not provided with information by displacement of a respective pixel of the received frame (Bh-1), but for which a motion vector of the corresponding pixel of the received frame (Bh-1) exists, are provided with information from corresponding pixels of the respectively following received frame (Bh) if there does not already exist for these pixels (135-138) an item of information that they are overwritten by displaced pixels of the following frame (Bh) for which a motion vector exists.
EP90104310A 1989-03-25 1990-03-07 Method and circuit arrangement for the reproduction of received video signals Expired - Lifetime EP0389835B1 (en)

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DE3909921 1989-03-25
DE3909921A DE3909921A1 (en) 1989-03-25 1989-03-25 METHOD AND CIRCUIT FOR PLAYING RECEIVED VIDEO SIGNALS

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EP0389835A2 EP0389835A2 (en) 1990-10-03
EP0389835A3 EP0389835A3 (en) 1992-10-28
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DE69214855T2 (en) * 1991-02-06 1997-05-15 Gen Electric Fluoroscopic procedure with reduced x-ray dosage
USRE35456E (en) * 1991-02-06 1997-02-18 General Electric Company Fluoroscopic method with reduced x-ray dosage
US5400383A (en) * 1991-12-09 1995-03-21 General Electric Company Fluoroscopic imager with frame-filling apparatus
US5838380A (en) * 1994-09-30 1998-11-17 Cirrus Logic, Inc. Memory controller for decoding a compressed/encoded video data frame
US5808629A (en) * 1996-02-06 1998-09-15 Cirrus Logic, Inc. Apparatus, systems and methods for controlling tearing during the display of data in multimedia data processing and display systems

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JPH0644815B2 (en) * 1984-04-27 1994-06-08 日本電気株式会社 Moving body interpolation device

Non-Patent Citations (1)

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Title
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DE59010353D1 (en) 1996-07-11
EP0389835A3 (en) 1992-10-28
DE3909921A1 (en) 1990-09-27
EP0389835A2 (en) 1990-10-03

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