EP0383271A2 - Waveform shaping circuit and receiver using same - Google Patents
Waveform shaping circuit and receiver using same Download PDFInfo
- Publication number
- EP0383271A2 EP0383271A2 EP90102814A EP90102814A EP0383271A2 EP 0383271 A2 EP0383271 A2 EP 0383271A2 EP 90102814 A EP90102814 A EP 90102814A EP 90102814 A EP90102814 A EP 90102814A EP 0383271 A2 EP0383271 A2 EP 0383271A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- integrating circuit
- input signal
- input terminal
- integrating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007493 shaping process Methods 0.000 title claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 33
- 238000010586 diagram Methods 0.000 description 6
- 230000001052 transient effect Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/062—Setting decision thresholds using feedforward techniques only
Definitions
- This invention relates to a waveform shaping circuit which is so designed as to intermittently operate and adapted for use with a mobile communication apparatus, and a receiver using such a waveform shaping circuit. More particularly, this invention is directed to such an arrangement with an improved transient characteristic which occurs when an input signal having digital data mingled therewith is subjected to waveform-shaping.
- Figure 1 is a circuit diagram showing an example of conventional waveform shaping circuit adapted for use with a paging device or the like, wherein reference numeral 2 indicates an input terminal to which is applied an input signal such as a digital data signal having an arbitrary waveform or a digital data signal retaining a relatively square waveform, and reference numeral 3 indicates an output terminal at which is obtained a waveform-shaped digital data signal.
- reference numeral 2 indicates an input terminal to which is applied an input signal such as a digital data signal having an arbitrary waveform or a digital data signal retaining a relatively square waveform
- reference numeral 3 indicates an output terminal at which is obtained a waveform-shaped digital data signal.
- Resistors 25 and 26 are connected at one end to the input terminal 2 and also coupled at the opposite end to inverting input terminal and non-inverting input terminal of a differential amplifier 1 which has a feedback resistor 28 connected across the inverting input terminal and output terminal 3 thereof so as to constitute a feedback circuit.
- a capacitor 16 is coupled to the connection point between the resistor 25 and the non-inverting input terminal of the differential amplifier 1, and the collector of a transistor 29 is also connected thereto.
- a reference voltage source V R is connected to a terminal 20 which comprises the emitter of the transistor 29; and a terminal 13 is connected to the base of the transistor 29, and a control signal for boosting charge is applied thereto.
- the power source voltage is intermittently applied to a waveform shaping circuit, and the control signal for boosting charge is applied to the terminal 13 in synchronism with turning-on of the power source so that a charging current i c is supplied to the capacitor 16 through the transistor 19.
- Input signal is supplied to the non-inverting input terminal of the differential amplifier 1 through the resistor 26.
- the resistor 25 and capacitor 16 constitute an integrating circuit 27 by which the input signal is smoothed. Such smoothed input signal is passed to the differential amplifier via the non-inverting input terminal so that the input signal is subjected to waveform-shaping.
- the waveform shaping circuit comprises a differential amplifier having an input terminal to which a first input signal is applied and a second input terminal to which is applied an output obtained by integrating the input signal by means of a first integrating circuit; and a second integrating circuit provided at the front stage of the differential amplifier and having a higher time constant than that of the first integrating circuit, whereby a capacitor of the first integrating circuit is boost-charged with the output of the second integrating circuit so that the charge-discharge period of the capacitance is shortened so as to minimize occurrence of data error, and thus the waveform shaping circuit is well adapted for use with a receiver such as pager or the like.
- FIG. 3 there is shown the waveform shaping circuit according to an embodiment of the present invention, wherein resistors 4, 5 and 9 are connected at one end to an input terminal 2 to which an input signal superimposed upon a DC bias voltage is applied, the resistors 4 and 5 being connected at the other end to inverting input terminal and non-inverting input terminal of a differential amplifier 1, and a feedback resistor 8 is connected across the inverting input terminal and output terminal 3 of the differential amplifier.
- the resistor 5 is connected at the opposite end to a capacitor 6, so that an intergrating circuit 7.
- the resistor 9 is connected at the other end to a capacitor 10, so that an integrating circuit 11 is constituted by the resistor 9 and capacitor 10.
- connection point P1 between the resistor 9 and the capacitor 10 is coupled to an non-inverting input terminal of a differential amplifier 12 which constitutes a voltage-follower type buffer circuit, and inverting input terminal and output terminal of the differential amplifier 12 are connected together and tied to the connection point P2 between the resistor 5 and the capacitor 6.
- the differential amplifier 12 includes a control terminal 13 to which is applied a control signal for affecting boost-charging.
- the integrating circuit 11 and differential amplifier 12 constitute a boost-charging circuit for boost-charing the capicitor 6. Indicated at 3 is an output terminal at which a shaped pulse waveform is obtained.
- FIG. 4 there is illustrated the frequency characteristic of the integrating circuits 7 and 11, wherein the abscissa indicates the frequency of input signal, and the ordinate indicates the amplitude ratio of the input voltage V1 of the intergrating circuit to output voltage V2 thereof; f1 and f2 are cut-off frequencies of the integrating circuits 7 and 11 respectively; f3 is the minimum frequency of the input signal; and f4 is the maximum frequency of input signal. Description will be made of the integrating circuit with reference to the drawings.
- the resistance value for the feedback resistor 8 is made to be infinite, then such a signal that the amplitude ratio (V2/V1) of input voltage to output voltage is unity, is applied to the inverting terminal of the differential amplifier 1.
- V2/V1 the amplitude ratio of input voltage to output voltage is unity
- the amplitude level of the input signal applied to the non-inverting input terminal of the differential amplifier 1 be more precisely smoothed output of integration. More specifically, for boosting charge of the capacitor 6, it is required that the cut-off frequency f2 for the time constant C 1 ⁇ R9 of the integrating circuit 11 be set to be lower than the frequency of the input signal.
- the integrating circuits 7 and 11 comprise the resistor 5 and capacitor 6 and the resistor and capacitor 10 respectively, and their time constants C6R5 and C 1 ⁇ R9 are are set as follows: C6R5 > C 1 ⁇ R9 (1) where R5 and R9 are the resistance values for the resistors 5 and 9 respectively, and C6 and C 1 ⁇ are the capacitance values for the capacitors 6 and 10 respectively.
- the frequency characteristics of the integrating circuits 11 and 7 are as shown at (1) and (2) in Figure 4 respectively, and the relationship between the integrating circuits 7 and 11 can be represented in terms of cut-off frequencies f1 and f2 are as follows: f1 ⁇ f2 (2)
- the time constant C 1 ⁇ R9 of the integrating circuit 11 may be set up in consideration of a frequency f3 at which the input signal becomes minimum. More specifically, the time constant C 1 ⁇ R9 of the integrating circuit 11 is set up so that the following relationship holds between the cutoff frequency f2 for the time constant C 1 ⁇ R9 of the integrating circuit 11 and the frequency f3 at which the input signal becomes minimum: f2 ⁇ f3 (3)
- the waveform shaping circuit according to the present invention can operate even when with the cutoff frequency f2 as reference, the following relationship holds between the minimum and maximum frequencies f3 and f4 of the input signal: f3 ⁇ f2 ⁇ f4 (4)
- the waveform shaping circuit is provided with power source voltage to be rendered operative during the time period from t1 to t4; and during the time period from t1 to t2, control signal is applied for boosting charge in synchronism with an intermittent receiving signal (see Figure 5(II)).
- the waveform of the input signal at the input terminal 2 turns out to be as shown at (a) in Figure 5(III).
- connection point P1 in the integrating circuit 11 there appears a waveform resulting from integration of the input signal and building up from zero potential.
- the output amplitude of the integrating circuit 11 turns out to be attenuated relative to the input signal in accordance with the frequency characteristic of the integrating circuit 11.
- the voltage at the point P1 in the integrating circuit 11 is charged at the capacitor 6 through the differential amplifier 12, which is adapted to function as a buffer circuit for boosting charge, so that waveform occurring at point P2 during the charging period (t1 to t2) turns out to be as shown at (b).
- the waveform occurring at the point P2 drops depicting a discharge curve such such dotted curve (c).
- the potential at the point P2 reaches a level (d) corresponding to smoothed input signal superimposed upon DC bias voltage at the time point t3, and the input signal is subjected to waveform-shaping so that from the time point t3 onward, there is provided a pulse output having uniform duty ratio.
- discharge starts with the voltage (V R - V CE (SAT) ), whereas according to the present invention discharge of the capacitor starts with the level of the signal attenuated by the integrating circuit 11, so that the discharge time (t2 to t3) can be shortened.
- the time constant of the integrating circuit 7 is higher than that of the integrating circuit 11 as mentioned above; thus, the integrating circuit 7 performs slower integrating operation and provides, as reference voltage, an integration output corresponding to the input signal level to the non-inverting input terminal of the differential amplifier 1. In this way, the time period during which data error tends to occur, can be shortened.
- FIG. 6 there is shown the waveform shaping circuit according to another embodiment of the present invention.
- boost charge circuit 15 is different from that of the embodiment shown in Figure 3;
- input terminal 2 is connected to input terminal of differential amplifier circuit 12 adapted to serve as a voltage-follower type buffer circuit; and output terminal is connected to a resistor 14 the other end of which is connected to a capacitor 6.
- the resistor 14 and capacitor 6 constitute an integrating circuit 11.
- the capacitor 6 is shared by another integrating circuit 7.
- the difference between the time constants of the integrating circuits 7 and 11 depends on the difference between the resistance values for the resistors 5 and 14.
- the remainder of the circuit shown in Figure 6 is the same as that of the embodiment shown in Figure 3.
- Figure 7 is a block diagram showing an example of receiver using the waveform shaping circuit according to the present invention, which includes an antenna 16; a tuning and receiving circuit 17 comprising a detector circuit and so forth; a waveform shaping circuit 8 provided after the receiving circuit 17; and an output terminal 19 at which is obtained a waveform-shaped digital data singal which in turn is decoded.
- a pulsating digital data signal being transmitted is received and converted into a digital signal in the waveform shaping circuit 18.
- the waveform shaping circuit according to the present invention comprises two types of integrating circuits having different time constants which are connected to one of the input terminals of the differential amplifier, to the other input terminal of which an input signal is applied.
- the integrating circuit having the lower time constant attenuates the input signal; the output voltage of this integrating circuit is applied to the capacitor of the integrating circuit having the higher time constant to effect boost-charging of the capacitor, thereby minimizing transient fluctuation in the integrating circuit during intermittent operation. In this way, it is possible to shorten the time period during which data error tends to occur due to transient fluctuation resulting from the charging and discharging of the capacitor.
- the waveform shaping circuit according to the present invention is well adapted for use with a receiver such as pager or the like.
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
- This invention relates to a waveform shaping circuit which is so designed as to intermittently operate and adapted for use with a mobile communication apparatus, and a receiver using such a waveform shaping circuit. More particularly, this invention is directed to such an arrangement with an improved transient characteristic which occurs when an input signal having digital data mingled therewith is subjected to waveform-shaping.
- To have a better understanding of the present invention, description will first be made of the prior art with reference to Figures 1 and 2 of the accompanying drawings. Figure 1 is a circuit diagram showing an example of conventional waveform shaping circuit adapted for use with a paging device or the like, wherein
reference numeral 2 indicates an input terminal to which is applied an input signal such as a digital data signal having an arbitrary waveform or a digital data signal retaining a relatively square waveform, andreference numeral 3 indicates an output terminal at which is obtained a waveform-shaped digital data signal.Resistors input terminal 2 and also coupled at the opposite end to inverting input terminal and non-inverting input terminal of adifferential amplifier 1 which has afeedback resistor 28 connected across the inverting input terminal andoutput terminal 3 thereof so as to constitute a feedback circuit. Acapacitor 16 is coupled to the connection point between theresistor 25 and the non-inverting input terminal of thedifferential amplifier 1, and the collector of atransistor 29 is also connected thereto. A reference voltage source VR is connected to a terminal 20 which comprises the emitter of thetransistor 29; and aterminal 13 is connected to the base of thetransistor 29, and a control signal for boosting charge is applied thereto. - The power source voltage is intermittently applied to a waveform shaping circuit, and the control signal for boosting charge is applied to the
terminal 13 in synchronism with turning-on of the power source so that a charging current ic is supplied to thecapacitor 16 through thetransistor 19. Input signal is supplied to the non-inverting input terminal of thedifferential amplifier 1 through theresistor 26. Theresistor 25 andcapacitor 16 constitute an integrating circuit 27 by which the input signal is smoothed. Such smoothed input signal is passed to the differential amplifier via the non-inverting input terminal so that the input signal is subjected to waveform-shaping. - In the waveform shaping circuit of Figure 1, input signal is supplied to the
input terminal 2. The waveform of the input signal is shown at (a) in Figure 2(II). When the control signal for boosting charge is applied to thecontrol terminal 13 as shown in Figure 2(I), thetransistor 29 is rendered operative so that the charging current ic is caused to rapidly flow in thecapacitor 16 and thus charging voltage at thecapacitor 16 builds up as shown by a charging curve (b). The charging voltage increases up to a value close to a voltage (VR - VCE(SAT)) which is equal to the reference voltage VR minus the saturation voltage VCE(SAT) of thetransistor 29. When the control signal is interrupted, the voltage charged at thecapacitor 16 drops down to a voltage level (d) corresponding to the smoothed input signal superimposed upon DC bias voltage, as indicated by a discharge curve (c) (see Figure 2(II)). - As will be seen from Figure 2, it is during the time period t₁ to t₂ that data error tends to occur, and this discharge time period is proportional to the time constant of the integrating circuit 27. With this type of waveform shaping circuit, digital data signal with a constant duty ratio is more stably obtained as the time constant of the integrating circuit 27 is increased. Disadvantageously, however, as the time constant of the integrating circuit 27 increased, the time period (t₁ to t₂) during which data error tends to occur, i.e., the time period during which the reference voltage level occurring after the boosting charge transiently becomes astable, becomes longer.
- It is a primary object of the present invention to provide a waveform shaping circuit which is so designed that a digital data signal havintg an arbitrary waveform is rapidly converted into a pulse signal of a substantially uniform duty ratio, thereby minimizing transient fluctuation.
- It is another object of the present invention to provide a waveform shaping circuit which so designed that the time period during which data error tends to occur can be shortened as greatly as possible, and a receiver using such a waveform shaping circuit.
- Briefly stated, the waveform shaping circuit according to the present invention comprises a differential amplifier having an input terminal to which a first input signal is applied and a second input terminal to which is applied an output obtained by integrating the input signal by means of a first integrating circuit; and a second integrating circuit provided at the front stage of the differential amplifier and having a higher time constant than that of the first integrating circuit, whereby a capacitor of the first integrating circuit is boost-charged with the output of the second integrating circuit so that the charge-discharge period of the capacitance is shortened so as to minimize occurrence of data error, and thus the waveform shaping circuit is well adapted for use with a receiver such as pager or the like.
- Other objects, features and advantages of the present invention will become apparent from the ensuing description taken in conjunction with the accompanying drawings.
-
- Figure 1 is a circuit diagram showing an example of conventional waveform shaping circuit.
- Figure 2 is a view useful for explaining the operation of the conventional waveform shaping circuit.
- Figure 3 is a circuit diagram showing the waveform shaping circuit according to an embodiment of the present invention.
- Figure 4 is a view illustrating the frequency characteristic of an integrating circuit.
- Figure 5 is a view useful for explaining the operation of the waveform shaping circuit according to the present invention
- Figure 6 is a circuit diagram showing the waveform shaping circuit according to a second embodiment of the present invention.
- Figure 7 is a block diagram showing a receiver using the waveform shaping circuit of the present invention.
- Referring to Figure 3, there is shown the waveform shaping circuit according to an embodiment of the present invention, wherein
resistors input terminal 2 to which an input signal superimposed upon a DC bias voltage is applied, theresistors differential amplifier 1, and afeedback resistor 8 is connected across the inverting input terminal andoutput terminal 3 of the differential amplifier. Theresistor 5 is connected at the opposite end to acapacitor 6, so that anintergrating circuit 7. The resistor 9 is connected at the other end to a capacitor 10, so that an integrating circuit 11 is constituted by the resistor 9 and capacitor 10. The connection point P₁ between the resistor 9 and the capacitor 10 is coupled to an non-inverting input terminal of adifferential amplifier 12 which constitutes a voltage-follower type buffer circuit, and inverting input terminal and output terminal of thedifferential amplifier 12 are connected together and tied to the connection point P₂ between theresistor 5 and thecapacitor 6. Thedifferential amplifier 12 includes acontrol terminal 13 to which is applied a control signal for affecting boost-charging. Further, the integrating circuit 11 anddifferential amplifier 12 constitute a boost-charging circuit for boost-charing thecapicitor 6. Indicated at 3 is an output terminal at which a shaped pulse waveform is obtained. - Referring to Figure 4, there is illustrated the frequency characteristic of the integrating
circuits 7 and 11, wherein the abscissa indicates the frequency of input signal, and the ordinate indicates the amplitude ratio of the input voltage V₁ of the intergrating circuit to output voltage V₂ thereof; f₁ and f₂ are cut-off frequencies of the integratingcircuits 7 and 11 respectively; f₃ is the minimum frequency of the input signal; and f₄ is the maximum frequency of input signal. Description will be made of the integrating circuit with reference to the drawings. - If the resistance value for the
feedback resistor 8 is made to be infinite, then such a signal that the amplitude ratio (V₂/V₁) of input voltage to output voltage is unity, is applied to the inverting terminal of thedifferential amplifier 1. For waveform-shaping the input signal into an output pulse having a uniform duty ratio, it is required that the amplitude level of the input signal applied to the non-inverting input terminal of thedifferential amplifier 1 be more precisely smoothed output of integration. More specifically, for boosting charge of thecapacitor 6, it is required that the cut-off frequency f₂ for the time constant C1ØR₉ of the integrating circuit 11 be set to be lower than the frequency of the input signal. - The integrating
circuits 7 and 11 comprise theresistor 5 andcapacitor 6 and the resistor and capacitor 10 respectively, and their time constants C₆R₅ and C1ØR₉ are are set as follows:
C₆R₅ > C1ØR₉ (1)
where R₅ and R₉ are the resistance values for theresistors 5 and 9 respectively, and C₆ and C1Ø are the capacitance values for thecapacitors 6 and 10 respectively. - The frequency characteristics of the integrating
circuits 11 and 7 are as shown at (1) and (2) in Figure 4 respectively, and the relationship between the integratingcircuits 7 and 11 can be represented in terms of cut-off frequencies f₁ and f₂ are as follows:
f₁ < f₂ (2) - The time constant C1ØR₉ of the integrating circuit 11 may be set up in consideration of a frequency f₃ at which the input signal becomes minimum. More specifically, the time constant C1ØR₉ of the integrating circuit 11 is set up so that the following relationship holds between the cutoff frequency f₂ for the time constant C1ØR₉ of the integrating circuit 11 and the frequency f₃ at which the input signal becomes minimum:
f₂ < f₃ (3) - The cutoff frequencies f₁ and f₂ of the integrating
circuits 7 and 11 are given as follows:
f₁ = 1/2πC₆R₅
f₂ = 1/2πC₁₀R₉ - Needless to say, the waveform shaping circuit according to the present invention can operate even when with the cutoff frequency f₂ as reference, the following relationship holds between the minimum and maximum frequencies f₃ and f₄ of the input signal:
f₃ < f₂ < f₄ (4) - Description will now be made of the operation of the waveform shaping circuit set up as mentioned above.
- As shown in Figure 5 (I), the waveform shaping circuit is provided with power source voltage to be rendered operative during the time period from t₁ to t₄; and during the time period from t₁ to t₂, control signal is applied for boosting charge in synchronism with an intermittent receiving signal (see Figure 5(II)). In this case, the waveform of the input signal at the
input terminal 2 turns out to be as shown at (a) in Figure 5(III). At connection point P₁ in the integrating circuit 11, there appears a waveform resulting from integration of the input signal and building up from zero potential. The output amplitude of the integrating circuit 11 turns out to be attenuated relative to the input signal in accordance with the frequency characteristic of the integrating circuit 11. The voltage at the point P₁ in the integrating circuit 11 is charged at thecapacitor 6 through thedifferential amplifier 12, which is adapted to function as a buffer circuit for boosting charge, so that waveform occurring at point P₂ during the charging period (t₁ to t₂) turns out to be as shown at (b). At the time point t₂ when the control signal is interrupted, the waveform occurring at the point P₂ drops depicting a discharge curve such such dotted curve (c). Subsequently, the potential at the point P₂ reaches a level (d) corresponding to smoothed input signal superimposed upon DC bias voltage at the time point t₃, and the input signal is subjected to waveform-shaping so that from the time point t₃ onward, there is provided a pulse output having uniform duty ratio. With the conventional waveform shaping circuit, discharge starts with the voltage (VR - VCE (SAT)), whereas according to the present invention discharge of the capacitor starts with the level of the signal attenuated by the integrating circuit 11, so that the discharge time (t2 to t3) can be shortened. The time constant of the integratingcircuit 7 is higher than that of the integrating circuit 11 as mentioned above; thus, the integratingcircuit 7 performs slower integrating operation and provides, as reference voltage, an integration output corresponding to the input signal level to the non-inverting input terminal of thedifferential amplifier 1. In this way, the time period during which data error tends to occur, can be shortened. - Referring to Figure 6, there is shown the waveform shaping circuit according to another embodiment of the present invention. wherein the arrangement of
boost charge circuit 15 is different from that of the embodiment shown in Figure 3;input terminal 2 is connected to input terminal ofdifferential amplifier circuit 12 adapted to serve as a voltage-follower type buffer circuit; and output terminal is connected to aresistor 14 the other end of which is connected to acapacitor 6. Theresistor 14 andcapacitor 6 constitute an integrating circuit 11. Thecapacitor 6 is shared by another integratingcircuit 7. The difference between the time constants of the integratingcircuits 7 and 11 depends on the difference between the resistance values for theresistors - While integrating circuits are used in the waveform shaping circuits according to the embodiments of Figures 3 and 6, it is also possible that use may be made of rectifying-smoothing circuits instead of such integrating circuits.
- Figure 7 is a block diagram showing an example of receiver using the waveform shaping circuit according to the present invention, which includes an
antenna 16; a tuning and receivingcircuit 17 comprising a detector circuit and so forth; awaveform shaping circuit 8 provided after the receivingcircuit 17; and anoutput terminal 19 at which is obtained a waveform-shaped digital data singal which in turn is decoded. A pulsating digital data signal being transmitted is received and converted into a digital signal in thewaveform shaping circuit 18. - As will be appreciated from the above discussion, the waveform shaping circuit according to the present invention comprises two types of integrating circuits having different time constants which are connected to one of the input terminals of the differential amplifier, to the other input terminal of which an input signal is applied. The integrating circuit having the lower time constant attenuates the input signal; the output voltage of this integrating circuit is applied to the capacitor of the integrating circuit having the higher time constant to effect boost-charging of the capacitor, thereby minimizing transient fluctuation in the integrating circuit during intermittent operation. In this way, it is possible to shorten the time period during which data error tends to occur due to transient fluctuation resulting from the charging and discharging of the capacitor. Thus, the waveform shaping circuit according to the present invention is well adapted for use with a receiver such as pager or the like.
- While the present invention has been illustrated and described with respect embodiments thereof, it is to be understood that the present invention is by no way limited thereto but encompasses all changes and modifications which will become possible within the scope of the appended claims.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1037010A JP2707461B2 (en) | 1989-02-16 | 1989-02-16 | Waveform shaping circuit |
JP37010/89 | 1989-02-16 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0383271A2 true EP0383271A2 (en) | 1990-08-22 |
EP0383271A3 EP0383271A3 (en) | 1992-03-11 |
EP0383271B1 EP0383271B1 (en) | 1996-01-24 |
Family
ID=12485711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP90102814A Expired - Lifetime EP0383271B1 (en) | 1989-02-16 | 1990-02-13 | Waveform shaping circuit and receiver using same |
Country Status (4)
Country | Link |
---|---|
US (1) | US5175748A (en) |
EP (1) | EP0383271B1 (en) |
JP (1) | JP2707461B2 (en) |
DE (1) | DE69024981T2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000030256A1 (en) * | 1998-11-13 | 2000-05-25 | University Of Surrey | Anti-jitter circuits |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04268809A (en) * | 1991-02-22 | 1992-09-24 | Mitsubishi Electric Corp | Method and device for extracting pulse signal |
US5359238A (en) * | 1992-08-04 | 1994-10-25 | Ford Motor Company | Analog to digital interface circuit with internal resistance compensation and integrity verification |
US5373388A (en) * | 1993-02-25 | 1994-12-13 | International Business Machines, Inc. | AC coupled fiber optic receiver with DC coupled characteristics |
US5585756A (en) * | 1995-02-27 | 1996-12-17 | University Of Chicago | Gated integrator with signal baseline subtraction |
US6538491B1 (en) * | 2000-09-26 | 2003-03-25 | Oki America, Inc. | Method and circuits for compensating the effect of switch resistance on settling time of high speed switched capacitor circuits |
US20030108110A1 (en) * | 2001-12-10 | 2003-06-12 | The Boeing Company | Systems and methods for reducing electromagnetic emissions in communications |
TWI260572B (en) | 2003-03-07 | 2006-08-21 | Hon Hai Prec Ind Co Ltd | Variable driving apparatus for light emitting diode |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61131912A (en) * | 1984-11-30 | 1986-06-19 | Toshiba Corp | Waveform shaping circuit |
GB2173378A (en) * | 1985-04-04 | 1986-10-08 | Rca Corp | A communications arrangement using an adaptive slicer |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE754157A (en) * | 1969-07-31 | 1971-02-01 | Siemens Ag | ASSEMBLY FOR COMPENSATION OF PARASITIC CONTINUOUS VOLTAGE COMPONENTS DURING DEMODULATION OF BINARY DATA SIGNALS |
US4339727A (en) * | 1978-03-07 | 1982-07-13 | Nippon Electric Co., Ltd. | Waveform converting circuit |
JPS58105623A (en) * | 1981-12-17 | 1983-06-23 | Nippon Denso Co Ltd | Waveform shaping circuit |
JPS58138121A (en) * | 1982-02-10 | 1983-08-16 | Nippon Denso Co Ltd | Waveform shaping circuit |
JPS5933370U (en) * | 1982-08-24 | 1984-03-01 | ミノルタ株式会社 | Binarization processing circuit |
JPS6183337U (en) * | 1984-11-05 | 1986-06-02 |
-
1989
- 1989-02-16 JP JP1037010A patent/JP2707461B2/en not_active Expired - Fee Related
-
1990
- 1990-02-08 US US07/476,895 patent/US5175748A/en not_active Expired - Fee Related
- 1990-02-13 DE DE69024981T patent/DE69024981T2/en not_active Expired - Fee Related
- 1990-02-13 EP EP90102814A patent/EP0383271B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61131912A (en) * | 1984-11-30 | 1986-06-19 | Toshiba Corp | Waveform shaping circuit |
GB2173378A (en) * | 1985-04-04 | 1986-10-08 | Rca Corp | A communications arrangement using an adaptive slicer |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 10, no. 325 (E-451)(2381) 6 November 1986 & JP-A-61 131 912 ( TOSHIBA ) 19 June 1986 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000030256A1 (en) * | 1998-11-13 | 2000-05-25 | University Of Surrey | Anti-jitter circuits |
US6791393B1 (en) | 1998-11-13 | 2004-09-14 | Toric Limited | Anti-jitter circuits |
Also Published As
Publication number | Publication date |
---|---|
EP0383271B1 (en) | 1996-01-24 |
DE69024981D1 (en) | 1996-03-07 |
JPH02215221A (en) | 1990-08-28 |
DE69024981T2 (en) | 1996-09-12 |
EP0383271A3 (en) | 1992-03-11 |
US5175748A (en) | 1992-12-29 |
JP2707461B2 (en) | 1998-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0109081A1 (en) | Bidirectional constant current driving circuit | |
EP0611100A1 (en) | Circuit for measuring the output power from an amplifier | |
EP0208530A2 (en) | Squelch detecting circuit with squelch start determining means | |
EP0383271B1 (en) | Waveform shaping circuit and receiver using same | |
GB2108791A (en) | A signal rectifier circuit with attack time changeable in response to input signal level | |
US4536666A (en) | Trigger coupling circuit for providing a plurality of coupling modes | |
US3214708A (en) | Frequency-type telemeter transmitter | |
US4652774A (en) | Rectangular wave-shaping circuit with varying threshold level | |
US4660002A (en) | High frequency oscillator using a diode for frequency switching and FM modulation | |
US3497621A (en) | Audio reproduction system with low frequency compensation | |
JPH054334Y2 (en) | ||
US4168472A (en) | Variable gain controller | |
US3165699A (en) | Automatic gain control system for suppressed carrier single sideband radio receivers | |
EP0531163A1 (en) | Audio amplifier | |
US4087762A (en) | Cable equalization resonant amplifier circuit | |
EP0202601A2 (en) | Optical pulse receiving circuit | |
JPS6113857A (en) | Telephone circuit | |
US3939426A (en) | Method and arrangement for furnishing an indication of multipath reception in an FM receiver | |
US5533057A (en) | High frequency signal detecting circuit | |
GB2034142A (en) | Muting circuit for an fm receiver | |
EP0398039A2 (en) | An attenuator circuit | |
JP2530229B2 (en) | Video signal clamp circuit | |
US2396507A (en) | Variable filtering and timing method and system | |
JPS6145632Y2 (en) | ||
JPS596676A (en) | Information signal insertion circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): BE DE FR NL |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): BE DE FR NL |
|
17P | Request for examination filed |
Effective date: 19920811 |
|
17Q | First examination report despatched |
Effective date: 19940722 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): BE DE FR NL |
|
REF | Corresponds to: |
Ref document number: 69024981 Country of ref document: DE Date of ref document: 19960307 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19990215 Year of fee payment: 10 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: BE Payment date: 19990219 Year of fee payment: 10 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 19990228 Year of fee payment: 10 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19990316 Year of fee payment: 10 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20000228 |
|
BERE | Be: lapsed |
Owner name: TOKO INC. Effective date: 20000228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20000901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20001031 |
|
NLV4 | Nl: lapsed or anulled due to non-payment of the annual fee |
Effective date: 20000901 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20001201 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |