EP0380964A2 - Verfahren zur Herstellung eines Halbleiterbauelements mit einem Kontaktteil - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements mit einem Kontaktteil Download PDF

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Publication number
EP0380964A2
EP0380964A2 EP90100909A EP90100909A EP0380964A2 EP 0380964 A2 EP0380964 A2 EP 0380964A2 EP 90100909 A EP90100909 A EP 90100909A EP 90100909 A EP90100909 A EP 90100909A EP 0380964 A2 EP0380964 A2 EP 0380964A2
Authority
EP
European Patent Office
Prior art keywords
wiring layer
layer
region
contact hole
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90100909A
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English (en)
French (fr)
Other versions
EP0380964A3 (de
EP0380964B1 (de
Inventor
Songsu Cho
Shinichi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
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Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP0380964A2 publication Critical patent/EP0380964A2/de
Publication of EP0380964A3 publication Critical patent/EP0380964A3/de
Application granted granted Critical
Publication of EP0380964B1 publication Critical patent/EP0380964B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor devices and a fabrication method thereof, for example, to static RAMs (Random Access Memories).
  • a field oxide film 2 for element separation is grown on a P type silicon substrate 1 by a well-known LOCOS (Local Oxidation of Silicon) method, and then a gate oxide film 3 is formed by thermal oxidation.
  • LOCOS Local Oxidation of Silicon
  • the gate oxide film 3 in a predetermined area is etched away as shown in Figure 5C (this forms a predetermined contact part 4).
  • a polysilicon layer 5 is deposited on the entire face including the contact part 4 by a well-known CVD (Chemical Vapor Deposition) method; and the polysilicon layer 5 is doped by, for example, phosphorus or the like to be N type; and then after a predetermined area is covered by a photoresist 40, a pattern is defined by, for example, a dry etching in order to leave only a predetermined polysilicon layer 5a (wiring layer) and 5b (gate electrode) as shown in Figure 5E. At this time, the P type silicon substrate 1 is also etched by patterning to form a recessed part 4a as shown in the figure.
  • CVD Chemical Vapor Deposition
  • the recessed part 4a in the figure is exaggerated to facilitate the understanding as said in the above.
  • 4b in the figure is a connecting region of the polysilicon layer 5a and the P type silicon substrate 1 (that is, an N+ type diffusion region which will be described later).
  • the gate oxide film 3 in a predetermined region is etched away except directly below the polysilicon layer 5b, using the above photoresist 40.
  • a predetermined area is selectively ion implanted with an N type impurity (for example As) 50 and is annealed (thermal treatment) to form N+ type diffusion region 6 and 7 (source region and drain region) as shown in Figure 5G; and furthermore, an interlevel insulating layer 8 (a phosphorus glass film such as, for example, PSG (Phosphosilicate Glass) or BPSG (Borophosphosilicate Glass)) is deposited as shown in Figure 5H.
  • N type impurity for example As
  • BPSG Biophosphosilicate Glass
  • a purpose of the invention is to provide semiconductor devices which are highly reliable and permit high degree of integration, and a fabrication method thereof.
  • This invention relates to such semiconductor devices comprising: a wiring layer with a predetermined pattern formed over a major surface of a semiconductor substrate through an insulating film, a diffusion layer formed under a contact hole formed in said insulating film in an adjacent region of the wiring layer, and a conductive layer deposited into said contact hole in a state of being connected to said wiring layer.
  • this invention provides a fabrication method of the above devices semiconductor devices comprising: a process of forming an insulating film over a major surface of semiconductor substrate, a process of forming a wiring layer over the insulating film, a process of patterning said wiring layer, a process of forming a contact hole across a part of the patterned wiring layer and the adjacent region thereof, a process of depositing a conductive layer into said contact hole so as to be connected to said wiring layer, and a process to form a diffusion layer under said contact hole.
  • Figures 1 - 3 show an embodiment in which the invention is applied to a static RAM.
  • N+ type source region 6 and an N+ type drain region 7 are formed in a predetermined pattern in a major surface of a P type silicon substrate 1; a gate electrode 5b is provided therebetween through a gate oxide film 3; and an N channel MOS transistor (for example, a transistor Q4 in Figure 2) is structured.
  • a wiring layer 5a of a predetermined pattern (for example, this wiring layer 5a is connected to a gate of an N channel MOS transistor Q1 in Figure 2) is formed on the gate oxide film 3 and a field oxide film 2 formed on the P type silicon substrate 1; an N+ type diffusion region 10 is formed by self-diffusion under a contact hole 9 formed in an adjacent region 12 of the wiring layer 5a; and this N+ type diffusion region 10 is connected to the source region 6.
  • a polysilicon layer 11 (conductive layer) is deposited into the contact hole 9, in a state of connection to the wiring layer 5a. 13 in the figure is a groove.
  • Figure 2 is an equivalent circuit diagram showing an example of the static MOS memory.
  • Q1 - Q6 in Figure 2 are N channel MOS transistors respectively.
  • a device of the invention includes the wiring layer 5a of the predetermined pattern formed through the gate oxide film 3, the N+ type diffusion layer formed under the contact hole 9 formed in the gate oxide film 3 in the adjacent region 12 of the wiring layer 5a, and the polysilicon layer 11 deposited into the contact hole 9 in a state of connection to the wiring layer 5a, so that the area of a region (the gate oxide film 3 under the wiring layer 5a and the adjacent region 12 of the wiring layer 5a in Figure 1), which corresponds to the contact part 4 (the connecting region 4b and a region of the recess part 4a) in a device by the conventional direct contact method as shown in Figure 5, can be reduced.
  • the connection characteristic may be sufficiently secured in this part. Therefore, the gate oxide film 3 under the wiring layer 5a may be smaller (however, this gate oxide film 3 may not entirely removed), so that the area of the above wiring layer 5a and the gate oxide film 3 may be reduced. Also, because the connection to the N+ type diffusion region (source region) 6 is made by the self-diffusion of the polysilicon layer 11 buried in the contact hole 9 (that is, by the N+ type diffusion region 10), there is little need to consider an excess area by, for example, alignment difference or the like, which is very advantageous to reduction of the device size. Thus, the defects in the direct contact method may be solved, and the high degree of integration of the device is made possible, taking advantage of its characteristic.
  • a field oxide film 2 (for example, 8000 ⁇ thick) is grown on a P type silicon substrate 1 by a well-known LOCOS method, and then a gate oxide film 3 (for example, 200 ⁇ thick) is formed on the silicon substrate 1 by thermal oxidation.
  • a polysilicon layer 5 (for example 5000 ⁇ thick) is deposited over the entire face by a well-known, for example, low pressure CVD method; then phosphorus, for example, is deposited by a CVD method at 950 degrees centigrade; and a thermal treatment is performed to dope the polysilicon layer 5 to be an N type.
  • a predetermined pattern is defined by, for example, dry etching to form a wiring layer 5a and a gate electrode 5b.
  • ion 60 of an N type impurity (for example As) is selectively implanted by a well-known ion implantation method, and an annealing is performed at 950 degrees centigrade to form the N+ type diffusion region 6 and 7 (source region and drain region).
  • an interlevel insulating layer 8 (for example, BPSG or the like) is deposited over the entire face by, for example, a normal pressure CVD method, and a steam treatment is performed at 850 degrees centigrade to planarize the interlevel insulating layer 8 and to increase the degree of oxidation (insulation).
  • a predetermined area is covered with a mask (for example, photoresist, not shown); then a groove 13 is formed by, for example, a dry etching of the interlevel insulating layer 8 in a predetermined area; and a contact hole 9 is formed by etching away the polysilicon layer 5a and removing the gate oxide film 3 by a predetermined dry etching as shown in Figure 3G.
  • a mask for example, photoresist, not shown
  • a polysilicon layer 11 is deposited by a well-known decreased pressure CVD method over the entire face which includes the contact hole 9 and the groove 13, and the polysilicon layer 11 is made low resistance by annealing at 900 degrees centigrade.
  • an N+ type diffusion region 10 is formed by self-diffusion under the contact hole 9 to be connected to the source region 6. This connects the polysilicon layer 11 and the wiring layer 5a.
  • one process may be omitted by performing the deposition of the polysilicon layer 11 and the anneal at the same step, which is advantageous.
  • a layer of SiO2 (for example, 3000 ⁇ thick) is again deposited by, for example, a well-known decreased pressure CVD method, and each normal wiring treatment is performed to complete the device.
  • the device of the embodiment and the fabrication method thereof do not require a mask process which removes the gate oxide film 3 in the predetermined region as in the conventional direct contact method shown in Figure 5B, the reliability of the device may be secured without contamination of the gate oxide film 3. Also, because a cleaning process for the contaminated gate oxide film 3 is not required as in conventional processes, it is an advantageous process without increased number of steps.
  • the P type silicon substrate 1 would not be exposed by alignment difference of the mask or the like as in the patterning of the polysilicon layer 5 shown in Figure 5E (because of the gate oxide film 3 as shown in Figure 3C), the P type silicon substrate 1 would not be also etched by a dry etching or the like (because the gate oxide film 3 works as a mask in patterning the polysilicon layer 5). Therefore, it is advantageous for the reliability of the device.
  • Figure 4 shows another embodiment of the invention, for instance, an embodiment structured as a diffusion resistance element.
  • the same reference numbers are used for the places corresponding to Figure 1.
  • the embodiment is basically structured quite similar to the one in Figure 1, but the difference is that it is structured to have, for example, an N+ type diffusion region 10 connected to an N+ type diffusion region 6 (the source region in the embodiment in Figure 1) in the region where the gate electrode 5b and the drain region 7 are formed in Figure 1 (the region in the right side of Figure 1). That is, the gate electrode as in the above embodiment of Figure 1 does not exist; the above structure is provided symmetrically with the N+ type diffusion region 6 in-between; the two diffusion regions 10 are each connected to the N+ type diffusion region 6; and the diffusion resistance is formed there.
  • an N+ type diffusion region 10 connected to an N+ type diffusion region 6 (the source region in the embodiment in Figure 1) in the region where the gate electrode 5b and the drain region 7 are formed in Figure 1 (the region in the right side of Figure 1). That is, the gate electrode as in the above embodiment of Figure 1 does not exist; the above structure is provided symmetrically with the N+ type diffusion region 6 in-between; the two diffusion regions 10 are each connected to the N+
  • 21 in the figure are electrodes to take out the wiring layer 5a; 22 are through holes; and 23 is a SiO2 layer.
  • the device of the embodiment has the similar structure as in the above embodiment of Figure 1, it has the same advantage as in the above embodiment, and it is also structurally convenient for electrical testing.
  • a direct contact structure of the invention may be easily checked by using the two diffusion regions 10 and the diffusion region 6 connected thereto shown in the figure as a diffusion resistance and measuring the electric characteristics thereof.
  • Resistive valve of 30 - 50 ohm per 1 contact hole may be actually freely controlled, and also very good contact characteristic may be obtained.
  • the conductive layer 11 deposited into the contact hole 9 in the above embodiments
  • other metal such as Al or the like may be deposited (in this case, metal or the like is deposited after the diffusion layer 10 is previously formed by an impurity diffusion by a conventional art).
  • the deposition of the conductive layer (polysilicon layer) 11 and the formation of the diffusion layer 10 by annealing may be performed at the same time.
  • the conductive layer 11 may be deposited after the formation of the diffusion layer 10.
  • the diffusion may be performed by an adequate optical excitation treatment such as laser anneal, lamp anneal, or the like.
  • the invention is applied to, for example, the N channel MOS transistor Q4 and Q1 within broken lines in Figure 2 in the above embodiments (that is, it is used for connecting the source of the transistor Q4 and the gate of the transistor Q1), it may also be applied for connecting the drain of the transistor Q5 and the gate of the transistor Q2, and connecting the source of the transistor Q4 and the drain of the transistor Q2, and so on, in the same figure.
  • the invention may be applied to appropriate places in other devices.
  • the conductivity types of the each above semiconductor region may be reversed, and the invention may be applied to the appropriate other than static RAMs, for example dynamic RAMs or the like.
  • the invention comprises: a wiring layer with a predetermined pattern formed over a major surface of a semiconductor substrate through an insulating film, a diffusion layer formed under a contact hole formed in said insulation film in an adjacent region of the wiring layer, and a conductive layer deposited into said contact hole in a state of being connected to said wiring layer, are occupied by said insulating film and wiring layer and also area of the adjacent region of said wiring layer may be reduced, which allows high degree of integration.
  • the contact hole is formed after patterning of the wiring layer over said insulating film, a process of etching said insulating film may be performed without contamination or the like of said insulating film.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
EP90100909A 1989-01-31 1990-01-17 Verfahren zur Herstellung eines Halbleiterbauelements mit einem Kontaktteil Expired - Lifetime EP0380964B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21807/89 1989-01-31
JP1021807A JPH02202054A (ja) 1989-01-31 1989-01-31 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
EP0380964A2 true EP0380964A2 (de) 1990-08-08
EP0380964A3 EP0380964A3 (de) 1991-03-13
EP0380964B1 EP0380964B1 (de) 1997-05-21

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EP90100909A Expired - Lifetime EP0380964B1 (de) 1989-01-31 1990-01-17 Verfahren zur Herstellung eines Halbleiterbauelements mit einem Kontaktteil

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EP (1) EP0380964B1 (de)
JP (1) JPH02202054A (de)
DE (1) DE69030743T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838049A (en) * 1992-09-11 1998-11-17 Sgs-Thomson Microelectronics, Ltd. Semiconductor device incorporating a contact and manufacture thereof
US6160294A (en) * 1993-09-20 2000-12-12 Fujitsu Limited Semiconductor device having an interconnection pattern for connecting among conductive portions of elements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0127020A2 (de) * 1983-05-31 1984-12-05 Kabushiki Kaisha Toshiba Verfahren zum Herstellen einer Mehrschicht-Halbleiteranordnung
EP0272051A2 (de) * 1986-12-17 1988-06-22 Advanced Micro Devices, Inc. Aneinandergefügte Kontaktstruktur mit vermindertem Flächenbedarf

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0127020A2 (de) * 1983-05-31 1984-12-05 Kabushiki Kaisha Toshiba Verfahren zum Herstellen einer Mehrschicht-Halbleiteranordnung
EP0272051A2 (de) * 1986-12-17 1988-06-22 Advanced Micro Devices, Inc. Aneinandergefügte Kontaktstruktur mit vermindertem Flächenbedarf

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"VLSI Technology", S.M.Sze, 1983, pages 169-171 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838049A (en) * 1992-09-11 1998-11-17 Sgs-Thomson Microelectronics, Ltd. Semiconductor device incorporating a contact and manufacture thereof
US6160294A (en) * 1993-09-20 2000-12-12 Fujitsu Limited Semiconductor device having an interconnection pattern for connecting among conductive portions of elements

Also Published As

Publication number Publication date
DE69030743D1 (de) 1997-06-26
JPH02202054A (ja) 1990-08-10
EP0380964A3 (de) 1991-03-13
EP0380964B1 (de) 1997-05-21
DE69030743T2 (de) 1997-11-13

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