EP0366530A3 - Josephson memory circuit - Google Patents

Josephson memory circuit Download PDF

Info

Publication number
EP0366530A3
EP0366530A3 EP19890402903 EP89402903A EP0366530A3 EP 0366530 A3 EP0366530 A3 EP 0366530A3 EP 19890402903 EP19890402903 EP 19890402903 EP 89402903 A EP89402903 A EP 89402903A EP 0366530 A3 EP0366530 A3 EP 0366530A3
Authority
EP
European Patent Office
Prior art keywords
memory circuit
josephson memory
josephson
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890402903
Other versions
EP0366530B1 (en
EP0366530A2 (en
Inventor
Seigo Kotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0366530A2 publication Critical patent/EP0366530A2/en
Publication of EP0366530A3 publication Critical patent/EP0366530A3/en
Application granted granted Critical
Publication of EP0366530B1 publication Critical patent/EP0366530B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/44—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using super-conductive elements, e.g. cryotron

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
EP89402903A 1988-10-24 1989-10-20 Josephson memory circuit Expired - Lifetime EP0366530B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63267886A JPH0834061B2 (en) 1988-10-24 1988-10-24 Josephson memory circuit
JP267886/88 1988-10-24

Publications (3)

Publication Number Publication Date
EP0366530A2 EP0366530A2 (en) 1990-05-02
EP0366530A3 true EP0366530A3 (en) 1990-09-26
EP0366530B1 EP0366530B1 (en) 1994-12-21

Family

ID=17450993

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89402903A Expired - Lifetime EP0366530B1 (en) 1988-10-24 1989-10-20 Josephson memory circuit

Country Status (4)

Country Link
US (1) US4974205A (en)
EP (1) EP0366530B1 (en)
JP (1) JPH0834061B2 (en)
DE (1) DE68920118T2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03276493A (en) * 1990-03-26 1991-12-06 Agency Of Ind Science & Technol Josephson memory circuit
US5024993A (en) * 1990-05-02 1991-06-18 Microelectronics & Computer Technology Corporation Superconducting-semiconducting circuits, devices and systems
US5315180A (en) * 1992-02-13 1994-05-24 Fujitsu Limited Synchronizing interface circuit between semiconductor element circuit and a Josephson junction element circuit
US5412788A (en) * 1992-04-16 1995-05-02 Digital Equipment Corporation Memory bank management and arbitration in multiprocessor computer system
US5365476A (en) * 1993-02-26 1994-11-15 Digital Equipment Corporation Three-port Josephson memory cell for superconducting digital computer
US7615385B2 (en) 2006-09-20 2009-11-10 Hypres, Inc Double-masking technique for increasing fabrication yield in superconducting electronics
TWI347607B (en) * 2007-11-08 2011-08-21 Ind Tech Res Inst Writing system and method for a phase change memory
TWI402845B (en) 2008-12-30 2013-07-21 Higgs Opl Capital Llc Verification circuits and methods for phase change memory
TWI412124B (en) 2008-12-31 2013-10-11 Higgs Opl Capital Llc Phase change memory
US8571614B1 (en) 2009-10-12 2013-10-29 Hypres, Inc. Low-power biasing networks for superconducting integrated circuits
US10222416B1 (en) 2015-04-14 2019-03-05 Hypres, Inc. System and method for array diagnostics in superconducting integrated circuit
US9613699B1 (en) 2016-04-22 2017-04-04 Microsoft Technology Licensing, Llc Memory system with a content addressable superconducting memory
US9812192B1 (en) * 2016-09-02 2017-11-07 Northrop Grumman Systems Corporation Superconducting gate memory circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2462824A1 (en) * 1979-07-25 1981-02-13 Nippon Telegraph & Telephone LOGIC CIRCUIT WITH ASYMMETRIC QUANTA INTERFEROMETER CIRCUITS

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182533A (en) * 1984-09-28 1986-04-26 Heihachiro Hirai Inverter
JPH0767077B2 (en) * 1986-10-14 1995-07-19 富士通株式会社 Josephson logic unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2462824A1 (en) * 1979-07-25 1981-02-13 Nippon Telegraph & Telephone LOGIC CIRCUIT WITH ASYMMETRIC QUANTA INTERFEROMETER CIRCUITS

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 27, no. 2, July 1984, pages 1156-1158, New York, US; C.C. CHI et al.: "Superconducting RAM using coupled squids" *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 23, no. 4, August 1988, pages 923-932, IEEE, New York, US; Y. WADA et al.: "AC- and DC-powered subnanosecond 1-kbit Josephson cache memory design" *
PATENT ABSTRACTS OF JAPAN, vol. 10, no. 255 (E-433)[2311], 2nd September 1986; & JP-A-61 082 533 (HEIHACHIRO HIRAI) 26-04-1986 *

Also Published As

Publication number Publication date
EP0366530B1 (en) 1994-12-21
EP0366530A2 (en) 1990-05-02
DE68920118D1 (en) 1995-02-02
JPH0834061B2 (en) 1996-03-29
DE68920118T2 (en) 1995-05-11
JPH02116090A (en) 1990-04-27
US4974205A (en) 1990-11-27

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