EP0359232A3 - Computer system and method for setting recovery time - Google Patents

Computer system and method for setting recovery time Download PDF

Info

Publication number
EP0359232A3
EP0359232A3 EP19890116955 EP89116955A EP0359232A3 EP 0359232 A3 EP0359232 A3 EP 0359232A3 EP 19890116955 EP19890116955 EP 19890116955 EP 89116955 A EP89116955 A EP 89116955A EP 0359232 A3 EP0359232 A3 EP 0359232A3
Authority
EP
European Patent Office
Prior art keywords
ready
bus cycle
cycle control
notice
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890116955
Other languages
German (de)
French (fr)
Other versions
EP0359232A2 (en
Inventor
Nobutaka Intellectual Property Division Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0359232A2 publication Critical patent/EP0359232A2/en
Publication of EP0359232A3 publication Critical patent/EP0359232A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)

Abstract

In a computer system, a CPU bus cycle control sec­ tion (211) receives a bus cycle request (BC-REQ) to gen­ erate a system bus request (SBC-REQ) and feeds back a ready notice (READY-a) to the CPU (11). A system bus cycle control section (221) performs the bus cycle control in response to the system bus cycle request (SBC-REQ) from the control section (211) and generates a ready notice (READY-b) to the CPU bus cycle control sec­ tion (221). The computer system includes a timer (213) for delaying the ready notice (READY-b), a selector (214) for selecting one of the ready notice (D'READY) delayed by the timer (213) and the ready notice (READy-b) from the system bus cycle control section (221) and supplies the selected ready notice to the CPU bus cycle control section (211) and a register (212) for holding a recovery state bit FRDY and recovery time data.
EP19890116955 1988-09-13 1989-09-13 Computer system and method for setting recovery time Withdrawn EP0359232A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP229014/88 1988-09-13
JP63229014A JPH0276057A (en) 1988-09-13 1988-09-13 I/o recovery system

Publications (2)

Publication Number Publication Date
EP0359232A2 EP0359232A2 (en) 1990-03-21
EP0359232A3 true EP0359232A3 (en) 1991-07-24

Family

ID=16885406

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890116955 Withdrawn EP0359232A3 (en) 1988-09-13 1989-09-13 Computer system and method for setting recovery time

Country Status (4)

Country Link
US (1) US5163135A (en)
EP (1) EP0359232A3 (en)
JP (1) JPH0276057A (en)
KR (1) KR930003443B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3018404B2 (en) * 1990-06-21 2000-03-13 日本電気株式会社 Microprocessor
DE4237259A1 (en) * 1992-11-04 1994-05-05 Siemens Ag Arrangement for data transmission with a parallel bus system
US5537664A (en) * 1993-06-30 1996-07-16 Intel Corporation Methods and apparatus for generating I/O recovery delays in a computer system
JP4698869B2 (en) * 2001-03-30 2011-06-08 Ｄｉｃ株式会社 Composite structure and method for producing the same
WO2016090267A1 (en) 2014-12-04 2016-06-09 The Regents Of The University Of Michigan Energy conscious warm-up of lithium-ion cells from sub-zero temperatures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0082683A2 (en) * 1981-12-17 1983-06-29 Honeywell Bull Inc. Computer memory system
EP0114523A2 (en) * 1982-12-27 1984-08-01 Honeywell Bull Inc. Distributed priority logic network

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342083A (en) * 1980-02-05 1982-07-27 The Bendix Corporation Communication system for a multiple-computer system
GB2075310A (en) * 1980-04-30 1981-11-11 Hewlett Packard Ltd Bus extender circuitry for data transmission
US4661905A (en) * 1983-09-22 1987-04-28 Digital Equipment Corporation Bus-control mechanism
JPS6243764A (en) * 1985-08-21 1987-02-25 Nec Corp Bus state control circuit
US5065313A (en) * 1989-03-30 1991-11-12 Dell Usa Corporation Digital computer system having circuit for regulation of I/O command recovery time

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0082683A2 (en) * 1981-12-17 1983-06-29 Honeywell Bull Inc. Computer memory system
EP0114523A2 (en) * 1982-12-27 1984-08-01 Honeywell Bull Inc. Distributed priority logic network

Also Published As

Publication number Publication date
KR900005306A (en) 1990-04-14
US5163135A (en) 1992-11-10
KR930003443B1 (en) 1993-04-29
EP0359232A2 (en) 1990-03-21
JPH0276057A (en) 1990-03-15

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