EP0354860A1 - Highly integrated EPROM device laid out in a grid and having an altered coupling factor and a redundancy capability - Google Patents

Abstract

The present invention relates to an electrically programmable nonvolatile memory composed of a grid of word lines (LM2) extending along a first direction referred to as a row direction, and of bit lines (LB2 to LB4) extending along a second direction referred to as a column direction. A conductive zone (25) formed by a second level of polycrystalline silicon contacts and covers the floating gate (23) of each transistor, projecting in the direction of the rows. The conductive zone (25) in each transistor is opposite the word line connected to the transistor, this word line corresponding, at the site of the conductive zones, to the control gate (28). <IMAGE>

Description

The present invention relates to semiconductor memories, and more particularly to electrically programmable non-volatile memories, more commonly called EPROM memories; the manufacture of floating gate memories is more specifically concerned.

To obtain memories with large storage capacity, for example memories capable of storing up to 16 megabits, the size of each of the cells constituting the memory must be reduced as much as possible.

However, it is obviously limited by physical considerations, and in particular by the fineness of the patterns which the photolithography stages allow; one is also limited by the parasitic electrical parameters which are due to the manufacturing process and which disturb the functioning of the memory.

A conventional memory elementary memory point is shown in FIGS. 1A and 1B, FIG. 1A being a representation in the form of an electrical diagram and FIG. 1B being a schematic sectional view of the elementary memory point.

FIG. 1A represents a transistor T of a floating gate memory point. This transistor has a floating gate 1 and a control gate 2, as well as two regions semiconductors of a first type of conductivity (source 3 and drain 4) separated by a channel region of an opposite type of conductivity covered by the floating gate 1 and the control gate 2.

The control gate 2 is connected to a word line LM. The drain 4 is connected to a bit line LB.

To program, or write, such a memory point, its floating gate 1 is loaded by injection of hot carriers, by applying to the control gate 2, while the transistor conducts a current between its source regions 3, set to mass, and of drain 4, a sufficiently high potential for the charge carriers (electrons) to be attracted and trapped in the floating grid. This writing operation has the effect of increasing the conduction threshold of the transistor which, once programmed, will conduct the current only for potential values applied to the control gate higher than in the absence of programming.

When reading the information contained in a memory point, a voltage is applied to the control gate of the transistor of this memory point that is both greater than the conduction trigger threshold voltage in the non-state programmed and lower than the conduction trigger threshold voltage in the programmed state. If the transistor conducts current when a suitable potential difference is applied between the source and the drain, the memory point is in the non-programmed state. If the transistor does not conduct current, the memory point is in the programmed state.

The potential applied to the control grid when programming the memory point, or Vpp programming potential, is for example 15 volts. The drain potential Vcc is then for example 10 volts, and the source potential Vss is for example zero volts, or ground.

The potential applied to the control grid when reading the memory point is for example 5 volts. The drain potential Vcc is then for example 1.5 volts, and the source potential Vss is for example zero volts, or ground.

In FIG. 1B, which represents a sectional view of a memory point implanted on a silicon wafer, there is the floating gate 1 and the control gate 2 of the transistor. We also see the source 3 and the drain 4, which are two semiconductor regions of a first type of conductivity, for example N⁺, separated by a channel region 7 of an opposite type of conductivity, for example P⁻.

The floating gate 1 of the transistor is produced by a first level of polycrystalline silicon (poly 1). It is separated from the substrate by a layer of silicon dioxide 5, also called the gate oxide layer.

Above the floating grid 1, there is a layer of silicon dioxide 6. This layer is located between the floating grid 1 and the control grid 2, the latter being produced by a second level of polycrystalline silicon (poly 2) . The silicon dioxide layer 6 thus also bears the name of the interpoly oxide layer.

In memory, the control gate 2 of the transistor is connected to a word line LM. Source 3 is connected to ground, and drain 4 to a bit line LB.

With the classic memory architecture and the associated programming mode, it is imperative that the drain of a transistor is electrically isolated, by thick silicon oxide (compared to the gate oxide of the transistors), from the drain adjacent transistors of the same word line, failing which one could not program a particular memory point without programming or deprogramming the others at the same time.

However, this thick oxide which isolates two adjacent points takes up a lot of space, especially when it is produced by the technique known as localized oxidation.

Attempts have been made to replace localized oxidation with insulation by trenches filled with oxide, in order to reduce the overall bulk of the cell, but this technology is not industrially developed.

To reduce the size of the memory points and thus increase the storage capacity of the memory, French patent application 86/12938 has proposed structures in which the thick oxide zones and the multiple contacts to the drains or sources are deleted. These structures are called checkerboard structures.

FIG. 2 represents a top view of nine adjacent memory points in such a checkerboard-type structure.

The various floating-gate transistors constituting the array of memory points are designated by Tij, where i is a row index and j a column index.

Thus, the transistors T11 to T13 are those of the first row, the transistors T21 to T23 are those of the second row, and the transistors T31 to T33 are those of the third row. Similarly, the transistors T11 to T31 are those of the first column, the transistors T12 to T32 are those of the second column and finally the transistors T13 to T33 are those of the third column.

The control gates of the transistors of the same row are all connected to the same word line, LM1 to LM3 for the rows 1 to 3, respectively.

The word lines are conductors (in practice in polycrystalline silicon) extending in a horizontal direction (direction of the rows).

Each transistor shares with the two adjacent transistors on the same row a region produced by a diffusion of the first type of conductivity which extends along a column to form a bit line, which is designated by LB1, LB2, LB3 and LB4 for columns 1 to 4, respectively, and by LBj generally speaking. These lines LBj can thus make, at the location of the transistors, either the source office or the drain office.

FIG. 3 represents a sectional view along the axis YY ′ of FIG. 2.

The devices are located on a substrate 10. The floating gates 11 of the transistors are produced by a first level of polycrystalline silicon (poly 1) and located between two bit lines. The control gates 12 of the transistors are formed by the parts of the word line LM2 located at the location of the transistors. The word lines, and thus the control grids of the transistors, are produced by a second level of polycrystalline silicon (poly 2).

A gate oxide layer 13 is located under the floating gate of the transistors.

An isolation zone 14 is located between the floating gates of the transistors. Conventionally, a planarization process is used so that the upper surfaces of this isolation zone 14 and of the first level of polycrystalline silicon are at the same level. This isolation zone 14 is for example made up of orthosilicate tetraethyl or TEOS.

An interpoly oxide layer 15 covers the floating gates 11 and the isolation zones 14.

The programming mode of this architecture is particular. It is set out in the aforementioned French patent application. This is due to the fact that each memory point shares with each of the two adjacent memory points of the same row a region which can be either source region or drain region.

FIG. 4 represents a diagram of the capacities existing at the location of a transistor, for example the transistor T22.

If a voltage V _M is applied to the word line LM2, the voltage V _F is obtained on the floating gate 11 by calculating the coupling factor γ which connects these two voltages by the relation:
V _F = γ V _M
and which is defined by the ratio between the capacity at the interpoly oxide layer and the sum of all the capacities present.

If we consider FIG. 4, we observe the capacitance at the level of the interpoly oxide layer 15 denoted C _OI and situated between the word line LM2 and the floating gate 11. We also have a capacitance C _OG at the level of the gate oxide layer 13 located between the floating gate 11 and the substrate 10.

The coupling factor γ is written:
γ = C _OI / (C _OI + C _OG )

One can calculate a numerical value representative of the coupling factor by using usual values for the dimensions of the elements concerned:
- length of the floating grid in the direction of the rows: 0.5 micrometer;
- thickness of the interpoly oxide layer: 20 nm;
- thickness of the gate oxide layer: 20 nm;

The numerical value of the coupling factor is then equal to the ratio between the quantities 0.5 / 20 and 0.5 / 20 + 0.5 / 20, ie only 0.5.

The present invention provides a new structure which improves the coupling factor. In addition, this new structure does not have a thick oxide zone, which allows the memory to occupy a reduced bulk.

According to the invention, the memory whose memory points consist of floating gate MOS transistors is composed of a network of word lines extending in a first direction called row, and bit lines extending along a second direction called column. In this memory, each transistor comprises two regions, each serving either to source or drain, each of the two regions is constituted by a diffusion of a first type of conductivity which is extended along a column to form a bit line in a substrate of the second type of conductivity, the floating gate of each transistor is produced by a first level of polycrystalline silicon, and an isolation zone is located between each pair of floating grids of the same row. A conductive zone produced by a second level of polycrystalline silicon contacts and covers, in the direction of the rows, the floating gate of each transistor by projecting in the direction of the rows. The conductive areas are covered on their upper surface with an interpoly oxide layer, and they are covered at their two ends, in the direction of the rows, by a corner oxide area. The word lines, of dimensions along the direction of the columns substantially equal to those of the floating gate of the transistors and produced by a third level of polycrystalline silicon, cover the layers of interpoly oxide, the corner oxide zones and the parts isolation zones not covered by the corner oxide zones. The conductive area in each transistor is opposite the word line connected to the transistor, this word line corresponding, at the location of the conductive areas, to the control gate.

• les figures 1A et 1B, déjà décrites, représentent un point-mémoire élémentaire de mémoire classique, la figure 1A étant une représentation sous forme de schéma électrique et la figure 1B étant une vue en coupe schématique du point-mémoire élémentaire ;
• la figure 2, déjà décrite, représente une vue de dessus de l'implantation de neuf points-mémoire adjacents sur une tranche de silicium dans une architecture classique de type damier ;
• la figure 3, déjà décrite, représente une vue en coupe suivant l'axe YY′ de la figure 2 ;
• la figure 4, déjà décrite, représente un schéma des ca­pacités existant à l'emplacement d'un transistor dans une archi­tecture telle que celle de la figure 2 ;
• la figure 5 représente une vue de dessus d'une structure selon la présente invention ;
• la figure 6 représente une vue en coupe suivant l'axe YY′ de la figure 5 ;
• la figure 7 représente une vue en coupe suivant l'axe ZZ′ de la figure 5 ;
• la figure 8 représente un schéma des capacités existant à l'emplacement d'un point-mémoire de la structure de la figure 5 ; et
• la figure 9 représente selon une coupe analogue à celle de la figure 6 une variante de réalisation de la présente inven­tion.

These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of a particular embodiment made in relation to the appended figures among which:

• FIGS. 1A and 1B, already described, represent an elementary memory point of conventional memory, FIG. 1A being a representation in the form of an electrical diagram and FIG. 1B being a schematic sectional view of the elementary memory point;
• FIG. 2, already described, represents a top view of the implantation of nine adjacent memory points on a silicon wafer in a conventional architecture of the checkerboard type;
• Figure 3, already described, shows a sectional view along the axis YY ′ of Figure 2;
• FIG. 4, already described, represents a diagram of the capacities existing at the location of a transistor in an architecture such as that of FIG. 2;
• FIG. 5 represents a top view of a structure according to the present invention;
• 6 shows a sectional view along the axis YY 'of Figure 5;
• 7 shows a sectional view along the axis ZZ 'of Figure 5;
• FIG. 8 represents a diagram of the capacities existing at the location of a memory point of the structure of FIG. 5; and
• Figure 9 shows a section similar to that of Figure 6 an alternative embodiment of the present invention.

In general, as is conventional in the representation of integrated circuits, it will be noted that the various figures are not represented to scale, neither from one figure to another, nor inside the same figure, and in particular that the thicknesses of the layers are drawn arbitrarily in order to facilitate the reading of the figures.

FIG. 5 represents a top view of an embodiment of the structure according to the present invention. As in the case of FIG. 2, the transistors are arranged in an array of rows and columns.

The control gates of the transistors of row i are still all connected to word lines LMi.

The bit lines LBj are located between each pair of columns of transistors and can act, at the location of the transistors, either as source office or as drain office.

A conductive area 25 is in contact with the floating gate of each transistor of the memory.

6 shows a sectional view along the axis YY 'of Figure 5. We see in this figure two transistors designated by T22 and T23.

The devices are located on a substrate 20. Each of the two transistors T22 and T23 comprises two regions 21 formed by a diffusion of a first type of conductivity which extends along a column to form a bit line. These bit lines are designated by LB2, LB3 and LB4 in the figure.

The floating gates 23 of the transistors are produced by a first level of polycrystalline silicon (poly 1). A gate oxide layer 24 is located under the floating gates of the transistors.

A conductive zone 25 contacts and covers in the direction of the rows the floating gate of each of the two transistors T22 and T23. It is produced by a second level of polycrystalline silicon (poly 2).

This conductive zone 25 is covered on its upper surface by an interpoly oxide layer 26, and it is covered at its ends, in the direction of the rows, by an oxide zone 27 which is called the corner oxide zone.

An isolation zone 29 is located between the floating gates of the transistors. As in the case of the structure shown in FIG. 3, a planarization process is used so that the upper surfaces of this zone 29 and of the first level of polycrystalline silicon are at the same level. This area 29 is for example made up of TEOS.

The word line LM2 covers the whole.

The interpoly oxide layer 26 and the corner oxide zones 27 make it possible to isolate the conductive zone 25 from the word line LM2. The word line LM2 acts as a control grid 28 at the location of the conductive zones 25.

7 shows a sectional view along the axis ZZ 'of Figure 5. This figure shows transistors designated by T13, T23 and T33. The transistors each have a floating gate 23 located above the gate oxide layer 24. The conductive zone 25 is placed above the floating gates 23 and below the interpoly oxide layer 26. It is observed also the word lines LM1, LM2 and LM3, located above the interpoly oxide layers 26, which act as a control grid 28 at the location of the conductive areas.

FIG. 8 represents a diagram of the capacities existing at the location of a memory point of the structure according to the present invention, for example the memory point comprising the transistor T22. We observe in this figure the capacity at the level of the interpoly oxide layer 26 denoted C _OI1 and located between the word line LM2 and the conductive area 25. There is also a capacity C _OG1 at the level of the oxide layer grid 24 located between the floating grids 23 and the substrate 20. There is also, since the conductive zone 25 extends beyond the floating grid of the transistors in the direction of the rows, a capacity C _OD1 and a capacity C _OD2 at the level of the zone d 'TEOS type isolation, each of these two capacities corresponding to overflow on one side.

The coupling factor γ is written:
γ = C _OI1 / (C _OI1 + C _OD1 + C _OG1 + C _OD2 )

A numerical value representative of the coupling factor can be calculated using the following usual values:
- length of the floating grid in the direction of the rows: 0.5 micrometer;
- total length of overflow from the conductive zone 25 (the overflows on each side of the floating grid are thus grouped together): 0.2 micrometer;
- thickness of the interpoly oxide layer: 20 nm;
- thickness of the gate oxide layer: 20 nm;
- thickness of the TEOS type isolation zone: 200 nm.

The numerical value of the coupling factor is then equal to the ratio between the quantities (0.5 + 0.2) / 20 and (0.5 + 0.2) / 20 + 0.5 / 20 + 0.2 / ( 200 + 20).

The coupling factor is then equal to 0.58.

The structure according to the invention thus makes it possible to improve the coupling factor.

This structure also has good planarization conditions due to the absence of a thick oxide zone.

However, in such a structure, the programming of a memory point must take account of the adjacent memory points. This makes the addressing system complex.

Figure 9 shows, in a section similar to that of Figure 6, and with the same reference numerals whenever possible, an alternative embodiment of the invention which allows the use of a conventional addressing section.

In this variant, T1, T2 denotes a pair of adjacent transistors which will be connected by the addressing system to constitute a single memory point PM. The memory then has a so-called half-checkerboard structure.

Column broadcasts are then specialized. The transistors T1 and T2 share a common drain region 40. Each of the two transistors T1 and T2 comprises a source region 41, 42 shared with a transistor of an adjacent memory point of the same row. The floating gates 23, 25 of the transistors T1, T2 are addressed simultaneously by the memory addressing system.

The half-checkerboard structure has redundancy. Indeed, if the floating gate of one of the transistors loses its charge, we can still read the charge present on the floating gate of the other.

The structure observed in FIG. 9 has other advantages in addition to the high security resulting from redundancy.

In fact, if we adopt the configuration shown in FIG. 9 with an offset (1) between the polycrystalline silicon portions of the second level (poly 2) 25 and the floating gates proper 23, we can form source regions 41 , 42 wider than the drain regions 40. An increase in the width of the source regions results in a decrease in the resistance, which has the effect of improving the programming characteristics.

Finally, a conductive line (not shown in the figures), for example made of aluminum, is conventionally located above each bit line. In the case of the structure shown in Figure 6, such a conductive line is located between each pair of columns of transistors. In the case of the structure shown in Figure 9, two columns of transistors separate two adjacent conductive lines. The development of the conductive lines will thus be easier to carry out in the second case.

Claims (3)

1. Memory whose memory points consist of floating gate MOS transistors, composed of a network of word lines (LM1 to LM3) extending in a first direction called row, and bit lines (LB1 to LB5) extending in a second direction known as a column, in which:
each transistor comprises two regions (21) each acting either as a source or as a drain,
each of the two regions (21) consists of a diffusion of a first type of conductivity which is extended along a column to form a bit line in a substrate (20) of the second type of conductivity,
the floating gate (23) of each transistor is produced by a first level of polycrystalline silicon,
an isolation zone (29) is located between each pair of floating grids in the same row,
characterized in that:
a conductive area (25) produced by a second level of polycrystalline silicon contacts and covers, in the direction of the rows, the floating gate of each transistor by projecting in the direction of the rows,
the conductive zones are covered on their upper surface with an interpoly oxide layer (26), and they are covered at their two ends, in the direction of the rows, by a corner oxide zone (27),
the word lines, of dimensions along the direction of the columns substantially equal to those of the floating gate of the transistors and produced by a third level of polycrystalline silicon, cover the layers of interpoly oxide, the corner oxide zones and the parts isolation zones not covered by the corner oxide zones, and
the conductive area in each transistor is opposite the word line connected to the transistor, this word line corresponding, at the location of the conductive areas, to the control gate (28). 2. Memory according to claim 1, characterized in that it is connected to a logic addressing part of memory of the half-checkerboard type. 3. Memory according to one of claims 1 or 2, characterized in that the diffusions constituting the source regions at the location of the transistors have a greater width than the width of the diffusions constituting the drain regions at the location of transistors.

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