FR2987700A1 - NON-VOLATILE MEMORY COMPRISING MINI FLOATING POTENTIAL HOUSINGS - Google Patents

Abstract

The invention relates to an integrated circuit (IC) comprising a non-volatile memory on a semiconductor substrate (WF, PW). The integrated circuit comprises a doped isolation layer (NISO) implanted in the depth of the substrate, isolated conducting trenches (SGCi, i + i) reaching the insulating layer (NISO), forming gates (SGC) of transistors of selection (ST41, ST42) of memory cells (C41, C42), isolation trenches (STI) perpendicular to the conducting trenches (SGCi, i + i), and reaching the insulating layer (NISO), and conducting lines (CGi, CGi + i) parallel to the conducting trenches (SGCi, i + i), extending on the substrate (PW) and forming control gates (CG) of charge accumulation transistors (FGT41, FGT42) of cells memory (C41, C42). the isolation trenches and the insulated conducting trenches delimit in the substrate a plurality of mini caissons (MPW1, MPW2, MPW3) electrically isolated from each other, each having a floating electrical potential, and each comprising two memory cells.

Description

The present invention relates to nonvolatile memories integrated circuit on a semiconductor chip. The present invention more particularly relates to memories comprising memory cells programmed and erased by the channel, called "UCP" (Uniform Channel Program). The present invention more particularly relates to the UCP memory cells with two transistors, comprising a selection transistor and a charge storage transistor such as a floating gate transistor.

FIG. 1 is a schematic sectional view of two memory cells C11, C12 of the UCP type, made on a P type PW substrate. Each memory cell C11, C12 comprises a floating gate transistor FGT11, FGT12 and a selection transistor ST11. , ST12. Each floating gate transistor comprises a drain region n1 (D), a source region n2 (S), a floating gate FG, a control gate CG, and a channel region CH1 extending under the floating gate FG between the drain regions n1 and source n2. Each selection transistor ST11, ST12 comprises a drain region n2 (D) common to the source region n2 of the corresponding floating gate transistor FGT11, FGT12, a source region n3 (S), a gate SG, and a region of channel CH2 extending under the gate SG between the drain regions n2 and source n3. The two transistors ST11, ST12 share the same source region n3. Regions n1, n2, n3 are generally formed by N-doping of the PW substrate. The substrate is generally a P-type well formed in a semiconductor wafer plate WF. The PW box is isolated from the rest of the wafer WF by an N-doped N-insulation layer which surrounds the entire box. The grids FG, SG are generally made of polycrystalline silicon of level 1, or "polyl", and are formed on the substrate PW by means of oxide layers D1, D2, the layer D1 being a tunnel oxide layer while that the layer D2 is a gate oxide layer. The control gate CG is generally made of polycrystalline silicon of level 2, or "poly2", and is formed on the floating gate FG via an oxide layer D3. The two memory cells are covered by a dielectric insulating material D0, which may also be SiO2 oxide. The drain regions n1 of the transistors FGT11, FGT12 are connected to the same bit line BL via a contact C1 passing through the insulator DO to reach an intermediate conductor Ti made in a first level of metal, or "metal and a conducting bushing V1 ("via") passing through the insulator DO to connect the conductor Ti to the bit line BL, made in a second metal level, or "metal2". The source region n3 common to the two transistors ST11, ST12 is connected to a source line SL via a contact C2 crossing the insulator DO, the source line SL being for example made in the first level of metal . The table REF1 in Appendix 1 describes in relation to FIG. 2 the voltages applied to the memory cells C11, C12, FIG. 2 representing their equivalent electrical diagram. The table RD1 in Appendix 1 describes in relation to FIG. 3 voltage values applied to the memory cells during the reading of the memory cell C11. The column "Ref." describes the reference assigned to each voltage value and the column "Ex." describes examples of voltage values. "GND" is the mass potential, namely the potential of the WF wafer, usually OV.

Thus, during the reading of the cell C11, the selection transistor ST12 receives the blocking voltage Voff and is not conducting. A current (represented by arrows in FIG. 3) flows in the channel region CH1 of the transistor FGT11 and in the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11 which is itself representative of a programmed or erased state of the transistor, which depends on a quantity of electric charges stored in its floating gate. This current is detected (sensed) by a sense amplifier (not shown in the figure), which provides a binary data stored by the cell C11.

The selection transistor ST12 being blocked by the voltage Voff, the value of the so-called "non-reading" voltage Vnread applied to the floating gate transistor FGT12 is small since this transistor is isolated from the source region n3 by the transistor ST12. . In the table RD1, this voltage is chosen equal to the voltage VB1 of the substrate PW, here the potential GND.

The cells C11, C12 have the advantage of being able to be programmed or erased by applying a determined pair of voltages to the substrate PW and to the control gate CG of their transistor FGT11, FGT12, this programming and erasing mode being called " programming and erasing through the channel ". To fix the ideas, the table ER1 in Appendix 1 describes voltage values applied to the memory cells during the deletion of the cell C11. Table PG1 in Appendix 1 describes voltage values applied to the memory cells during the programming of cell C11. "HZ" refers to a floating potential (open circuit).

The transfer of charges from the substrate PW to the floating gate FG (programming) or from the floating gate to the substrate (erasure) is carried out without passing through the selection transistor ST11, as well as the application of the high potential difference (here 15V) allowing this charge transfer. As a result, the steps of programming, erasing, and reading are conducted with low value voltages, exploiting the potential difference between the substrate and the control gate of the floating gate transistors. Thus, the selection transistors ST11, ST12 do not undergo high voltages, which makes it possible to provide memory cells C11, C12 which are simple in design and compact in terms of the semiconductor surface.

Despite the advantages offered by such memory cells UCP, it may be desired to provide a means for further reducing their size, to reduce the size of a memory plane comprising a plurality of such memory cells. It might also be desirable to provide a compact memory structure.

Embodiments of the invention relate to a method of manufacturing on a semiconductor substrate an integrated circuit comprising a non-volatile memory comprising memory cells each comprising a charge-storage transistor and a selection transistor, which method comprises steps of: implanting in the depth of the substrate a doped isolation layer, producing in the substrate isolated conducting trenches reaching the insulation layer and each delimited by an insulating layer, to form grids of selection transistors, realize in the substrate of the isolation trenches perpendicular to the conducting trenches, and reaching the insulating layer, producing conductive lines parallel to the conducting trenches on the substrate, to form control gates for charge accumulation transistors, and to implant doped regions; on each side of the trenches these insulators and conductive lines parallel to the conductive trenches, for forming drain and charge accumulation transistor source regions and memory cell selection transistors, the insulating trenches and isolated conducting trenches delineating in the substrate a plurality of mini boxes electrically insulated from each other, each having a floating electrical potential, and each comprising two memory cells. According to one embodiment, the isolation trenches are designed to cut the conducting trenches into a plurality of sections. each forming a common vertical grid of two selection transistors of two memory cells belonging to different mini boxes. According to one embodiment, the isolation trenches are designed to completely cut the conductive trenches in a plurality of sections each forming a common vertical grid of two memory cells, and comprising a step of producing, in a metal layer, a word line that electrically connects the different sections. According to one embodiment, the conductive trenches are designed to cut the isolation trenches into a plurality of sections. Embodiments of the invention also include an integrated circuit comprising a nonvolatile memory on a semiconductor substrate, and comprising a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the insulation layer and each delimited by an insulating layer, forming grids of memory cell selection transistors, isolation trenches perpendicular to the conducting trenches, and reaching the insulating layer, conductive lines parallel to the conducting trenches, extending over the substrate and forming control gates of memory cell charge accumulating transistors, and doped regions on each side of the isolated conductive trenches and conductive lines parallel to the conducting trenches, forming drain and transistor regions of the storage accumulator transistor. charge and selection transistors of cel memory modules, isolating trenches and isolated conductive trenches defining in the substrate a plurality of mini boxes electrically insulated from each other, each having a floating electrical potential, and each comprising two memory cells. According to one embodiment, the isolation trenches section the conductive trenches in a plurality of sections each forming a common vertical grid of two selection transistors of two memory cells belonging to different mini boxes.

According to one embodiment, the isolation trenches completely cut the conducting trenches in a plurality of sections each forming a common vertical grid of two memory cells, and comprising a metal word line extending above the substrate, which electrically connects the different sections. According to one embodiment, the conductive trenches cut the isolation trenches in a plurality of sections.

According to one embodiment, the isolation layer forms a source line of the memory cell selection transistors. According to one embodiment, the charge storage transistors are floating gate transistors.

Embodiments of the invention also relate to a method of writing memory cells in an integrated circuit as defined above, comprising a step of erasing a first memory cell implanted in a mini box, wherein step of erasing comprises the steps of applying a negative erase voltage to the control gate of the charge storage transistor of the first memory cell, applying a positive voltage to the drain region of the charge accumulation transistor of the first memory cell the first memory cell, and raise the electric potential of the mini box by means of a junction leakage current blocked through the drain region, until the electric potential of the mini box is positive less than or equal to the voltage positive applied to the drain region, and causes a transfer of electrical charges by tunnel effect between the storage transistor loads and the mini box. According to one embodiment, the step of erasing the first memory cell is conducted without erasing a second memory cell implanted in the same mini box, and comprises a step of applying a positive non-erasure voltage to the control gate of the charge storage transistor of the second memory cell. Embodiments of the invention also relate to a method of writing memory cells in an integrated circuit as defined above, comprising a step of programming a first memory cell implanted in a mini box, in which the programming step comprises the steps of applying a positive programming voltage to the control gate of the charge storage transistor of the first memory cell, applying a negative voltage to the drain region of the charge accumulation transistor of the first cell memory, and decrease the electric potential of the mini box by means of a pass-through current passing through the drain region, until the electric potential of the mini box is negative and greater than the negative voltage applied to the region of drain, and causes a transfer of electrical charges by tunnel effect between the mini box and the transis tor charge accumulation.

According to one embodiment, the step of programming the first memory cell is conducted without programming a second memory cell implanted in the same mini box, and comprises a step of applying a negative non-erasure voltage to the gate controlling the charge storage transistor of the second memory cell.

Embodiments of a method for reading memory cells, memory cell structures and memory structures according to the invention will be described in the following in a nonlimiting manner, with reference to the appended figures among which: FIG. 1 previously described is a diagrammatic sectional view of a pair of conventional memory cells; FIG. 2 previously described is the electrical diagram of the memory cells; FIG. 3 previously described illustrates a method for the conventional reading of a memory cell; of the pair of memory cells of FIG. 1, FIG. 4 illustrates a reading method according to the invention of a memory cell of the conventional memory cell pair of FIG. 1; FIG. 5 is a sectional view. schematic of a first embodiment of a pair of memory cells according to the invention, - Figure 6 is a schematic sectional view of a second embodiment of a pair of memory cells. e of memory cells according to the invention, - Figure 7 shows an alternative embodiment of an element of the pair of memory cells of Figure 6, - Figure 8 is the electrical diagram of the pair of memory cells of Figure FIG. 9 illustrates a reading method according to the invention of a memory cell of the pair of memory cells of FIG. 6; FIG. 10 is a cross-sectional view of a portion of the pair of cells. FIG. 9, FIGS. 11 and 12 respectively illustrate erasure and programming steps of a memory cell of the pair of memory cells of FIG. 6; FIG. 13 shows voltages undergone by memory cells. FIGS. 14A to 14E are cross-sectional views showing steps of a method of manufacturing memory cells according to the invention; FIGS. 15A to 15F are views in FIG. cut showing a variant of Figs. 14A-14E; Figs. 16A-16E are top views showing further steps of a memory cell manufacturing method according to the invention; Figs. 17A, 17B are sectional views; of a step shown in Fig. 16B, Figs. 18A to 18E are top views showing a variation of the steps shown in Figs. 16A to 16E; Figs. 19A, 19B are sectional views of a step shown in Figs. FIG. 18B; FIG. 20 is a sectional view of a box receiving memory cells; FIG. 21 is a sectional view of a plurality of boxes receiving memory cells; FIG. 22 is a view of FIG. FIG. 23 is a circuit diagram of an erasable memory per page according to the invention; FIG. 24 is a circuit diagram of a word erasable memory according to the invention; FIGS. 25, 26 and 27; show voltages applied to the memory of FIG. 24 during reading, erasing and programming phases of memory cells, and FIG. 28 shows an electronic device comprising a memory according to the invention; FIGS. 29A, 29B are sectional views of a manufacturing step; represented in FIG. 16B, forming a variant of the steps shown in FIGS. 17A, 17B; FIG. 30 is a schematic sectional view of a third embodiment of a pair of memory cells according to the invention having the characteristic shown in Figs. 29A, 29B; Fig. 31 illustrates a reading method according to the invention of a memory cell of the pair of memory cells of Fig. 30; Fig. 32 shows the voltages undergone by the pair of cells. memory of FIG. 30 when reading a neighboring memory cell; FIG. 33 illustrates an erasing method according to the invention of a memory cell of the pair of memory cells of FIG. 30; FIG. 34 shows the voltages experienced by the pair of memory cells of FIG. 30 when erasing a neighboring memory cell; FIG. 35 illustrates a programming method according to the invention of a memory cell of the pair; Figure 36 shows the voltages experienced by the pair of memory cells of Figure 30 when programming a neighboring memory cell.

Table RD2 in Appendix 1 describes in connection with FIG. 4 a reading method according to the invention of one of the memory cells C11, C12 shown in FIG. 1. The voltages mentioned in the first column of the table have previously been described. in relation with the REF1 table. The example described here relates to the reading of the memory cell C11. The cell C12 can be read in a similar manner by applying to it the voltages applied to the cell C11, and vice versa. The reading method produces an effect similar to that described by table RD1: the C11 cell is conducting and is traversed by a current which also crosses the bit line BL. This current is sensed by a sense amplifier (not shown).

This method differs from that described by Table RD1 in that the gates of the two selection transistors ST11 and ST12 receive the read selection voltage Von, the non-selection voltage Voff read is no longer used for the pair of memory cells considered. Thus, the selection transistor ST12 of the cell C12 is turned on and has a conductive channel in its channel region CH2. To prevent the C12 cell from having a current flowing through, the voltage CGV applied to the control gate of the transistor FGT12, instead of being equal to the non-reading voltage Vnread, is equal to a inhibition voltage Vinh which forces the transistor FGT12 in the off state and thus prevents it from driving. The inhibition voltage Vinh, here negative, is chosen lower than the lowest possible value of the threshold voltage of the transistor FGT12, which is a function of its programmed or erased state, in order to ensure that the transistor FGT12 remains in the blocked state. In other words, the selection transistor ST12, usually used for the read selection of a memory cell, is no longer used in its usual function, for the pair of memory cells considered, and the floating gate transistor FGT12 is forced into the locked state.

Thus, a characteristic of this reading method is that the voltages applied to the gates of the selection transistors ST11, ST12 are identical regardless of the memory cell that is read in the pair of memory cells. It will be noted that this characteristic of the reading method concerns two neighboring memory cells forming a pair, that is to say, sharing the same source region and connected to the same bit line. It relates generally to two rows of memory cells consisting of neighboring memory cells connected to the same group of bit lines. This characteristic does not relate to other memory cells, the selection transistors of which are conventionally in the off state during the reading of one of these memory cells. This characteristic is to be compared with two other characteristics that appear in the tables ER1 and PG1, namely that the voltages applied to the gates of the selection transistors ST11, ST12 during the erasure or programming of a memory cell of the pair of cells memory, are themselves identical regardless of the memory cell erased or programmed. By combining these characteristics, it appears that the two selection transistors of a pair of memory cells can receive the same voltage whatever the process to be performed, read, erased or programmed, and whatever the memory cell is subject to of this process. This combination of features makes it possible to provide for structural modifications of the pairs of memory cells, with a view to reducing their bulk, as will now be described. FIG. 5 represents a first embodiment of a pair of memory cells C21, C22 according to the invention. Each memory cell C21, C22 comprises a floating gate transistor FGT21, FGT22 and a selection transistor ST21, ST22. The structure of the memory cells C21, C22 is identical to that of the memory cells C11, C12 with the exception of two characteristics: 1) the gates SG of the selection transistors ST21, ST22 are connected to a common word line WL. The word line WL is for example made in the first metal level ("metall") and is connected to the gates of the transistors by CT contacts passing through the dielectric layer DO which covers the two memory cells. 2) The classical SL source line (see Fig. 4) is deleted. The source region n3 of the transistors ST11, ST12 shown in FIG. 4 is replaced by a source region n3 'of the transistors ST21, ST22 which is deeper than the source region n3 and reaches the buried NISO layer delimiting the PW box in which two memory cells are implanted. Thus, the source region n3 'and the NISO layer are at the same electrical potential, and the NISO layer is used as the source line SL. These two characteristics are independent of each other and are shown in the same figure for convenience. The removal of the source line and its replacement by the NISO layer simplifies the structure of the higher metal levels. In addition, since the NISO layer is in the form of a plate delimited by vertical walls, it has a lower electrical resistance than a doped semiconductor layer which would be in the form of a strip.

The feasibility of using the NISO layer as a source line can be demonstrated by observing, in Tables RD2, ER1 and PG1, the electrical voltages applied to the SL source line and to the NISO layer: 1) Table RD2 shows that the electric potential SLV of the source line is the same as the potential VI of the NISO layer during the reading of a memory cell, namely the GND ground potential. Thus, the NISO layer can be used as a source line during the reading of a memory cell. 2) The table ER1 shows that, during the erasing of a memory cell, the voltage SLV of the source line is brought to a floating potential SLV2 = HZ while the voltage VI of the NISO layer is brought to a potential VI2 = 5V. However, the selection transistors are not on because the voltage SV applied to their gates (SV = SV2 = 5V) is identical to that of the substrate (VB = VB2 = 5V), so that no conductive channel is formed in their channel region CH2. Under these conditions, the source line SL can be brought to the potential of the NISO layer instead of being left floating, without this hindering the erasing process. It is therefore also possible to use the NISO layer as a source line, without changing its potential, during an erasure process, so that its isolation function, which requires this potential, is retained. 3) Finally, the table PG1 shows that during the programming of a memory cell, the voltage SLV of the source line is brought to a floating potential SLV2 = HZ while the voltage VI of the NISO layer is brought to a potential VI2 = GND. Since the selection transistors are also not on during programming of the memory cell, the source line SL can be brought to the GND potential instead of being left floating, without hindering the programming process. It is therefore also possible to use the NISO layer as a source line, without changing its potential, during the programming process. Table REF2 in Appendix 1 describes the voltages applied to the memory cells C21, C22.

Except for the references assigned to the different transistors, the REF2 table is identical to the REF1 table. The NISO voltage no longer appears and is considered to form the SLV voltage of the source line. The table RD3 in Appendix 1 describes in relation to FIG. 5 voltage values applied to the memory cells during the reading of the memory cell C21. Apart from the references attributed to the different transistors, the reading method is identical to that described in Table RD2. FIG. 6 represents a second embodiment of memory cells C31, C32 according to the invention. Each memory cell C31, C32 comprises a floating gate transistor FGT31, FGT32 and a selection transistor ST31, ST32. The transistors FGT31, FGT32 are of the same structure as the transistors FGT21, FGT22 and each has a horizontal channel region CH1 extending under its floating gate FG, between the drain regions n1 and source n2. The selection transistors ST31, ST32 are distinguished from the selection transistors ST21, ST22 in that they comprise a common vertical gate SGC. This vertical grid SGC is buried in the PW substrate via an insulating layer 12, for example oxide SiO 2, forming the gate oxide of the selection transistors ST31, ST32. It extends in the depth of the PW substrate and has left and right lower edges that penetrate into the NISO layer. The NISO layer thus forms, in its part surrounding the lower left and right edges of the SGC gate, the source region (S) of the transistors ST31, ST32. The NISO layer also forms, as previously, the source line SL of these transistors. The drain regions n2 (D) of the transistors ST31, ST32 (which also form the source regions of the floating gate transistors) are preserved, but here respectively extend along an upper left edge and along a upper right edge of the SGC grid. Thus, the transistor ST31 has a vertical channel region CH2 which extends opposite the left vertical wall of the gate SGC, between the first region n2 and the NISO layer. Similarly, the transistor ST32 has a vertical channel region CH2 which extends in front of the right vertical wall of the SGC gate, between the second region n2 and the NISO layer. With respect to the structure of the pair of memory cells C21, C22, the structure of the pair of memory cells C31, C32 has the advantage of occupying a very small semiconductor area, due to the suppression of the transistors of selection ST31, ST32 at the substrate surface, these having become buried transistors having a common gate. As will be seen later in light of examples of manufacturing processes, the vertical grid SGC is made from a conductive trench that connects several pairs of memory cells, sectional view in Figure 6. According to the method of manufacturing retained, this trench may have no electrical discontinuity. It can then be used directly as a word line WL, as indicated by the reference "WL" in FIG. 6. In other embodiments, this trench can be divided into different sections by STI insulation trenches (" Shallow Trench Isolation ") described later. In this case, each SGC vertical grid of each pair of memory cells is independent of the others and must be individually connected to a word line made in a metal level. FIG. 7 represents an embodiment of the vertical grid SGC in which it does not extend sufficiently in the depth of the substrate PW to reach the NISO layer. A doped region n3 "is thus implanted between the lower end of the SGC gate and the NISO layer .The region n3" surrounds the lower left and right edges of the gate SGC and forms the source region (S) of the transistors ST31, ST32. It extends to the NISO layer that it electrically connects to the source region of transistors ST31, ST32.

FIG. 8 is the electrical diagram of the memory cells C31, C32. The control gate of the transistor FGT31 is connected to a gate control line CGL, via a contact C4. The control gate of the transistor FGT32 is connected to a gate control line CGL, -pi via a contact C4. The drain regions (D) of the transistors FGT31, FGT32 are connected to a bit line BL via contacts C1. The vertical gate SGC is connected to a word line WLi, i + i common to the two memory cells. via a contact C3. Alternatively, it can itself form the word line as indicated above. The channel regions of the transistors FGT31, FGT32, ST31, ST32 are at the electric potential of the box PW, as represented by dashed lines. Finally, the source regions (S) of transistors ST31, ST32 are electrically connected to the NISO layer forming a source line. This can be connected via a contact C5 to a general source line SL made in a metal level.

Table REF3 in Appendix 1 describes in relation to FIG. 6 the voltages applied to the memory cells C31, C32. Except for the references assigned to the different transistors, the REF3 table is identical to the REF2 table. The voltage SLV is now a single voltage applied to the common gate SGC of the transistors ST31, T32.

The table RD4 in Annex 1 describes in relation to FIG. 9 the voltage values applied to the memory cells during the reading of the memory cell C31. The array RD4 is identical to the array RD3 except the references of the memory cells and the transistors. Thus, in reading, the memory cells C31, C32 are equivalent to the memory cells C21, C22. In FIG. 9, arrows show that a current flows through the channel region CH1 of the transistor FGT31 and the vertical channel region CH2 of the transistor ST31. A conductive channel also appears in the vertical channel region CH2 of the transistor ST32, under the effect of the voltage SV = Von applied to the common gate SGC, but the associated floating gate transistor FGT32 remains blocked under the effect of the voltage Vinh inhibition. FIG. 10 is a cross-sectional view of the transistor ST31 along a sectional plane AA 'shown in FIG. 9. The section plane passes through the drain region n2 of the transistor, the vertical channel region CH2 which extends into the PW substrate, NISO layer and WF wafer. It appears that the transistor is made between two isolation trenches STI, which do not reach here the NISO layer. Arrows show the current distribution in the channel region CH2 between the drain region n2 and the source region formed by the NISO layer. The channel region has a narrow portion between the two insulation trenches STI and a portion of indeterminate width where the current lines are no longer channeled by the insulation trenches STI and bloom until reaching the NISO layer. Unlike a conventional selection transistor, the transistor ST31 therefore has a conductive channel of variable width.

The table ER2 in Appendix 1 describes in relation to FIG. 11 voltage values applied to the memory cells during the erasing of the memory cell C31. The erasing method described by the table ER2 differs from that described by the table ER1 in that the voltage SLV of the source line, formed by the NISO layer, is equal to the voltage VI2 which is applied to the NISO layer in the method described in Table ER1. In FIG. 11, arrows show that an electric field appears between the substrate PW and the floating gate FG of the transistor FGT31. This electric field extracts electrons from the floating gate by tunnel effect (Fowler Nordheim effect). Furthermore, the transistor FGT32 undergoes a soft stress effect SST said "Soft Stress" due to the potential difference between the PW substrate and its control grid, here equal to 2.5 V. This effect of mild stress is insufficient to substantially extract electrical charges from the floating gate of this transistor. The table PG2 in Appendix 1 describes in relation to FIG. 12 voltage values applied to the memory cells during the programming of the memory cell C31. The programming method described by the table PG2 differs from that described by the table PG1 in that the voltage SLV of the source line, formed by the NISO layer, is equal to the voltage VI3 which is applied to the NISO layer in the process described in Table PG1.

In FIG. 12, arrows show that an electric field appears between the substrate PW and the floating gate FG of the transistor FGT31. This electric field causes a conductive channel to appear in the channel region CH1 of the transistor FGT31, and causes the injection of electrons into the floating gate by tunnel effect (Fowler Nordheim effect). Furthermore, the transistor FGT32 undergoes a mild stress effect SST due to the potential difference between the substrate PW and its control gate, here equal to -2.5 V. This mild stress effect is insufficient to inject charges. the floating gate of this transistor. The table PG2 'in Annex 1 describes in relation to FIG. 13 voltage values experienced by neighboring memory cells C31', C32 'during the programming step of the memory cell C31 illustrated in FIG. 12. These neighboring memory cells C31 ', C32' are connected to the same word line and grid control lines as memory cells C31, C32, but are connected to a different bit line BL '. With respect to the sectional plane of FIG. 12, these memory cells C31 ', C32' are "in front of" or "behind" the memory cells C31, C32 of FIG. 12. These memory cells receive the same voltages as the memory cells C31. , C32, except for the bit line voltage BLV which is brought to a non-programming voltage BLV3 ', for example the ground potential GND.

The transistor FGT32 'undergoes a mild stress effect SST because of the potential difference between the substrate PW and its control gate, here equal to -2.5 V. This mild stress effect is insufficient to inject electrical charges of the floating gate of this transistor. The transistor FGT31 'undergoes a non-cumulative stress effect, or NCS stress ("Non Cumulative Stress") due to the potential difference of 15V between the PW substrate and its control gate. However, since its drain region n1 is connected to ground via the bit line BL ', the conducting channel which is created in its channel region CH1 is maintained at OV and limits the injection of electrons into the its floating gate. This stress effect, which is known per se in the prior art, is said to be "non-cumulative" since it only operates on memory cells connected to the same gate control line as the transistor being programmed. Thus, it has been demonstrated in the foregoing that UCP memory cells comprising a buried vertical gate SGC and a source line formed by the NISO isolation layer can be used to realize a memory. such memory cells have no more use constraints than conventional UCP memory cells, in reading, erasure and programming, particularly in terms of soft stress SST or non-cumulative stress NCS.

FIGS. 14A to 14E show, in sectional views, the steps of a method for manufacturing vertical grids of selection transistors according to the invention. During a step S10, FIG. 14A, an N-doped NISO insulating layer is implanted in the WF wafer to delimit a P-type PW well forming a substrate. The vertical walls of the NISO insulation layer are not shown in the sectional view of Fig. 14A, which represents only a portion of the wafer. Optionally, a P-doped layer is also implanted in the box, above the NISO layer. This layer makes it possible to adjust the threshold voltages of the selection transistors ST31, ST32 previously described, as well as the threshold voltage of the blank cells (threshold voltage of the floating gate transistors in the absence of electrical charges trapped in their floating gates. ). During a step S11, FIG. 14B, an etching mask 10 is deposited on the substrate PW. Trenches 11 parallel to each other are etched into the substrate via the etching mask. The trenches here are deep enough to reach the NISO layer. During a step S13, FIG. 14C, the etching mask is removed and a gate oxide layer 12 is deposited on the substrate PW and in the trenches 11. During a step S14, FIG. polycrystalline silicon layer 13 is deposited on the PW substrate and in the trenches 11, above the oxide layer 12.

During a step S15, FIG. 14E, the polycrystalline silicon layer 13 is removed from the surface of the substrate PW, as well as the oxide layer 12, so that the surface of the substrate is ready for other manufacturing steps. described below. There remain the conductive trenches 11 in polycrystalline silicon 13, isolated from the substrate by the oxide layer 12, intended to form vertical gates SGC such as that shown in FIG.

Figures 15A to 15F illustrate sectional views of a variant of the manufacturing method which has just been described. The method comprises steps S20, S21, S22, S23, S24 and S25. Step S20, FIG. 15A, is identical to step S10 previously described. Step S21, FIG. 15B, is identical to step S11 described above, but here trenches 11 'are made which are shallower and do not reach the NISO layer. Step S22, FIG 15C, consists in implanting pockets n 3 "of N-doped semiconductor around the lower part of the trenches 11 'These pockets will form source regions n 3" of selection transistors, previously described in connection with FIG. Figure 7. The pockets n3 "are, for example, implanted through the inside and the bottom of the trenches, and are deep enough to reach the NISO layer.The steps S23, S24, S25, Figures 15D, 15E, 15F, are identical to the previously described steps S13, S14, 515. At the end of these steps, polysilicon conductive trenches 11 'are obtained, isolated from the substrate by the oxide layer 12, which will form vertical gates SGC as shown In Figure 7. These trenches do not reach the NISO layer but their lower part is surrounded by pockets n3 "which reach the NISO layer. Steps of a method of manufacturing memory cells in an integrated circuit are shown in Figs. 16A to 16E by top views. This method relates to the collective production of memory cells, to produce a memory of the type described below in relation with FIGS. 25 and 26. During a step S30, FIG. 16A, SGCi conducting trenches are produced in the PW substrate. i + i, SGCi + 2, i + 3 parallel to each other and isolated from the substrate. The trenches are made in accordance with one of the two manufacturing processes which have just been described. Only two trenches are represented, for the sake of simplification of the drawings. These trenches, noted with indices (i, i + 1) and (i + 2, i + 3), relate to the manufacture of four pages or four words of ranks i, i + 1, i + 2, and i + 3. During a step S31, FIG. 16B, shallow insulation trenches STI ("Shallow Trench Isolation") are made perpendicularly to the SGCp-pi, SGC, + 2 ,, + 3 conductive trenches. The trenches are parallel to each other and are made by etching the semiconductor and filling the trenches obtained with oxide. They reveal in the substrate semiconductor strips DST, DSJ + 1 perpendicular to the conducting trenches SGC ,,, + 1, SGC, + 2 ,, + 3, which are intended to subsequently form the drain and source regions. of transistors. The engraving of the STI insulation trenches also severely cuts the SGCi, i + i, SGCi + 2, and + 3 trenches in crossing areas. For the sake of clarity, FIGS. 17A and 17B are views in longitudinal and transverse section of the insulation trenches STI along cutting axes AA 'and BB' shown in FIG. 16B. The STI insulation trenches are shallower than the SGCi, i + i, SGCi + 2, i + 3 conductive trenches and show in them conductive sections separated by the STI insulation trenches. Each section is intended to form a vertical SGC grid common to two selection transistors. As can be seen in FIG. 17B, these sections are electrically interconnected by the part of the conductive trenches which is not cut by the insulation trenches STI and extends below them. In an embodiment which is not shown, the insulation trenches STI totally cut the conducting trenches and the various sections obtained are not electrically connected.

During a step S32, FIG. 16C, conducting lines CGC, CG1 + 1, CG1 + 2, CG1 + 3 parallel to the conducting trenches SGC1,1 + 1, SGC1 + 2,1 + 3 are formed on the PW substrate , at the rate of two conducting lines per conducting trench, one being placed on the left and the other on the right of the conducting trench. These conductive lines are formed by deposition of a layer of polycrystalline silicon of second level or "poly2", then etching thereof in strips. They are intended to form both control gates of floating gate transistors and CGL gate control lines. Step S32 is preceded by steps of forming floating gates that are not shown in the figures, performed after step S31. These steps include depositing a tunnel oxide layer on the substrate, depositing a first polycrystalline silicon layer or "poly 1", etching the "poly1" layer to form floating gates, and then depositing on the substrate of an oxide layer, for example of the ONO (Oxide-Nitride-Oxide) type, on which the conductive lines CGC to CG1 + 3 are formed.

During a step S33, FIG. 16D, N type dopants are implanted in the semiconductor strips DST, DSJ + 1, to form drain regions n1 and source n2 of floating gate transistors. The source regions n2, which extend to the right and to the left of the conducting trenches SGC1,1 + 1, SGC1 + 2,1 + 3, also form selection transistor drain regions, in accordance with the memory cell structure represented in FIG. 6. During a step S34, FIG. 16E, the whole of the substrate including conductive lines CGC, CGi + 1, CGi + 2, CGi + 3 is covered by the dielectric layer DO mentioned above. . This dielectric layer is not shown in the diagram to show the elements it covers. Orifices are made in the dielectric layer, and the orifices are then metallized to form the contacts C1, C3, C4 (see Fig. 8) intended to connect the elements that have just been made to metal conductive tracks. Thus, the contacts C1 are intended to connect the drain regions n1 to bit lines. The contacts C4 are intended to connect the conductive lines CGC, CGi + 2, CGi + 3 to a gate control circuit. The contacts C3 are intended to connect the conductive trenches SGCi, i + i, SGCi + 2, i + 3 to a word line pilot circuit. More precisely, if the conducting trenches are completely cut by the insulation trenches STI, the contacts C3 make it possible to connect them to lines of metal words which lead to the word line pilot circuit. In this case, additional contacts C3 'are provided for connecting to the word lines the sections formed by the severed conductive trenches. Conversely, if the conducting trenches are not completely severed, they can be used as word lines. The C3 contacts then make it possible to connect them to the word line pilot circuit.

The steps which have just been described are followed by steps of making metal lines mentioned below, or interconnection lines for connecting the memory cells to the control elements of the integrated circuit. These steps in themselves classic will not be described.

A variant of this method of manufacturing memory cells is shown in FIGS. 168 to 18E. The isolation trenches STI are performed first, during a step S40 shown in FIG. 18A. During a step S41, FIG. 18B, the conducting trenches SGC ,,, + 1, SGC, + 2 ,, + 3 are produced. Thus, here, the conducting trenches cut the STI insulation trenches. For the sake of clarity, FIGS. 19A and 19B are views in longitudinal and transverse section of the conductive trenches, along cutting axes AA 'and BB' shown in FIG. 18B. The SGC ,,, + 1, SGC, + 2 ,, + 3 conductive trenches are deeper than the STI insulation trenches and completely section them (Figure 19A). In an alternative embodiment, the conducting trenches are shallower than the isolation trenches and only partially cut them. In both cases, the electrical continuity of the conducting trenches is total over their entire depth (FIG. 19B). The other steps of this manufacturing process are identical to those described above. FIGS. 18C, 18D, 18E differ only from FIGS. 16C, 16D, 16E in that the SGC ,,, + 1, SGC, + 2 ,, + 3 conductive trenches cut the STI insulation trenches instead of being cut off by these. Thus, the method comprises a step S42 (FIG. 18C) for forming the conductive lines CG 'CG, + 1, CG, + 2, CG, + 3 preceded by stages of formation of floating grids and oxide deposition, not shown. , a step S43 (FIG. 18D) for forming the drain regions n1 and source n2 of the floating gate transistors, and a step S44 for forming the contacts C1, C3, C4, the additional contacts C3 'no longer being necessary here . FIG. 20 shows a formation step, in the wafer WF, of the NISO layer which delimits the PW box. The NISO layer is formed by two implantations of N-type dopants. A first implantation makes it possible to form a doped semiconductor horizontal "plate" which delimits the bottom of the PW box. A second implantation makes it possible to form vertical walls or "walls" of the PW box. In an alternative embodiment shown in FIG. 21, the NISO layer comprises a plurality of "walls" delimiting a plurality of boxes PW0, PW1, PW2, etc. It will be seen later that certain embodiments of a memory according to the invention require such a plurality of boxes, each of which can be brought to an electrical potential different from that of others. FIG. 22 shows a step of making contacts C5 on the upper edge of the walls of the NISO insulation layer. This step can be performed at the same time as the contact formation step C1, C3, C4 shown in FIG. 16E or 18E. Since the NISO layer is used as a source line, many C5 contacts are preferably provided along the upper edge of the walls of the NISO layer, as shown in the figure, in order to reduce its electrical resistance and favor the distribution of the lines. current in all directions. As indicated above, the contacts C5 make it possible to connect the NISO layer to a general source line SL made in a metal level, or to the control devices of the source line voltage. FIG. 23 represents an erasable memory MEM1 per page comprising a memory plane made in a PW box. The memory array comprises IxJ memory cells C31, C32 according to the invention, each memory cell C31, C32 comprising a charge accumulation transistor FGT31, FGT32 in series with a selection transistor ST31, ST32. The memory comprises I pages P each comprising a row of J memory cells, and a CGL grid control line. Figure 23 shows the first two pages P0, P1 of ranks 0 and 1, and the last two pages of ranks I-2 and I-1. The memory also comprises J bit lines BL, each being connected to memory cells of the same rank J belonging to different pages. FIG. 23 shows the first two rows of bits of ranks 0 and 1 and the last two rows of bits of ranks J-2 and J-1. Each bit line BL is connected to the drain regions of the floating gate transistors FGT of memory cells of the same rank j, while each CGL gate control line is connected to the control gates of the FGT transistors of memory cells of the same rank. . The source regions of the selection transistors are connected to the NISO layer surrounding the PW well.

The memory also comprises word lines WL which are connected to the gates of the selection transistors ST of the memory cells. Each word line WL controls the common selection grid of memory cells of two neighboring pages, or "linked" pages. Thus, a word line WL of rank (0) (1) is associated with the first two pages of rank 0 and 1 and controls the selection transistors of the memory cells of these two linked pages. Likewise, a rank word line (I-2) (I-1) is associated with the last two pages of rank I-2 and I-1 and controls the selection transistors of the memory cells of the two linked pages. The voltages applied to the various control lines of the memory array are provided by memory devices according to an address of a page to be erased or a group of memory cells to be read or programmed. These elements comprise: bit line locks BLT which apply to the different bit lines BL the appropriate BLV voltages during the programming of memory cells; a word line pilot circuit WLDCT ("Word Line Driver Circuit") which applies to the different word lines WL the SV voltages for the selection transistors; - a gate control circuit CGCTO which applies to the different gate control lines CGL the gate control voltages CGV of the floating gate transistors; SLS source line which applies the SLV source line voltage to the NISO layer, - a PWS box switch which applies the substrate voltage VB to the PW box, - SA amplifiers ("Sense Amplifiers"), which apply to the different bit lines BL the appropriate BLV voltages during the reading of memory cells, and provide a binary word read in the memory, for example an 8 bit word B 0-B7, and - a CDEC column decoder, which connects the SA sense amplifiers to the different bit lines. The voltages provided by these various members are described in Tables RD4, ER2, PG2 and PG2 '. In particular, the BLT bit line locks provide the "bias voltage during programming" or the "non-programming voltage" in the PG2 and PG2 'tables. The read amplifiers SA provide the "reading bias voltage" in table RD4. It will be clear to one skilled in the art that this memory structure comprises a word line WL common to two rows of neighboring memory cells (for example the pages Po, Pi), in which the common word line is connected to grids of selection transistors ST31 of the first row and grids of selection transistors ST32 of the second row may be modified to receive memory cells C21, C22 of the type described above in relation to FIG. selection transistors ST21, ST22 do not have a common gate but share the same word line WL. FIG. 24 represents a word-erasable memory MEM2 comprising a memory plane made in a plurality of CPW boxes. Each CPW boxes comprises memory cells C31, C32 according to the invention, each comprising a charge accumulation transistor FGT31, FGT32 in series with a selection transistor ST31, ST32. The memory also includes SPW boxes receiving control switches. The structure of the memory array is of the CPW-SPW-CPW / CPW-SPW-CPW / CPW-SPW-CPW / ... type, a control box being associated with two boxes of memory cells and arranged therebetween (for for reasons of readability, FIG. 24 represents only one SPW box and two CPW boxes). In a variant, the structure of the memory plane could be of the CPW-SPW / CPW-SPW / CPW-SPW / ... type, by providing a cell box control box. The structure of each box CPW is similar to the structure of the memory array of the memory MEM1 erasable per page, but the pages are replaced by words WD, that is to say a group of memory cells containing a number of memory cells less than the number of memory cells of a page, for example 8 memory cells. A page of the memory MEM2 is thus composed of a plurality of words WD. Figure 24 shows the first four pages Po, Pi, P2, P3 of the memory plane.

More particularly, each page comprises: a plurality of WD words distributed in different CPW boxes, CGL grid control lines each assigned to a WD word, a general MCGL gate control line. ") which traverses the whole memory plane and provides a general grid control voltage MCGV to the different gate control lines CGL, and - a word line WL, shared with a neighboring page, which crosses the whole plane memory.

Each CPW case includes a WD word on each page. Each memory cell of each word is connected to a bit line BL, to the gate control line CGL, common to all the memory cells of the word, and to the NISO layer of the box. The CGL grid control line of the word is connected to the general grid control line MCGL of the page to which the word belongs, via the SPW control box. The control box SPW comprises: a first vertical row of switching transistors CS controlled by a common signal NOSEL, designed to control the CGL lines of the cell box to the left of the control box, a first vertical row of switching transistors SS controlled by a common signal SEL, also intended to control the CGL lines of the cell box to the left of the control box, - a second vertical row of switching transistors CS controlled by a common signal NOSEL, provided for controlling the lines CGL the cell box located to the right of the control box, and - a second vertical row of SS switch transistors controlled by a common signal SEL, also intended to control the CGL lines of the cell box to the right of the control box.

Specifically, each switch CS connects a CGL line to ground, and each SS switch connects a CGL line to the general grid control line MCGL of the page to which the word belongs. The combination of signals SEL and NOSEL thus makes it possible to connect the CGL line to the ground or to connect it to the general control line MCGL. The voltages applied to these various lines of the memory plane are provided by memory organs according to a selection address of a word to be erased, read or programmed. These elements comprise: - BLT bit line locks, which apply to the different bit lines BL the appropriate BLV voltages during the programming of memory cells, - a WLDCT word line pilot circuit that applies to the different lines of WL words the selection voltages SV for the selection transistors, - a gate control circuit CGCT1, which applies to the different general grid control lines MCGL gate control voltages CGV, - column latches CLT which provide the signals SEL and NOSEL at each vertical row of switches CS, SS. - an SLS source line switch which applies the SLV source line voltage to the NISO layer of all the caissons, - a CPWS caisson switch per CPW box, which applies the substrate voltage VB to the CPW box, - a switch SPW case SPW box, which applies the substrate voltage VB 10 to the CPW box, - SA sense amplifiers, which apply to the different BL bit lines the appropriate BLV voltages during the reading of memory cells, and provide a binary word read in the memory, for example an 8-bit word B0-B7, and a CDEC column decoder, which connects the sense amplifiers to the different bit lines. The memory array thus organized makes it possible to apply to the memory cells the reading, erasing and programming methods previously described. The table RD5 in Annex 1 describes in relation to FIG. 25 voltage values applied to the memory plane 20 during the reading of memory cells. FIG. 25 shows the distribution of these voltage values during the reading of two memory cells C31, C31 'which are framed in the figure. The table ER3 in Annex 1 describes in relation to FIG. 26 voltage values applied to the memory plane during erasure of a word. Figure 26 shows the distribution of these voltage values when erasing a word WD which is framed in the figure. Table PG3 in Appendix 1 describes in connection with FIG. 27 examples of values of voltages applied to the memory plane during programming of a memory cell. Figure 27 shows the distribution of these voltage values when programming a memory cell C31 which is framed in the figure.

It appears in tables ER3, PG3 that during the deletion of a word, a general grid control line not selected but linked to the selected general grid control line (ie which is associated with a page linked to the page selected) requires a voltage different from that applied to a general grid control line that is not selected. Also, while reading memory cells, a grid control line that is not selected but linked to the selected grid control line requires a voltage different from that applied to an unselected grid control line. It will be clear to those skilled in the art that this memory structure comprising a word line WL common to two rows of neighboring memory cells forming words WD, can be modified to receive memory cells C21, C22 of the type described above. High in relation to FIG. 5, whose selection transistors ST21, ST22 do not have a common gate but share the same word line WL.

FIG. 28 represents an example of application of a memory MEM according to the invention (MEM1 or MEM2). The memory MEM is arranged in an integrated circuit IC equipped with a processor and an ICT communication interface circuit, for example an integrated circuit for a smart card. The integrated circuit is mounted on a CD medium, for example a plastic card. The memory MEM makes it possible, with identical memory capacity, to reduce the size and the cost price of the integrated circuit, or, with the same integrated circuit area, to increase the storage capacity of the memory. In a variant of the manufacturing method previously described, memory cells are formed in mini caissons which are electrically isolated from each other by the SGC ,,, + 1, SGC, + 2 ,, + 3 conductive trenches and the trenches. STI insulation. In order to obtain this characteristic, it is ensured during the step of making insulation trenches STI previously described (see FIG. 16B or FIG. 18A) that the depth of the insulation trenches STI is sufficient to reach the insulation layer. NISO and that the depth of the conducting trenches SGC ,,, + 1, SGC, + 2 ,, + 3 is also sufficient to reach the NISO layer (see Figures 14A to 14E). This variant of the manufacturing process is illustrated on Figures 29A, 29B, which replace Figures 17A, 17B previously described in connection with the manufacturing method shown in Figures 16A to 16E. Figures 29A and 29B are longitudinal and transverse sectional views of insulation trenches STI along the cutting axes AA 'and BB' shown in Figure 16B. STI insulation trenches may be substantially deeper or substantially shallower than SGC1,1 + 1, SGC1 + 2,1 + 3 conducting trenches, provided both trenches reach the NISO layer. They could even be one or the other, or both, of a depth such that they would exceed the NISO layer. If the isolation trenches are substantially deeper than the conducting trenches, as shown here, they reveal in them conductive sections. Each section is intended to form a vertical SGC grid common to two selection transistors. In the opposite case, the conducting trenches retain a lower part not severed by the isolation trenches, which electrically connects their different sections (not shown). This variant can also be applied to the manufacturing method previously described in relation with FIGS. 18A to 18E, in which the insulation trenches STI are severed by the conducting trenches SGC1,1 + 1, SGC1 + 2,1 + 3. The fact that the insulation trenches and the conducting trenches both reach the NISO layer then makes appear, in the PW box, a plurality of mini boxes which are isolated in three dimensions relative to each other by: - the trenches STI insulation, - the SGC1,1 + 1, SGC1 + 2.1 + 3 conductive trenches, these being effectively electrically insulated from the substrate by the insulating layer 12 surrounding them (see Figure 14E for example), and - the NISO layer itself.

Figure 30 is a sectional view showing a third embodiment of memory cells according to the invention, made according to the variant of the manufacturing method which has just been described. More particularly, FIG. 30 shows two pairs PR1, PR2 of memory cells connected to the same bit line BL. Each pair PR1, PR2 comprises two memory cells C41, C42 according to the invention (the same references being assigned to the memory cells of each pair). Each memory cell C41, C42 comprises a floating gate transistor FGT41, FGT42 and a selection transistor ST41, ST42. Transistors FGT41, FGT42 are of the same structure as transistors FGT31, FGT31 previously described and each has a horizontal channel region CH1 extending under their floating gate FG, between the drain regions n1 and source n2. The selection transistors ST41, ST42 have the same structure as the selection transistors ST31, ST32 previously described and comprise a buried vertical common gate SGC which reaches the NISO layer, the transistor ST41 having a vertical channel region CH2 opposite the wall vertical left of the SGC grid, and the transistor ST42 a CH2 vertical channel region in front of the right vertical wall of the SGC grid. Moreover, it is assumed in this embodiment that the common gate SGC of the selection transistors of each pair PR1, PR2 is entirely cut at its ends by the insulation trenches STI, and is connected via contacts to a word line WL made in a first metal level ("metall) .The bit line BL is in this case made in a second metal level (" metal2 ") and the drain regions n1 of the transistors FGT41, FGT42 of each pair of memory cells are connected to the bit line BL via conductive contacts and bushings of a type already described, and each pair of memory cells C41, C42 thus does not distinguish from the pair of memory cells C31, C32 in that the STI insulation trenches which extend in front of and behind the memory cells (in front of and behind the sectional plane of FIG. 30) reach the NISO layer, as represented by a horizontal dotted line ntal mounting the depth of the insulation trenches STI. As a result: - the second memory cell C42 of the first pair PR1 and the first memory cell C41 of the second pair PR2 are in a first mini-box MPW1, - the second memory cell C42 of the second pair PR2 is located in a second mini-well MPW2, which also receives the first memory cell C41 from a pair of memory cells extending to the right of the pair PR2, not shown in FIG. 30, and the first memory cell C41 of the first pair PR1 is in a third mini-well MPW3, which also receives the second memory cell C42 from a pair of memory cells extending to the left of the pair PR2, not shown in FIG. 30. With the exception of the electric potential VB of the mini boxes, the voltages applied to the memory cells C41, C42 are identical to those applied to the memory cells described by the table REF3: - BLV is the voltage applied to the bit line BL and therefore applied to the drain regions n1 of the transistors FGT41, FGT42 of each of the pairs PR1, PR2, - CGV is the voltage applied to the control gate of a transistor FGT41, FGT42 via a control line gate (not shown), - SV is the selection voltage applied to the common gate SGC of the transistors ST41, ST42 of the same pair PR1, PR2 via the corresponding word line WL, - SLV is the voltage applied to the NISO isolation layer as the SL source line.

In this embodiment of the memory cells, the electric potential VB of the mini boxes is not "applied" but induced via the bit line BL, erasing and programming. The electrical potential VB of each mini box is, by default, the floating potential (HZ), but may vary depending on the voltage applied to the bit line. The mini boxes being isolated from each other, each mini box can thus have a floating potential VB different from that of the neighboring mini boxes. One embodiment of a method for reading, erasing and programming the memory cells is based on this technical effect to control the potential VB mini boxes, as will be described in the following.

A method of reading the memory cell C41 of the second pair PR2 of memory cells is illustrated in FIG. 31 and described by the table RD6 in Appendix 2. This method differs from that previously described in relation to FIG. 9 in that the mini boxes MPW1, MPW2, MPW3 are not connected to the ground and are at a potential VB1, VB1 'which is floating (HZ). Arrows show that a current flows through channel region CH1 of transistor FGT41 of cell C41 of pair PR2, and the vertical channel region CH2 of corresponding transistor ST41. A conductive channel also appears in the vertical channel region CH2 of the transistor ST42 having the same gate SGC, under the effect of the voltage SV = Von applied to the common gate SGC, but the associated floating gate transistor FGT42 remains blocked under the effect of the Vinh inhibition voltage.

The table RD6 also describes, in connection with FIG. 32, voltage values applied to the memory cells during the reading of a memory cell connected to the same gate control line and to the same word line WL as that of the memory cell. C41 of the second pair PR2, but connected to another bit line than the bit line BL than that shown in the figure. With respect to the sectional plane of FIG. 36, these memory cells are in front of or behind the memory cells C41, C42 of FIG. 36. The memory cells C41, C42 of the PR2 pair receive the same voltages as the memory cell in the process of reading, except the BLV bit line voltage which is brought to a non-reading voltage BLV1 ', here the floating potential HZ. Thus, no current passes through the memory cell C41 of the pair PR2 although its transistors FGT41 and ST41 each have a conductive channel in their channel region CH1, CH2. The table ER4 in Appendix 2 describes in relation to FIG. 33 voltage values applied to the memory cells during the erasing of the memory cell C41 of the PR2 pair of memory cells. In contrast to the erasing method previously described, the bit line BL here receives a positive and non-zero voltage BLV2, for example 5V, and the potential VB2 of the corresponding mini box MPW1 is floating. At the same time, the control gate CG of the transistor FGT41 of the memory cell C41 receives the negative erase voltage Ver, for example -10V. The PN junction between the mini-well MPW1 and the drain region n1 of the transistor FGT41 is in the off state due to the positive bias applied to the drain region n1 (here 5V) via the bit line BL . However, the negative voltage V L induces a high electric field which causes a non-negligible inverse leakage current to appear in a zone of the PN junction close to the floating gate FG of the transistor FGT41, this current being called the "band-to-leakage" leakage current. band "(" band-to-band current "). This leakage current rapidly increases the floating potential VB of the mini box MPW1, until it reaches or is close to the potential of the drain region n1 imposed by the bit line BL, here 5V. Under these conditions, and as shown in FIG. 33 by arrows, an erase electric field appears between the mini box MPW1 and the floating gate FG of the transistor FGT41. This electric fading field extracts electrons from the floating gate by tunnel effect (Fowler Nordheim effect). Moreover, the transistor FGT42 which is in the same mini-well MPW1, that of the PR1 pair (and not, as previously, that of the same pair), undergoes a mild stress effect SST because of the difference in potential between the mini box MPW1 and its control grid, here equal to 2.5 V. This mild stress effect is insufficient to extract significantly electric charges from the floating gate of this transistor. During this erasing process, the potential VB2 'of the mini boxes MPW2, MPW3 which do not contain a memory cell selected in erasure, also tends to the voltage BLV2 but slower due to a band-to-band current much lower, the transistors FGT41, FGT42 of these memory cells receiving the positive non-erasing voltage Vner, here 2.5 V.

The table ER4 also describes, in connection with FIG. 34, voltage values applied to the memory cells during the erasure of a memory cell connected to the same gate control line and to the same word line WL as the cell. memory C41 of the pair PR2, but connected to another bit line than the bit line BL shown in the figure. The memory cells C41, C42 receive the same voltages as the memory cells being erased, except for the bit line voltage BLV which is brought to a non-erasing voltage BLV2 ', here the ground potential GND. The voltage VI2 applied to the NISO layer, for example 5 V, could raise the floating potential VB2 "of the mini-boxes MPW1, MPW2, MPW3 to 5 V by reverse junction leakage, but passing junctions between the mini-boxes and the drain regions which are grounded limit this voltage rise to the value of a passing diode voltage, for example 0.6 V. As the transistor FGT41 of the memory cell C41 of the PR2 pair receives the voltage of erasing Ver on its CG control grid, it undergoes a non-cumulative stress effect of low intensity, under a potential difference of the order of 10.6 V.

The table PG4 in Annex 2 describes in relation to FIG. 35 voltage values applied to the memory cells during the programming of the memory cell C41 of the PR2 pair of memory cells. The voltages applied to the memory cell are identical to those previously described in relation with FIG. 12 and table PG2, with the difference that the mini boxes are at a floating potential VB3, VB3 '. Under the effect of the negative voltage BLV3 applied to the bit line, here -5 V, the PN junctions between the drain regions n1 of the transistors FGT41, FGT42 and the mini boxes are conducting and raise the floating potential VB3, VB3 until it reaches a value equal to the voltage BLV3 minus the diode voltage passing, here 0.6 V. Thus, the potentials VB3, VB3 'stabilize in the vicinity of -4.4 V. In these conditions, and as shown in FIG. 33 by arrows, a programming electric field appears between the mini box MPW1 and the floating gate FG of the transistor FGT41. This electric field causes a conductive channel to appear in the CH1 channel region of the transistor and causes the injection of electrons into its floating gate by tunnel effect (Fowler Nordheim effect).

The table PG4 in Annex 2 also describes in relation to FIG. 36 voltage values applied to the memory cells when programming a memory cell connected to the same grid control line and to the same word line WL as to the memory cell C41 of the PR2 pair, but connected to another bit line than the bit line BL shown in the figure. The bit line BL is then brought to a non-selection voltage BLV3 ', here the ground potential GND. Under these conditions, the floating potential VB3 "of each mini box does not tend to a significant voltage, and remains neutral (HZ) The transistor FGT41 of the PR2 pair undergoes a non-cumulative stress effect NCS which is not very active due to the potential of 10V applied to its control gate CG As its drain region n1 is connected to the ground via the bit line BL, the conducting channel which is created in its channel region CH1 is maintained at OV and limits the injection of electrons into its floating gate.

In summary, memory cells according to this third embodiment can be read, erased and programmed in a manner similar to those performed according to the second embodiment and shown in FIG. 6, with the difference that they do not require a control of the electrical potential of the PW box containing the mini boxes, the potential of each mini box being controlled in erasure and programming via the bit lines. Moreover, as follows from the foregoing description, the segmentation of the PW box into mini MPW boxes allows individual erasure or individual programming of each memory cell. The memory MEM1 previously described in relation with FIG. 23 can therefore be implemented with such memory cells to obtain a memory which is intrinsically and advantageously erasable and programmable by bit. In practice, the control members of the memory MEM1 can be configured to form a page erasable memory, word erasable or erasable by bit, depending on the intended application. In particular, the BLT bit line locks are configured to control both the erasure and the programming of the memory cells, by supplying the different bit line voltages that have just been described. It will be clear to those skilled in the art that a memory cell according to the invention and a memory according to the invention are susceptible of various other variants and applications. In particular, although in the foregoing embodiments of memory cell embodiments have been described from floating gate transistors, other types of charge storage transistors could be used, for example transistors provided with silicon ("silicon dots") embedded in a dielectric material, which accumulate electrical charges and replace the floating gates.

Annex 1 forming an integral part of the description References attributed to the voltages REF1 Voltages applied to the cells C11, C12 BLV Voltage applied to a bit line BL CGV Voltage applied to the control gate of a transistor FGT11, FGT12 VB Voltage applied to the PW substrate (box) SV Voltage applied to the gate of a transistor ST11, ST12 SLV Voltage applied to the source line SL VI Voltage applied to the insulation layer NISO REF2 Voltages applied to the cells C21, C22 BLV Voltage applied to a line of bit BL CGV Voltage applied to the control gate of a transistor FGT21, FGT22 VB Voltage applied to the substrate PW (box) SV Voltage applied to the gate of a transistor ST21, ST22 SLV Voltage applied to the insulation layer NISO in as source line SL REF3 Voltages applied to cells C31, C32 BLV Voltage applied to a bit line BL CGV Voltage applied to the control gate of a FGT transistor 31, FGT32 VB Voltage applied to the PW substrate (box) SV Voltage applied to the SGC common gate of the ST31, T32 SLV transistors Voltage applied to the NISO insulation layer as a source line SL Examples of voltage values during the reading an RD1 memory cell Ref. Ex. Cell reading C11 (prior art) BLV BLV1 1V Reading bias voltage CGV Vread 1.2V Transistor reading voltage FGT11 CGV Vnread VB1 Non-reading voltage applied to FGT12 VB VB 1 GND Bias voltage during read SV Von 2V Reading selection voltage applied to ST11 SV Voff GND Reading clamping voltage applied to ST12 SLV SLV1 GND Polarization voltage during reading VI VII GND Polarization voltage during reading RD2 Ref. Ex. Cell reading C11 BLV BLV1 1V Reading bias voltage CGV Vread 1.2V Transistor reading voltage FGT11 CGV Vinh -2V Transistor inhibit voltage FGT12 VB VB 1 GND Polarization voltage during SV Von 2V reading Reading selection voltage of transistors ST11, ST12 SLV SLV1 GND Polarization voltage during reading VI VII GND Polarization voltage during reading RD3 Ref. Ex. Cell reading C21 BLV BLV1 1V Reading bias voltage CGV Vread 1.2V Transistor reading voltage FGT21 CGV Vinh -2V Transistor inhibit voltage FGT22 VB VB 1 GND Bias voltage during SV playback Von 2V Reading selection voltage of transistors ST21, T22 SLV SLV1 GND Polarization voltage during reading5 RD4 Ref. Ex. Reading cell C31, figure 9 BLV BLV1 1V Reading bias voltage CGV Vread 1.2V Transistor reading voltage FGT31 GV Vinh -2V Transistor inhibit voltage FGT32 VB VB1 GND Polarization voltage during SV reading Von 2V Readout voltage of transistors ST31, T32 SLV VII GND Polarization voltage during reading Examples of voltage values during deletion of a memory cell ER1 Ref. Ex. Clearing cell C11 (prior art) BLV BLV2 HZ Polarization voltage during clearing CGV Ver -10V Clearing voltage of transistor FGT11 CGV Vner 2.5V Non-erasing voltage of transistor FGT12 VB VB2 5V Voltage of polarization during deletion SV SV2 5V Polarization voltage during deletion SLV SLV2 HZ Polarization voltage during deletion VI VI2 5V Polarization voltage during deletion ER2 Ref. Ex. Deletion of cell C31, Figure 11 BLV BLV2 HZ Polarization voltage during clearing CGV Ver -10V Clearing voltage of transistor FGT31 CGV Vner 2.5V Non-erasing voltage of transistor FGT32 VB VB2 5V Polarization voltage during deletion SV SV2 5V Polarization voltage during deletion SLV VI2 5V Polarization voltage during deletion Examples of voltage values during programming of a memory cell PG1 Ref. Ex. Programming of cell C11 (prior art) BLV BLV3 -5V Bias voltage during programming GV Vprog 10V FGT11 transistor programming voltage CGV Vnprog -2.5V FGT12 VB transistor voltage non-programming voltage VB3 -5V Voltage from polarization during programming SV SV3 -5V Bias voltage during programming SLV SLV3 HZ Bias voltage during programming VI VI3 GND Bias voltage during programming PG2 Ref. Ex. Programming of cell C31, Figure 12 BLV BLV3 -5V Bias voltage during programming GV Vprog 10V FGT31 transistor programming voltage GV Vnprog -2,5V Transistor non-programming voltage FGT32 VB VB3 -5V Bias voltage during programming SV SV3 -5V Bias voltage during programming SLV VI3 GND Bias voltage during programming PG2 'Ref. Ex. Voltages sustained by a neighboring cell BLV BLV3 'GND Non-programming voltage CGV Vprog 10V Voltage experienced by transistor FGT31' CGV Vnprog -2,5V Voltage experienced by transistor FGT32 'VB VB3 -5V Polarization voltage during programming SV SV3 -5V Voltage experienced by transistors ST31 ', ST32' SLV VI3 GND Bias voltage during programming Examples of voltage values during reading of a memory cell (Fig. 25) RD5 Voltage Line Value Status BLV BL 1V Line bit rate (BL) selected BLV BL HZ Bit line not selected MCGV MCGL 1.2V General grid control line selected MCGV MCGL -2V General grid control line not selected related to the selected general grid control line MCGV MCGL GND General grid control line not selected CGV CGL 1.2V Selected grid control line CGV CGL -2V Unselected grid control line linked to cone line selected grid control CGV CGL GND Unselected grid control line VB - GND Selected box VB - GND Unselected box VB - -2V Switches box SS, CS SV WL 2V Selected word line SV WL GND Unselected word line SLV NISO GND Source and Layer Line Voltage NISO SEL - 5V SS Switches Control of the selected subwoofer NOSEL - -2V CS Switch Control of the selected subwoofer SEL - 5V SS Switch Control of the unselected subwoofer NOSEL - -2V CS switches of unselected housing5 Examples of voltage values during deletion of a word (Fig. 26) ER3 Voltage Line Value Status BLV BL HZ Bit line (BL) selected BLV BL HZ Bit line not selected MCGV MCGL -10V General grid control line selected MCGV MCGL 2.5V General line control line not selected MCGV MCGL 2.5V General Grid Control Line General Grid Control Line Not Selected CGV CGL -10V Grid Control Line Selected GTC CGL 2.5V Grid Control Line Unselected Related to Control Line selected GVC CGL 2.5V Unselected gate control line VB - 5V Selected box VB - GND Unselected box VB - -10V Switches box SS, CS SV WL GND Selected word line SV WL GND Word line no SLV NISO 5V Source and Layer Line Voltage NISO SEL - 5V SS Switches Control of the selected subwoofer NOSEL - -10V CS Switch Control its selected SEL - -10V Control of the SS switches of the unselected box NOSEL - 5V Control of the CS switches of the unselected box Examples of voltage values during programming of a word (Fig. 27) PG3 Voltage Line Value Status BLV BL -5V Bit line (BL) selected BLV BL GND Bit line not selected MCGV MCGL 10V General grid control line selected MCGV MCGL -2,5V General grid control line not selected linked to the selected general grid control line MCGV MCGL -2,5V General grid control line not selected CGV CGL 10V Selected grid control line CGV CGL -2,5V Not selected grid control line linked to the line selected grid control CGV CGL -2.5V Unselected gate control line VB - -5V Selected box VB - GND Unselected box VB - -2.5V Switch box SS, CS SV WL -5V Selected word line SV WL -5V Unselected word line SLV NISO GND Source and Layer Line Voltage NISO SEL - 13V SS Switch Control of the selected subwoofer NOSEL - -2,5V Switch Control C S of the selected box SEL - -2,5V Control of the SS switches of the unselected box NOSEL - 5V Control of the CS switches of the unselected box Annex 2 forming an integral part of the description Examples of voltage values during the reading of a memory cell (Figures 31 and 32) RD6 Voltage Ref. Value Status BLV BLV1 1V Bit line (BL) selected BLV BLV1 'HZ Bit line (BL) not selected CGV Vread 1.2V Grid control line selected CGV Vinh -2V Grid control line not selected but related to selected grid control line CGV Vn s el GND Grid control line not selected and not linked to the selected grid control line VB VB1 HZ Mini box comprising at least one memory cell selected for reading VB VB1 'HZ Mini box comprising two non-selected memory cells and connected to a selected bit line (BL) VB VB1 "HZ Mini box comprising two non-selected memory cells and connected to an unselected bit line (BL) SV Von 2V Selected word line (WL) SV Voff GND Unselected word line (WL) SLV VII GND Source and NISO layer line voltage Examples of voltage values during deletion of a memory cell (Fig. 33 and 34 ER4 Voltage Ref Value Status BLV BLV2 5V Bit line (BL) selected BLV BLV2 'GND Bit line (BL) not selected CGV Ver -10V Grid control line selected CGV Vner 2.5V Grid control line not selected but linked to the selected grid control line CGV Vner 2.5V Grid control line not selected and not linked to the selected grid control line VB VB2 5V (HZ) Mini box with at least one selected memory cell in clearing VB VB2 '<5V (HZ) Mini box comprising two unselected memory cells and connected to a selected bit line (BL) VB VB2 "<0.6V (HZ) Mini box comprising two unselected memory cells and connected to bit line (BL) not selected SV Voff GND Word line (WL) selected SV Voff GND Word line (WL) not selected SLV VI2 5V Source and layer line voltage NISO5 Examples of voltage values during the programming of a memory cell (Fig. 35 and 36) PG4 Voltage Ref. Value Status BLV BLV3 -5V Bit line (BL) selected BLV BLV3 'GND Bit line (BL) not selected CGV Vprog 10V Grid control line selected CGV Vnprog -2,5V Grid control line not selected but linked to the selected grid control line CGV Vnprog -2,5V Grid control line not selected and not linked to the selected grid control line VB VB3 -4,4V (HZ) Mini box comprising at least one memory cell selected from programming VB VB3 '-4,4V (HZ) Mini box comprising two unselected memory cells and connected to a selected bit line (BL) VB VB3 "HZ Mini box comprising two unselected memory cells and connected to a bit line ( BL) unselected SV SV3 -5V Selected word line (WL) SV SV3 -5V Unselected word line (WL) SLV VI3 GND Source and layer line voltage NISO5

Claims (14)

REVENDICATIONS1. A method of manufacturing on a semiconductor substrate (WF, PW) an integrated circuit (IC) comprising a non-volatile memory (MEM1) comprising memory cells (C41, C42) each comprising a charge-storage transistor (FGT41, FGT42) and a selection transistor (ST41, ST42), the method comprising the steps of: - implanting (S10, S22) in the depth of the substrate a doped isolation layer (NISO), - making (S11-S15, S21 -S25, S30, S41) in the substrate of isolated conductive trenches (SGC ,, i + i) reaching the insulating layer (NISO) and each delimited by an insulating layer (12), to form grids (SGC) of selection transistors, - making (S31, S40) in the insulation trench substrate (STI) perpendicular to the conducting trenches (SGC +1), and reaching the insulating layer (NISO), - making (S32, S42) on the substrate (PW) conductive lines (CGC, CG, + i) parallel to the conducting trenches (SGCi , i + 1), to form control gates (CG) of charge-storage transistors (FGT41, FGT42), and - to implant (S33, S43) doped regions (n1, n2) on either side of isolated conductive trenches and conductive lines parallel to the conductive trenches, for forming drain and charge storage transistor source regions (FGT41, FGT42) and memory cell selection transistors (ST41, ST42), isolation trenches, and isolated conducting trenches delimiting in the substrate a plurality of mini boxes (MPW1, MPW2, MPW3) electrically isolated from each other, each having a floating electrical potential, and each comprising two memory cells, The method of claim 1, wherein the isolation trenches (STI) are designed to sever the conducting trenches (SGC ,, i + i) into a plurality of sections each forming a common vertical grid (CGS) of two selection transistors (ST41, ST42) of two memory cells belonging to different mini-boxes (MPW1, MPW2, MPW3). The method of claim 2, wherein the isolation trenches (STI) are designed to completely sever the conducting trenches (SGC ,, i + i) into a plurality of sections each forming a common vertical grid (CGS). two memory cells, and comprising a step of producing, in a metal layer, a word line (WL) which electrically connects the different sections. 4. The method of claim 1, wherein the conductive trenches (SGC ,,, + i) are designed to cut the isolation trenches (STI) into a plurality of sections. 5. Integrated circuit (IC) comprising a non-volatile memory on a semiconductor substrate (WF, PW), characterized in that it comprises: a doped insulation layer (NISO) implanted in the depth of the substrate, trenches isolated conductors (SGC ,,, + i) reaching the insulating layer (NISO) and each delimited by an insulating layer (12) forming gates (SGC) of selection transistors (ST41, ST42) of memory cells (C41 , C42), - insulating trenches (STI) perpendicular to the conducting trenches (SGC ,,, + i), and reaching the insulating layer (NISO), - parallel conductive lines (CG 'CG, + i) conductive trenches (SGC ,,, + 1) extending over the substrate (PW) and forming control gates (CG) of charge storage transistors (FGT41, FGT42) of memory cells (C41, C42), and doped regions (n1, n2) on each side of the isolated conducting trenches and conductive lines parallel to the trenches conductors, forming drain and charge storage transistor source regions (FGT41, FGT42) and memory cell selection transistors (ST41, ST42), isolation trenches and isolated conductive trenches delineating in the substrate a plurality of mini boxes (MPW1, MPW2, MPW3) electrically isolated from each other, each having a floating electrical potential, and each comprising two memory cells. An integrated circuit according to claim 5, wherein the isolation trenches (STI) sever the conductive trenches (SGC ,,, + i) in a plurality of sections each forming a common vertical grid (SGC) of two selection transistors. (ST41, ST42) of two memory cells belonging to different mini boxes (MPW1, MPW2, MPW3). An integrated circuit according to claim 6, wherein the isolation trenches (STI) completely sever the conducting trenches (SGC ,,, + i) in a plurality of sections each forming a common vertical grid (SGC) of two memory cells, and comprising a metal word line (WL) extending above the substrate, which electrically connects the different sections. The integrated circuit of claim 7, wherein the conductive trenches (SGC ,, i + i) sever the isolation trenches (STI) in a plurality of sections. 9. An integrated circuit according to one of claims 5 to 8, wherein the insulating layer (NISO) forms a source line (SL) of the selection transistors (ST41, ST42) of the memory cells. 10. Integrated circuit according to one of claims 5 to 9, wherein the charge storage transistors (FGT41, FGT42) are floating gate transistors. 15 11. A method of writing memory cells in an integrated circuit according to one of claims 5 to 10, comprising a step of erasing a first memory cell (C41) implanted in a mini box (MPW1), wherein step of erasing comprises the steps of: - applying a negative erase voltage (Ver) to the control gate (CG) of the charge accumulation transistor (FGT41) of the first memory cell (C41), applying a positive voltage (BLV2) to the drain region (n1) of the charge accumulation transistor (FGT41) of the first memory cell, and - raising the electric potential (VB2) of the mini box by means of a current of blocked junction leakage passing through the drain region (n1), until the electric potential of the mini-well is positive less than or equal to the positive voltage (BLV2) applied to the drain region, and causes a charge transfer electric tuning effect between the charge-storage transistor and the mini-box. The method of claim 11, wherein the step of erasing the first memory cell (C41) is conducted without erasing a second memory cell (C42) implanted in the same mini-well (MPW1), and comprises a step of applying a positive non-erasing voltage (Vner) to the control gate (CG) of the charge accumulation transistor (FGT42) of the second memory cell (C42). 13. A method of writing memory cells in an integrated circuit according to one of claims 5 to 10, comprising a step of programming a first memory cell (C41) implanted in a mini box (MPW1), wherein the programming step comprises the steps of: - applying a positive programming voltage (Vprog) to the control gate (CG) of the charge storage transistor (FGT41) of the first memory cell (C41), - applying a negative voltage (BLV3) to the drain region (n1) of the charge storage transistor (FGT41) of the first memory cell, and - to decrease the electric potential (VB3) of the mini-well by means of a pass-through current passing through the drain region (n1), until the electric potential of the mini box is negative and greater than the negative voltage (BLV3) applied to the drain region, and results in an electric charge transfer by tunnel effect between the mini box and the charge storage transistor. 14. The method of claim 13, wherein the programming step of the first memory cell (C41) is conducted without programming a second memory cell (C42) located in the same mini box (MPW1), and comprises a step applying a negative non-erase voltage (Vnprog) to the control gate (CG) of the charge accumulation transistor (FGT42) of the second memory cell (C42).