EP0354804B1 - Superconductive transistor - Google Patents
Superconductive transistor Download PDFInfo
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- EP0354804B1 EP0354804B1 EP89308176A EP89308176A EP0354804B1 EP 0354804 B1 EP0354804 B1 EP 0354804B1 EP 89308176 A EP89308176 A EP 89308176A EP 89308176 A EP89308176 A EP 89308176A EP 0354804 B1 EP0354804 B1 EP 0354804B1
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- superconductor layer
- layer
- superconductive
- superconductor
- insulator film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/20—Permanent superconducting devices
- H10N60/205—Permanent superconducting devices having three or more electrodes, e.g. transistor-like structures
- H10N60/207—Field effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/85—Superconducting active materials
Definitions
- This invention relates to a superconductive transistor having a large capacity for electric current and utilizing the electric field effect.
- thyristors In the field of semiconductors, thyristors, GTO-thyristors, power transistors, power MOSFETs and similar devices are popularly used for quick switch of large electric currents.
- FIGs. 3 through 6 of the accompanying drawings show some examples of the devices that have been developed to meet these requirements.
- Fig. 3 shows a known device comprising an n-type semiconductor 11 made of n-InSb or n-InAs, on which a source electrode 12 and a drain electrode 13, both being made of an In showing superconductive properties, are juxtaposed with a space L, equal to the coherence length (e.g. 0.5 ⁇ m), provided therebetween, an A1 gate electrode 15 being provided below said semiconductor 11 with an insulating layer 14 inserted therebetween and said insulator 14 being made of SiO 2 or Si 3 N 4 , and an insulating layer 16 made of the same material as that of said insulating layer 14 being arranged between said semiconductor layer 11 and said juxtaposed electrodes 12 and 13 for electrically insulating them from each other.
- a space L equal to the coherence length (e.g. 0.5 ⁇ m)
- the source electrode 12 and the drain electrode 13 become active with zero resistance due to the proximity effect.
- the source electrode 12 as well as the drain electrode 13 are made inactive with high resistance by modifying the carrier density of the semiconductor between the source and drain electrodes 12, 13 and consequently modifying the coherence length.
- Fig. 4 shows a device, which is similar to that of Fig. 3 but comprises a gate electrode 15 arranged on the side of a semiconductor 11 where a source electrode 12 and a drain electrode 13 are provided.
- the device of Fig. 4 essentially functions in the same manner as the device of Fig. 3.
- Fig. 5 illustrates a device comprising a semiconductor 11, on which a superconductor layer 18 having a notch (notched portion 17) is placed, an upper electrode 20 being arranged on said notch 17 with an insulator layer provided therebetween and a lower electrode 21 being arranged under said semiconductor 11.
- the electric conductivity of the device can be controlled by the voltage applied to the upper and lower electrodes 20 and 21.
- Fig. 6 illustrates a device comprising an MgO dielectric layer 23 having a thickness of 10nm (100 ⁇ ), an In/InO x superconductor layer 24 having a thickness of 4nm (40 ⁇ ) and an A1 gate electrode 25 being formed respectively on and under said dielectric layer 23.
- the device of Fig. 6 is free from the requirement of a space equal to the coherence length between the superconductor members, since it does not utilize the proximity effect.
- the coherence length can be one-tenth to one-hundredth of that of a metal superconductor, requiring micropatterning that deals with less than 10nm (100 ⁇ ), a process which is by no means easy.
- the device illustrated in Fig. 6 resembles a field-effect transistor using a semiconductor and hence the charge density of the depletion region that can be injected into the superconductor layer should be roughly equivalent to the carrier density of the superconductor layer.
- This allows the use of only low carrier density superconductive materials such as In-InO x and by turn the critical temperature for the use of the superconductor layer will become inevitably very low.
- the requirement of low carrier density necessarily entails reduction of the critical current density of the superconductor layer, making the device incapable of switching large electric current.
- any attempt to increase the charge density of the depletion region of the device of Fig. 6 can result in break down of the insulator layer, reduction of applicable gate voltage, reduction of the charge injected into the depletion region and other unfavorable characteristics, because a low carrier density superconductive material such as In-InO x comprises a mixture of ⁇ -In and crystalline InO x and does not accept any high-quality insulator layer (dielectric layer) to be deposited thereon.
- a low carrier density superconductive material such as In-InO x comprises a mixture of ⁇ -In and crystalline InO x and does not accept any high-quality insulator layer (dielectric layer) to be deposited thereon.
- EP-A-0324044 discloses a superconductive transistor comprising a substrate, an oxide superconductor layer epitaxially grown on said substrate, a source electrode and a drain electrode disposed on said oxide superconductor layer, an insulator film grown on said oxide superconductor layer and located between said source and drain electrodes, and a gate electrode disposed on said insulator film, the thickness of the oxide superconductor layer being such that the superconductive channel can be completely depleted by applying a suitable gate voltage V being smaller than a critical voltage V f so as to avoid the formation of an inversion layer on the surface of the superconductor layer.
- the insulator film is grown by a chemical vapour deposition (CVD) process.
- the superconductive transistor in accordance with this invention is characterised in that the insulator film is epitaxially grown on said oxide superconductor layer.
- the electric current is normally controlled by electrostatically modifying the conductivity of the electric path by the third electrode(s) (gate electrodes).
- the conductivity of the super-conductor layer is modified by the electrode provided on the insulator film that covers the superconductor layer.
- the gate voltage applied to a superconductive transistor is actually divided into two portions; a portion of the voltage applied to the insulator film and the portion applied to the superconductor layer.
- the applied gate voltage V exceeds a critical voltage V f , an inversion layer is formed on the surface of the superconductor layer and an inversion charge (a thin layer of electrons) appears.
- the value V of the voltage applied to the gate should be kept smaller than the critical voltage value V f .
- the thickness d c of the superconductor layer should satisfy equation II below.
- a superconductive material having a low carrier density is used.
- the voltage V f of an oxide superconductor such as YBaCuO is approximately 3eV. If its dielectric constant is assumed to be 20 ⁇ o , its value that corresponds to that of perovskite crystal being similar to oxide superconductor crystal structure and its carrier density is 10 21 /cm 3 , d c will be less than 2.5nm (25 ⁇ ).
- d c can be doubled, if the relationship expressed by equation III below is met and a pair of gate electrodes are provided, respectively on and below the superconductor layer.
- a superconductive transistor according to the invention comprises an oxide superconductor layer having a high critical temperature and a low carrier density as well as a high critical current density and other desirable characteristics.
- the superconductive transistor according to an embodiment of the invention is realized in the form of a laminate of insulator layer-superconductor layer-insulator film, i.e. a three-layered planar structure, it can be prepared without micropatterning or fine precision fabrication processes.
- the superconductor layer will have a high critical current density. Moreover, it will exhibit a large breakdown voltage and a depletion region will be effectively generated because of clear interface between an insulator film and the superconductor layer.
- the net effect of such a structure is an oxide superconductor layer having an excellent electric field effect.
- the thickness of the superconductor layer should satisfy the above equations II and III in order for the superconductive transistor according to this invention to function as a switching device.
- the transistor Since the whole current transmitted by the superconductive transistor according to the invention is superconducting transport current, the transistor functions as a switch that can accommodate electric current far greater than the known devices as illustrated in Figs. 3 and 4.
- a lower gate 2 of n-type Si having a thickness of less then 1 ⁇ m is formed by ion implantation on the upper surface of a substrate 1 made of p-type Si.
- a buffer insulator layer 3 of MgAl 2 O 4 is epitaxially grown with a view to lattice matching.
- a lower gate insulator film 4 of SrTiO 3 is epitaxially grown on said buffer insulator layer 3.
- a superconductor film 5 of Y 1 Ba 2 Cu 3 O 6 . 8 is also epitaxially grown. Moreover, an upper gate insulator film 6 of SrTiO 3 is formed on said superconductor film 5.
- a source electrode 7a and a drain electrode 7b, both made of Ag, are formed on said superconductor film 5 as ohmic contacts and the clearance between these electrodes 7a and 7b provides a predetermined channel length.
- a gate electrode 8 is arranged on said upper gate insulator film 6.
- a sample superconductive transistor as illustrated in Fig. 1 was prepared in the following way.
- a lower gate 2 of n-type Si was formed on the upper surface of a p-type (100) Si substrate 1 up to a thickness of 0.25 ⁇ m using a P (phosphor) ion implant system.
- the energy of the injected P ion was 200kv and its dose was 10 15 ions/cm 2 .
- the temperature was maintained at 800°C for 30 minutes.
- a buffer insulator layer 3 of MgAl 2 O 4 was epitaxially grown on the p-type Si substrate 1, on which said lower gate 2 had been formed, by means of the CVD technique up to a thickness of 1.5nm (15 ⁇ ).
- the heating temperature was actually 840°C and the rate of supply of H 2 gas to be used as carrier of MgCl 2 gas was 2 liter/min.
- the natural oxide film that had been formed on said Si substrate was removed by using H 2 gas.
- a lower gate insulator film 4 of SrTiO 3 was epitaxially grown on the upper surface of the buffer insulator layer 3 up to a thickness of 20nm (200 ⁇ ).
- a superconductor film 5 of Y 1 Ba 2 Cu 3 O 6.8 was epitaxially grown on said lower gate insulator film 4 up to a thickness of 5nm (50 ⁇ ) by means of the pulsed LASER deposition technique.
- a piece of sintered Y 1 Ba 2 Cu 3 O 6.8 was used as target, while a KrF excimer LASER was used as a LASER source and the target was placed in an atmosphere of O 2 gas of 1.33 N/m 2 (100m Torr), said target being repeatedly irradiated by the LASER beam from said LASER source with a LASER pulse energy level of 0.2J/shot and the LASER power density of 4J/cm 2 at a rate of 10Hz to form said superconductor film 5 on the substrate which had been heated to 600 to 700°C.
- an upper gate insulator film 6 of SrTiO 3 with a thickness of 20nm (200 ⁇ ) was formed on said superconductor film 5 using the technique as described for the formation of the lower gate insulator film 4.
- a source electrode 7a and a drain electrode 7b made of Ag were ohmically contacted on said superconductor film 5 with a clearance or a channel length of 100 ⁇ m provided therebetween and a gate electrode 8 was arranged on the upper gate insulator film 6 conforming to a known technique.
- the superconductor film is made of a YBaCuO type material
- its thickness is required to be very small, or 2.5nm (25 ⁇ ) in the above example, making the allowable maximum current (critical current) very low.
- critical current critical current
- One way to bypass such problems is provision of a structure where the electric channel is sandwiched by an upper gate and a lower gate. With such an arrangement, the critical height of the channel can be doubled.
- the allowable maximum thickness of the superconductor layer 5 will be 5nm (50 ⁇ ).
- Fig. 2 is a graphic illustration of the characteristics at 77°K of a device prepared on the basis of the above-mentioned principle.
- Fig. 2 shows the relationship between source-to-drain voltage V D and drain current I D , using gate voltage V G as parameter.
- I D shows its maximum values when V G is nil and declines as the absolute value of V G increases in the negative sense, a phenomenon which obviously reveals the switching characteristics of the device.
- the switching speed of the device determined by the charging time of the gate capacity and the inductance of the superconductive channel, was approximately 30nsec, which is considerably shorter than that of a power semiconductor.
- the switching current of the device was 20A/cm, which is more than twenty times greater than that of a semiconductor power MOSFET device or 0.8A/cm. This means that the size of a device according to the present invention can be as small as one-twentieth of that of a MOSFET for switching electricity of same level.
- the superconductor layer of the above example is made of a YBaCuO type material
- a superconductive transistor comprising a superconductor layer made of a BsSrCaCuO-type material will show similar characteristics.
- the gate insulator film may be realized by using ZrO 2 or MgAl 2 O 4 with high dielectric constant and high break-down voltage, in place of SrTiO 3 .
- a superconductive transistor according to the present invention uses an established planar structure and known electrodes, the thickness of the superconductor layer can be made smaller than that of any conventional superconductor, allowing easy manufacture and handling of large current capacity. Moreover, since a superconductive transistor according to the present invention preferably comprises a pair of gate electrodes arranged respectively on and under the superconductor layer, the thickness of the superconductor layer may be increased to stabilize the performance of the transistor.
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Description
- This invention relates to a superconductive transistor having a large capacity for electric current and utilizing the electric field effect.
- In the field of semiconductors, thyristors, GTO-thyristors, power transistors, power MOSFETs and similar devices are popularly used for quick switch of large electric currents.
- While such devices as thyristors, GTO-thyristors and power transistors are available for currents up to 1KA, they are accompanied by the drawback of large electric loss or heat generation whenever they are activated. Besides, they are normally slow for switching, requiring some 30 µ seconds.
- On the other hand, although power MOSFETs are very quick, requiring only 0.1 µ second for switching, they show a large resistance when activated and hence can not be used for large currents, making themselves only good for electric currents up to several Amps.
- In the current trend of technological advancement, development of new switching devices are expected to accommodate large current, high speed switching, minimized loss of electrical power during use, complete shut-out of electric current once deactivated and other requirements.
- Figs. 3 through 6 of the accompanying drawings show some examples of the devices that have been developed to meet these requirements.
- Fig. 3 shows a known device comprising an n-
type semiconductor 11 made of n-InSb or n-InAs, on which asource electrode 12 and adrain electrode 13, both being made of an In showing superconductive properties, are juxtaposed with a space L, equal to the coherence length (e.g. 0.5µm), provided therebetween, anA1 gate electrode 15 being provided below saidsemiconductor 11 with aninsulating layer 14 inserted therebetween and saidinsulator 14 being made of SiO2 or Si3N4, and aninsulating layer 16 made of the same material as that of said insulatinglayer 14 being arranged between saidsemiconductor layer 11 and said juxtaposedelectrodes - With a device as illustrated in Fig. 3, when no voltage is applied to the
gate electrode 15, thesource electrode 12 and thedrain electrode 13 become active with zero resistance due to the proximity effect. On the other hand, when voltage is applied to thegate electrode 15, thesource electrode 12 as well as thedrain electrode 13 are made inactive with high resistance by modifying the carrier density of the semiconductor between the source anddrain electrodes - Fig. 4 shows a device, which is similar to that of Fig. 3 but comprises a
gate electrode 15 arranged on the side of asemiconductor 11 where asource electrode 12 and adrain electrode 13 are provided. - The device of Fig. 4 essentially functions in the same manner as the device of Fig. 3.
- Fig. 5 illustrates a device comprising a
semiconductor 11, on which asuperconductor layer 18 having a notch (notched portion 17) is placed, anupper electrode 20 being arranged on saidnotch 17 with an insulator layer provided therebetween and alower electrode 21 being arranged under saidsemiconductor 11. - With a device as illustrated in Fig. 5, since the superconductivity of the notched portion 17 (of the superconductor) is nullified under the influence of carrier density modulation of the semiconductor layer due to the proximity effect of a normal state into a superconducting state, the electric conductivity of the device can be controlled by the voltage applied to the upper and
lower electrodes - Fig. 6 illustrates a device comprising an MgO
dielectric layer 23 having a thickness of 10nm (100Å), an In/InOx superconductor layer 24 having a thickness of 4nm (40Å) and anA1 gate electrode 25 being formed respectively on and under saiddielectric layer 23. - Contrary to the devices of Figs. 3 through 5, the device of Fig. 6 is free from the requirement of a space equal to the coherence length between the superconductor members, since it does not utilize the proximity effect.
- The above described known devices are still on the way of technological development and accompanied by the following problems to be solved.
- While the devices of Figs. 3 through 5 have a quick On/Off function, they can not cope with a large electric current, since the current to be controlled by these devices is either the tunnel current or the Josephson current.
- Apart from this, the superconductor members of each of the devices have to be separated by the coherence length and therefore preparation of such a device requires fine precision etching and fabrication processes.
- It should be noted when an oxide superconductor is involved, the coherence length can be one-tenth to one-hundredth of that of a metal superconductor, requiring micropatterning that deals with less than 10nm (100Å), a process which is by no means easy.
- In principle, the device illustrated in Fig. 6 resembles a field-effect transistor using a semiconductor and hence the charge density of the depletion region that can be injected into the superconductor layer should be roughly equivalent to the carrier density of the superconductor layer. This allows the use of only low carrier density superconductive materials such as In-InOx and by turn the critical temperature for the use of the superconductor layer will become inevitably very low.
- In other words, the maximum temperature at which the device normally functions will become very low, probably lower than the temperature of liquid helium (4.2°K), making the device practically infeasible.
- Moreover, the requirement of low carrier density necessarily entails reduction of the critical current density of the superconductor layer, making the device incapable of switching large electric current.
- Any attempt to increase the charge density of the depletion region of the device of Fig. 6 can result in break down of the insulator layer, reduction of applicable gate voltage, reduction of the charge injected into the depletion region and other unfavorable characteristics, because a low carrier density superconductive material such as In-InOx comprises a mixture of α-In and crystalline InOx and does not accept any high-quality insulator layer (dielectric layer) to be deposited thereon.
- EP-A-0324044 discloses a superconductive transistor comprising a substrate, an oxide superconductor layer epitaxially grown on said substrate, a source electrode and a drain electrode disposed on said oxide superconductor layer, an insulator film grown on said oxide superconductor layer and located between said source and drain electrodes, and a gate electrode disposed on said insulator film, the thickness of the oxide superconductor layer being such that the superconductive channel can be completely depleted by applying a suitable gate voltage V being smaller than a critical voltage Vf so as to avoid the formation of an inversion layer on the surface of the superconductor layer.
- The insulator film is grown by a chemical vapour deposition (CVD) process.
- It is an object of the present invention to provide a superconductive transistor of the above-mentioned type having a large capacity for electric current and utilizing the electric field effect for directly controlling majority carriers in the superconductor channel instead of controlling minority carriers due to the Josephson effect and proximity effect, and allowing an easy fabrication process.
- Thus, the superconductive transistor in accordance with this invention is characterised in that the insulator film is epitaxially grown on said oxide superconductor layer.
- With a conventional field-effect transistor, the electric current is normally controlled by electrostatically modifying the conductivity of the electric path by the third electrode(s) (gate electrodes). Contrary to this, with a superconductive transistor according to this invention, the conductivity of the super-conductor layer is modified by the electrode provided on the insulator film that covers the superconductor layer.
- In order to make this arrangement feasible, conditions under which a depletion region is formed in the superconductor layer, through utilization of the field effect, should be determined. Now how to determine these conditions will be described below.
- The gate voltage applied to a superconductive transistor is actually divided into two portions; a portion of the voltage applied to the insulator film and the portion applied to the superconductor layer.
-
- If the applied gate voltage V exceeds a critical voltage Vf, an inversion layer is formed on the surface of the superconductor layer and an inversion charge (a thin layer of electrons) appears. To avoid this phenomenon, the value V of the voltage applied to the gate should be kept smaller than the critical voltage value Vf.
-
- For reference, the voltage Vf of an oxide superconductor such as YBaCuO is approximately 3eV. If its dielectric constant is assumed to be 20εo, its value that corresponds to that of perovskite crystal being similar to oxide superconductor crystal structure and its carrier density is 1021/cm3, dc will be less than 2.5nm (25Å).
-
- A superconductive transistor according to the invention comprises an oxide superconductor layer having a high critical temperature and a low carrier density as well as a high critical current density and other desirable characteristics.
- Because the superconductive transistor according to an embodiment of the invention is realized in the form of a laminate of insulator layer-superconductor layer-insulator film, i.e. a three-layered planar structure, it can be prepared without micropatterning or fine precision fabrication processes.
- Because the three-layered structure is epitaxially grown, the superconductor layer will have a high critical current density. Moreover, it will exhibit a large breakdown voltage and a depletion region will be effectively generated because of clear interface between an insulator film and the superconductor layer.
- The net effect of such a structure is an oxide superconductor layer having an excellent electric field effect.
- It should be emphasized that the thickness of the superconductor layer should satisfy the above equations II and III in order for the superconductive transistor according to this invention to function as a switching device.
- Since the whole current transmitted by the superconductive transistor according to the invention is superconducting transport current, the transistor functions as a switch that can accommodate electric current far greater than the known devices as illustrated in Figs. 3 and 4.
- Now the present invention will be described in greater detail by referring to a preferred embodiment of the invention.
-
- Fig. 1 is a sectional view of an embodiment of the invention,
- Fig. 2 is a graphic illustration showing the characteristics of the embodiment of Fig. 1, and
- Figs. 3 through 6 are sectional views of so many different known superconductive transistors.
- Referring to Fig. 1 which illustrates a sectional view of an embodiment of the invention, a
lower gate 2 of n-type Si having a thickness of less then 1µm is formed by ion implantation on the upper surface of asubstrate 1 made of p-type Si. - On the upper surface of said p-
type Si substrate 1, on which saidlower gate 2 is arranged, abuffer insulator layer 3 of MgAl2O4 is epitaxially grown with a view to lattice matching. A lower gate insulator film 4 of SrTiO3 is epitaxially grown on saidbuffer insulator layer 3. - On said lower gate insulator film 4, a
superconductor film 5 of Y1Ba2Cu3O6.8 is also epitaxially grown. Moreover, an uppergate insulator film 6 of SrTiO3 is formed on saidsuperconductor film 5. - A
source electrode 7a and adrain electrode 7b, both made of Ag, are formed on saidsuperconductor film 5 as ohmic contacts and the clearance between theseelectrodes - A
gate electrode 8 is arranged on said uppergate insulator film 6. - A sample superconductive transistor as illustrated in Fig. 1 was prepared in the following way.
- To begin with, a
lower gate 2 of n-type Si was formed on the upper surface of a p-type (100)Si substrate 1 up to a thickness of 0.25µm using a P (phosphor) ion implant system. - The energy of the injected P ion was 200kv and its dose was 1015 ions/cm2. For annealing, the temperature was maintained at 800°C for 30 minutes.
- Then, a
buffer insulator layer 3 of MgAl2O4 was epitaxially grown on the p-type Si substrate 1, on which saidlower gate 2 had been formed, by means of the CVD technique up to a thickness of 1.5nm (15Å). - During this process, in which aluminum (Al) was heated to 600 to 700°C to react with HCl gas to produce AlCl3 gas, the actual temperature of the aluminum was 650°C. HCl gas was supplied at the rate of 2cc/min, while carrier gas H2 was fed at the rate of 0.5 liter/min.
- Thereafter, solid MgCl2 was heated to 800 to 900°C for gasification, the obtained MgCl2 gas being used as source gas.
- The heating temperature was actually 840°C and the rate of supply of H2 gas to be used as carrier of MgCl2 gas was 2 liter/min.
- Then using H2 gas as carrier, gaseous AlCl2 and MgCl2 were brought onto said
Si substrate 1, which had been heated to 920°C. At the same time, CO2 gas, fed at the rate of 2 to 10cc/min, was supplied onto the heated substrates at the rate of 3cc/min to epitaxially grow a MgAl2O4 film 3 on saidSi substrate 1 according to the following formula; - Prior to the formation said film, the natural oxide film that had been formed on said Si substrate was removed by using H2 gas.
- Thereafter, a lower gate insulator film 4 of SrTiO3 was epitaxially grown on the upper surface of the
buffer insulator layer 3 up to a thickness of 20nm (200Å). - The expitaxial growth of said film 4 was conducted under the condition of gas pressure of 13.3 N/m2 (10m Torr) and substrate temperature of 550°C and in the atmosphere of Ar:O2=4:1 by means of RF magnetron sputtering, using a sintered SrTiO3 piece as target.
- Then a
superconductor film 5 of Y1Ba2Cu3O6.8 was epitaxially grown on said lower gate insulator film 4 up to a thickness of 5nm (50Å) by means of the pulsed LASER deposition technique. - More specifically, a piece of sintered Y1Ba2Cu3O6.8 was used as target, while a KrF excimer LASER was used as a LASER source and the target was placed in an atmosphere of O2 gas of 1.33 N/m2 (100m Torr), said target being repeatedly irradiated by the LASER beam from said LASER source with a LASER pulse energy level of 0.2J/shot and the LASER power density of 4J/cm2 at a rate of 10Hz to form said
superconductor film 5 on the substrate which had been heated to 600 to 700°C. - For reference, a thin film of YBCO formed to the thickness of 5nm (50Å) on a substrate made of single crystal SrTiO3 will have the characteristics of Tco=81K and JC=105A/cm2 (at 77K).
- Then, an upper
gate insulator film 6 of SrTiO3 with a thickness of 20nm (200Å) was formed on saidsuperconductor film 5 using the technique as described for the formation of the lower gate insulator film 4. - Finally, a
source electrode 7a and adrain electrode 7b made of Ag were ohmically contacted on saidsuperconductor film 5 with a clearance or a channel length of 100µm provided therebetween and agate electrode 8 was arranged on the uppergate insulator film 6 conforming to a known technique. - The expected epitaxial growth of the films of the above described sample was verified by X-ray analysis and RHEED patterns.
- It should be noted that there are restrictions to the thickness of the superconductor layer for a device having a configuration as described above to function as a superconductive transistor.
- For instance, when the superconductor film is made of a YBaCuO type material, its thickness is required to be very small, or 2.5nm (25Å) in the above example, making the allowable maximum current (critical current) very low. With such an epitaxial film, the quality of the crystals is often required to meet rigorous standards.
- One way to bypass such problems is provision of a structure where the electric channel is sandwiched by an upper gate and a lower gate. With such an arrangement, the critical height of the channel can be doubled.
- If the
superconductor layer 5 is made of a YBaCuO material, for example, the allowable maximum thickness of thesuperconductor layer 5 will be 5nm (50Å). - Fig. 2 is a graphic illustration of the characteristics at 77°K of a device prepared on the basis of the above-mentioned principle.
- More specifically, Fig. 2 shows the relationship between source-to-drain voltage VD and drain current ID, using gate voltage VG as parameter.
- As is apparent from Fig. 2, ID shows its maximum values when VG is nil and declines as the absolute value of VG increases in the negative sense, a phenomenon which obviously reveals the switching characteristics of the device.
- Some of the results of measurement of the response speed of the device prepared as described above will be shown below.
- When the load transistor in the latter stage was driven by the drain current of the driving transistor in the former stage, the switching speed of the device, determined by the charging time of the gate capacity and the inductance of the superconductive channel, was approximately 30nsec, which is considerably shorter than that of a power semiconductor.
- The switching current of the device was 20A/cm, which is more than twenty times greater than that of a semiconductor power MOSFET device or 0.8A/cm. This means that the size of a device according to the present invention can be as small as one-twentieth of that of a MOSFET for switching electricity of same level.
- While the superconductor layer of the above example is made of a YBaCuO type material, a superconductive transistor comprising a superconductor layer made of a BsSrCaCuO-type material will show similar characteristics.
- While the Si substrate can be replaced by a GaAs substrate or an InP substrate, the gate insulator film may be realized by using ZrO2 or MgAl2O4 with high dielectric constant and high break-down voltage, in place of SrTiO3.
- As is apparent from the above description, while a superconductive transistor according to the present invention uses an established planar structure and known electrodes, the thickness of the superconductor layer can be made smaller than that of any conventional superconductor, allowing easy manufacture and handling of large current capacity. Moreover, since a superconductive transistor according to the present invention preferably comprises a pair of gate electrodes arranged respectively on and under the superconductor layer, the thickness of the superconductor layer may be increased to stabilize the performance of the transistor.
Claims (2)
- A superconductive transistor comprising a substrate (1), an oxide superconductor layer (5) epitaxially grown on said substrate, a source electrode (7a) and a drain electrode (7b) disposed on said oxide superconductor layer (5), an insulator film (6) grown on said oxide superconductor layer (5) and located between said source and drain electrodes (7a,7b), and a gate electrode (8) disposed on said insulator film (6), the thickness of the oxide superconductor layer (5) being such that the superconductive channel can be completely depleted by applying a suitable gate voltage V being smaller than a critical voltage Vf so as to avoid the formation of an inversion layer on the surface of the superconductor layer (5), characterised in that the insulator film (6) is epitaxially grown on said oxide superconductor layer (5).
- A superconductive transistor as claimed in claim 1, characterised in that it further comprises a lower insulator film (4) epitaxially grown on said substrate (1) and having said oxide superconductor layer (5) epitaxially grown thereon, and a lower gate electrode (2) located under said lower insulator film (4) and opposite the first-mentioned gate electrode (8).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20047588 | 1988-08-11 | ||
JP200475/88 | 1988-08-11 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0354804A2 EP0354804A2 (en) | 1990-02-14 |
EP0354804A3 EP0354804A3 (en) | 1990-07-18 |
EP0354804B1 true EP0354804B1 (en) | 1997-04-02 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP89308176A Expired - Lifetime EP0354804B1 (en) | 1988-08-11 | 1989-08-11 | Superconductive transistor |
Country Status (5)
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EP (1) | EP0354804B1 (en) |
JP (1) | JP2862137B2 (en) |
KR (1) | KR940001296B1 (en) |
CN (1) | CN1040463A (en) |
DE (1) | DE68927925T2 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0477063B1 (en) * | 1990-09-06 | 1996-12-04 | Sumitomo Electric Industries, Ltd. | Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same |
EP0475838B1 (en) * | 1990-09-10 | 1996-03-06 | Sumitomo Electric Industries, Ltd. | Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same |
CA2051778C (en) * | 1990-09-19 | 1997-05-06 | Takao Nakamura | Method for manufacturing superconducting device having a reduced thickness of oxide superconducting layer and superconducting device manufactured thereby |
CA2052379C (en) * | 1990-09-27 | 1997-01-07 | Takao Nakamura | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material |
EP0478464B1 (en) * | 1990-09-27 | 1997-08-27 | Sumitomo Electric Industries, Ltd. | Method for manufacturing a superconducting device having an extremely thin superconducting channel formed of oxide superconductor material |
CA2052970C (en) * | 1990-10-08 | 1996-07-02 | Takao Nakamura | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same |
CA2054470C (en) * | 1990-10-30 | 1997-07-01 | Takao Nakamura | Method for manufacturing superconducting device having a reduced thickness of oxide superconducting layer and superconducting device manufactured thereby |
CA2054644C (en) * | 1990-10-31 | 1998-03-31 | Takao Nakamura | Superconducting device having an extremely short superconducting channel formed of extremely thin oxide superconductor film and method for manufacturing same |
CA2054795C (en) * | 1990-11-01 | 1996-08-06 | Hiroshi Inada | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same |
DE69132972T2 (en) * | 1991-01-07 | 2003-03-13 | Ibm | Superconducting field effect transistor with inverse MISFET structure and method for its production |
EP0523275B1 (en) * | 1991-07-19 | 1996-02-28 | International Business Machines Corporation | Enhanced superconducting field-effect transistor with inverted MISFET structure and method for making the same |
EP0523279A1 (en) * | 1991-07-19 | 1993-01-20 | International Business Machines Corporation | Electric field-effect devices having a superconducting channel |
DE69210150T2 (en) * | 1991-08-26 | 1996-10-31 | Sumitomo Electric Industries | Superconducting device with extremely thin superconducting channel made of oxide superconducting material and process for its production |
CA2077047C (en) * | 1991-08-28 | 1998-02-10 | So Tanaka | Method for manufacturing superconducting thin film formed of oxide superconductor having non superconducting region in it, method for manufacturing superconducting device utilizing the superconducting thin film and superconducting thin film manufactured thereby |
US5828079A (en) * | 1992-06-29 | 1998-10-27 | Matsushita Electric Industrial Co., Ltd. | Field-effect type superconducting device including bi-base oxide compound containing copper |
JPH0745880A (en) * | 1993-07-29 | 1995-02-14 | Sumitomo Electric Ind Ltd | Laminated film of insulator thin film and oxide superconducting thin film |
CA2153189A1 (en) * | 1994-07-04 | 1996-01-05 | Takao Nakamura | Superconducting device having a superconducting channel formed of oxide superconductor material |
KR101234870B1 (en) * | 2011-05-23 | 2013-02-19 | 한국과학기술원 | Transistor using semiconductor-superconductor transition materials |
Citations (1)
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EP0324044A1 (en) * | 1988-01-15 | 1989-07-19 | International Business Machines Corporation | A field-effect device with a superconducting channel |
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JPS6288381A (en) * | 1985-10-11 | 1987-04-22 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Superconducting switching apparatus |
AU597951B2 (en) * | 1986-03-27 | 1990-06-14 | Monsanto Company | Enhanced protein production in bacteria by employing a novel ribosome binding site |
JP2654567B2 (en) * | 1987-03-17 | 1997-09-17 | 株式会社 半導体エネルギー研究所 | Operation method of superconducting element |
-
1989
- 1989-07-26 JP JP1193102A patent/JP2862137B2/en not_active Expired - Lifetime
- 1989-08-11 KR KR1019890011466A patent/KR940001296B1/en not_active IP Right Cessation
- 1989-08-11 CN CN89106453A patent/CN1040463A/en active Pending
- 1989-08-11 DE DE68927925T patent/DE68927925T2/en not_active Expired - Fee Related
- 1989-08-11 EP EP89308176A patent/EP0354804B1/en not_active Expired - Lifetime
Patent Citations (1)
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EP0324044A1 (en) * | 1988-01-15 | 1989-07-19 | International Business Machines Corporation | A field-effect device with a superconducting channel |
Non-Patent Citations (2)
Title |
---|
Phys.Rev.Lett., Vol.59(17), 26 October 1987, pp. 1958-1961; Z.Schlesinger et al.: "Superconducting Energy gap and Normal-State Reflectivity of Single Crystal Y-Ba-Cu-O" * |
Solid State Physics, by N.W.Ashcroft and N.D.Mermin; New York 1976, Holt, Rinehart and Winston; pp. 551 and 744 * |
Also Published As
Publication number | Publication date |
---|---|
EP0354804A2 (en) | 1990-02-14 |
JP2862137B2 (en) | 1999-02-24 |
JPH02138780A (en) | 1990-05-28 |
KR900004048A (en) | 1990-03-27 |
DE68927925T2 (en) | 1997-07-17 |
KR940001296B1 (en) | 1994-02-18 |
CN1040463A (en) | 1990-03-14 |
DE68927925D1 (en) | 1997-05-07 |
EP0354804A3 (en) | 1990-07-18 |
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