EP0337752B1

EP0337752B1 - Graphic display system for cutting out partial image

Info

Publication number: EP0337752B1
Application number: EP89303602A
Authority: EP
Inventors: Yutaka Aoki; Kazunori Takayanagi
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1988-04-15
Filing date: 1989-04-12
Publication date: 1995-01-04
Anticipated expiration: 2009-04-12
Also published as: DE68920353T2; EP0337752A3; EP0337752A2; BR8901475A; CN1011092B; KR930004023B1; KR890016434A; DE68920353D1; CN1037975A; JPH01270176A

Description

This invention relates to a graphic display system and more particularly, to a graphic display system capable of cutting out any desired partial image.
In the field of image processing including graphics, an operation such cut-and-past is frequently performed by specifying a partial image on a screen of a display (especially, a colour display). Conventionally, the partial image has been cut out by using software or a dedicated hardware. For example, European Patent Application published under No. EP-A- 0 172 368 assigned to the same assignee as the present invention discloses a software technique in which a partial image is cut out and displayed at a different place on a screen with an enlarged scale. IBM Technical Disclosure Bulletin, Vol. 24, No. 4, pp. 1778-1782, published in September 1981, discloses a technique for cutting out a partial image with dedicated AND gates.
IBM Technical Disclosure Bulletin, Vol. 28, No. 6, 11/85, pp 2721-2724, published in November 1985, discloses a system for making Bit-blt (Bit-Boundary Block Transfer) copy operations of arbitrary shapes within a frame buffer. The disclosed system uses mask data in form of ones and zeros contained in one or more planes of the frame buffer, so a large amount of mask data is required for storing the shapes in the frame buffer.
If a partial image is cut out with software, there is a limitation in improvement of its speed. On the other hand if it is performed with dedicated hardware, high speed processing is possible, but there is a lack of expandibility and flexibility because its functions are fixed. In addition, it is expensive because additional hardware is provided and, in general, a more efficient operation is desirable.
It is therefore an object of the invention as claimed to provide a more efficient graphic display system.
Another object of the invention as claimed is to allow any desired partial image to be cut out by utilizing a raster operation function that an ordinary display system has.

Summary of the Invention

The graphic display system capable of cutting a partial image according to the invention is as disclosed in claim 1.
The image storage means is an all point addressable (APA) memory in which an source image storage area for storing the source image, a work storage area for storing a dot pattern representing the outline, and a destination storage area for storing the partial image are allocated. The mask data generator means generates mask data, whereby a region enclosed with the outline dot pattern is put in the non-masked state, while the rest is put in the masked state. The partial image write means may write the partial image and predetermined pattern data into the destination storage area by combining them.
In order that the invention may be fully understood a preferred embodiment thereof will now be described with reference to the accompanying drawings in which:
Figure 1 is a block diagram illustrating an embodiment of the graphic display system according to the invention.
Figure 2 is a block diagram illustrating the contents of the APA memory 10.
Figure 3 is a circuit diagram illustrating an example of the mask data generator 14.
Referring to Figure 1, there is illustrated a configuration of a graphic display system according to the invention. The system comprises an APA memory 10 for storing a source image from which a partial image is cut out, an outline drawing unit 12 for drawing an outline of the partial image to be cut out, a mask data generator 14 for generating mask data based on the outline data drawn by the outline drawing unit 12, a bit operation circuit 16 that allows bit-by-bit operations on the image data read from the APA memory 10, a raster operation circuit 18, a multiplexer (MUX) 20 for selecting either the mask data from the mask data generator 14 or the image data from the raster operation circuit 18 and supplying it to data input terminals of the APA memory 10, a video circuit 22 for converting the image data read from the APA memory 10 into signals for display, a display unit 24 for providing a visual display by the signals from the video circuit 22, and a controller 26 for controlling the entire system. Although the invention can be applied to either a colour display system or a monochrome display system, the colour display system in which a pixel consists of n bits (for example, n = 4) will be described below by way of example.
As is well known, in the colour display system, the APA memory 10 consists of n memory planes. Each pixel data of n bits read from the APA memory 10 is converted into colour data of m bits (for example, m = 6) representing an actual display colour by a palette circuit provided in the video circuit 22, and supplied to the display unit 24 after digital-analog conversion.
Now, referring to Figure 2, the cutting out of the partial image that is executed by the graphic display system of Figure 1 is described. Figure 2 illustrates the contents of the APA memory 10 which contains a source image storage area 10A, a work storage area 10B for drawing the outline of the partial image to be cut out, and a destination storage area 10C to which the cut out partial image is transferred. These storage areas 10A - 10C are of the same size. The APA memory 10 may further contain pattern data 10D and 10E. These pattern data are combined with the source image data in the raster operation circuit 18.
When it is desired to cut out a partial image, the user first uses the outline drawing unit 12 to draw an outline (for example, a circle) defining a partial image that the user wants to cut out from a source image stored in the storage area 10A. The outline drawing unit 12 may be a hardware drawing facility that is usually provided in the graphic display system. European Patent Application published under No. EP-A- 0 201 754 assigned to the same assignee as the present invention discloses a technique for drawing a quadratic curve including a circle by using such a hardware drawing facility. If it is desired to interactively draw the outline while viewing the screen of the display 24, a mouse may be used as the outline drawing unit 12. In any case, the dot pattern 11 representing the outline drawn by the outline drawing unit 12 is written in the work storage area 10B. The location of the outline dot pattern 11 in the work storage area 10B corresponds to that of the partial image 11′ in the source image storage area 10A. In this embodiment, one dot consists of n bits, but as far as the outline dot is concerned, it may be a single bit. In that case, the outline dots are written in a selected one of the n memory planes. In case where one dot consists of n bits, it is sufficient to assign a specific colour code of n bits to the outline dot.
The outline dot pattern 11 written in the work storage area 10B has an even number of outline dots per line when it is viewed laterally. For example, in a case of a circle, it is easily recognised that the number of dots turned on is two per line except for the upper and lower ends. At the upper and lower ends, writing is performed in the work storage area 10B so that two adjacent or close dots are turned on. Although two or more adjacent dots may be turned on to approximate a curve in an ordinary drawing facility, only the outermost dot is turned on when the outline of the partial image is drawn. This satisfies a condition to make the number of outline dots per line even. This condition is required to distinguish on each line the start and end points of a region enclosed with the outline. In this embodiment, an even-numbered dot including No. 0 represents the start point while an odd-numbered dot represents the end point.
After the writing of the outline dot pattern is completed, the contents of the work storage area 10B in the APA memory 10 are read out to the mask data generator 14 under control of the controller 26. It is assumed here that a unit of access for the APA memory 10 is one word (16 bits). The controller 26 reads the words one by one beginning from the address at the upper left corner of the work storage area 10B or its start address, and supplies it to the mask data generator 14. The mask data generator 14 checks whether the read word contains the even- or odd-numbered outline dot. Then, it generates mask data that put on each line a region from the even- numbered outline dot to the next odd-numbered one in the non-masked state, and the rest in the masked state.
Figure 3 shows an illustrative configuration of the mask data generator 14. In the example shown, the mask data generator 14 consists of 16 exclusive OR gates 30-i (i = 0, 1, ... 15) and a latch 32. The exclusive OR gates 30-i are cascade connected in which the output of each gate becomes the input of the next gate. The output of the last exclusive OR gate 30-15 is fed to the first exclusive OR gate 30-0 through the latch 32. The second input of each gate is supplied with a corresponding bit B0 - B15 in a word read from the work storage area 10B. Outputs M0 - M15 of the exclusive OR gates 30-i form a word of mask data.
When the mask data generator 14 is to be operated, the latch 32 is first cleared prior to the operation. In a situation where the work storage area 10B is not read, the mask data bits M0 - M15 are all 0's because B0 - B15 and Q output of the latch 32 are all 0's. This condition is maintained as long as the 16 bits B0 - B15 of each word read from the work storage area 10B are all 0's. Now, it is assumed that a read word contains the first or number 0 outline dot. Then, a corresponding bit Bi is 1 so that the output Mi of the exclusive OR gate 30-i, which receives it as its input, becomes 1. Because the output Mi is fed to the next exclusive OR gate 30-(i+1), its output Mi+1 also becomes 1 as long as its second input Bi+1 is not 1, that is, the next odd-numbered outline dot is not contained. Similarly, up to the last exclusive OR gate 30-15, as long as the next odd-numbered outline dot is not contained, the mask data with Mi-M15 being all 1's is generated. When writing to the APA memory 10 using the mask data, which will be described later, is completed, an enable signal is generated and applied to a clock input C of the latch 32. This sets the latch 32 which then supplies the Q output of 1 to the first exclusive OR gate 30-0. This is to maintain the previous state in preparation for the next word reading. Under this condition, even if an all 0 word is read next, an all 1 mask data is generated.
If a word containing an even-numbered outline dot or its subsequent word contains the next odd-numbered outline dot, the output Mj of the exclusive OR gate 30-j which receives a corresponding 1 bit at Bj, becomes 0 because another input from the previous stage is also 1.
Thus, as long as the same word does not contain the next even- numbered outline dot, a mask data with Mj to M15 being all 0's is generated. When M15 becomes 0, the latch 32 is reset and its Q output being 0 is supplied to the first exclusive OR gate. Under such a condition, 0 mask bits are generated until an even-numbered outline dot is next detected.
As clearly seen from the above, the mask data generator 14 generates 0 mask bits which represent the masked state, for the outside of the outline dot pattern 11 written in the work storage area 10B, and 1 mask bits which represent the non-masked state, for the inside of the outline dot pattern 11. A word of mask data M0 - M15 from the mask data generator 14 is supplied to the data input terminals of the APA memory 10 through the multiplexer 20 and the bus 28.
In this embodiment, the APA memory 10 is a dynamic RAM having write per bit capability, in which only a data input terminal receiving a 1 mask bit can perform writing. Whenever a mask data word is generated, the controller 26 reads a corresponding image data word of 16 bits from the source image storage area 10A and supplies it to the bit operation circuit 16. The bit operation circuit 16 is a hardware facility which allows a bit boundary transfer for the image data from the APA memory 10 which is accessed only at a word boundary. Such hardware is well known in the bit block transfer technique (generally called BitBlt), detailed description of which is omitted.
The image data from the bit operation circuit 16 is entered into the raster operation circuit 18. The raster operation circuit 18 performs a specific logic operation on the image data read from the APA memory 10 and other image data (such as a predetermined pattern data), and supplies its result to the multiplexer 20. A logic operation such as pass (allowing a selected image data to pass through as it is), AND, OR or exclusive OR is specified by the controller 26. Thus, a partial image can be cut out from the source image as it is without any change, or in an overlapped manner with a desired pattern. Examples of such a raster operation circuit are disclosed in European Patent Application published under No. EP-A- 0 241 655 assigned to the same assignee as the present invention, and IBM Technical Disclosure Bulletin, Vol. 27, No. 7A, pp. 4019 - 4020, December 1984.
The image data word from the raster operation circuit 18 is supplied to the data input terminals of the APA memory 10 through the multiplexer 20 and the bus 28. At that moment, the controller 26 sends a write command and an appropriate address of the destination storage area 10C to the APA memory 10. Thus, writing of the image data is performed at the data input terminals that have received the 1 mask bits representing the non-masked state.
The above operation is repeated until the last word in each storage area is reached in the order of (1) reading one word from the work storage area 10B, (2) generating a mask data, (3) reading a corresponding image data word from the source image storage area 10A, and (4) writing non-masked image data bits into the destination storage area 10C. When this is completed, the destination storage area 10C has been written with the partial image cut out from the source image.
Although, in the embodiments heretofore described, the work storage area 10B of the APA memory 10 is provided separately from the source image storage area 10A and the destination storage area 10B, it may be allocated the same area as either one of them. It is noted, however, if the work storage area 10B is allocated the same area as the source image storage area 10A, it is necessary to use a colour code not used in the source image for the outline dots because the outline dots are represented by a colour code of n bits. In case of a monochrome system, the work storage area 10B cannot be the same as the original image storage area 10A.
Also, in the above-mentioned embodiments, the outline of the partial image is a circle, but any desired outline such as an ellipse, rectangle or doughnut shape may be drawn. However, in case of the rectangle, dots of upper and lower horizontal sides are not written in the work storage area 10B. Generated for the upper side are mask data that put a region between the uppermost ends of the left and right sides in the non-masked state, and for the lower side are mask data that put a region between the lowermost ends of the left and right sides in the non- masked state.

Claims

A graphic display system including storage means (10) having a source storage area (10A) for storing source image data representing an image to be displayed on a screen (24), a work storage area (10B) containing outline data defining a portion (11′) of said image, and a destination storage area (10C) for storing partial image data representing said portion (11′) and partial image writing means (16, 18, 20, 26) for reading source image data in the source storage area (10A) and writing partial image data representing said portion (11′) of said image into the destination storage area (10C), characterized in that it includes an outline drawing device (12) for drawing an outline (11) of said portion (11′) of said image; said work storage area (10B) in the storage means (10) stores outline data representing said outline (11) as determined by input signals of the outline drawing device (12); a mask data generator (14) reads the outline data stored in the work storage area (10B) and generates mask data indicating by masked and non masked states whether the locations of the source image are within the outline and represent the area of said portion (11′) of said image, and in that said partial image writing means (16, 18, 20, 26) write into the destination storage area (10C) only those source image data from the source storage area (10A) that are indicated by said mask data as being included within the area of said portion (11′) of said image.
A graphic display system as claimed in claim 1 wherein said system includes a raster driven display screen (24) and the outline data representing said outline (11) in said work storage area (10B) contain an even number of data per raster line.
A graphic display system as claimed in claim 2, wherein said storage means (10) include pattern data area (10D, 10E) and said partial image writing means (16, 18, 20, 26) include means for reading data in said pattern data area (10D, 10E) and a raster operation circuit (18) which logically combines data from said pattern data area (10D, 10E) with data to be written into said destination storage area (10C).
A graphic display system as claimed in any one of claims 1, 2 or 3 wherein said source storage area (10A) is also used as said work storage area (10B).
A graphic display system as claimed in any one of claims 1, 2, 3, or 4 wherein said destination storage area (10C) is also used as said work storage area (10B).