EP0320555A1 - Famille étendue de circuits logiques du type commutateur de courant cascode (CSC) - Google Patents

Famille étendue de circuits logiques du type commutateur de courant cascode (CSC) Download PDF

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Publication number
EP0320555A1
EP0320555A1 EP87480023A EP87480023A EP0320555A1 EP 0320555 A1 EP0320555 A1 EP 0320555A1 EP 87480023 A EP87480023 A EP 87480023A EP 87480023 A EP87480023 A EP 87480023A EP 0320555 A1 EP0320555 A1 EP 0320555A1
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EP
European Patent Office
Prior art keywords
logic
output
level
cascode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87480023A
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German (de)
English (en)
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EP0320555B1 (fr
Inventor
Bruno Caplier
Jean-Paul Rousseau
Hervé Beranger
Armand Brunin
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International Business Machines Corp
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International Business Machines Corp
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Priority to DE3751365T priority Critical patent/DE3751365T2/de
Priority to EP87480023A priority patent/EP0320555B1/fr
Priority to JP63291120A priority patent/JP2580289B2/ja
Priority to US07/275,860 priority patent/US4942316A/en
Publication of EP0320555A1 publication Critical patent/EP0320555A1/fr
Application granted granted Critical
Publication of EP0320555B1 publication Critical patent/EP0320555B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H03K19/0866—Stacked emitter coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1738—Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the master-slave type

Definitions

  • the present invention relates generally to logic circuit networks and more particularly to powerful combinational 2 N high cascoding logic tree net- N orks with embedded supplemental logic functions capable of processing complex Boolean logic functions.
  • the cascode logic family is derived from the N ell known Emitter Coupled Logic (ECL) family, which is characterized by a systematic usage of non saturated transistors, which, in turn, results in astonishing high speed performances.
  • ECL Emitter Coupled Logic
  • the cascode logic technology is the VLSI ideal candidate for being implemented in high end computers. First of all, it has potentially superior power-performance attributes compared to other logic circuit technologies. Secondly, this technology may be integrated in low cost bipolar chips compatible with a CMOS environment. However, it has also some drawbacks which have prevented it from becoming a generalized logic technology to date.
  • Two-level single-ended cascode (2L-SE) circuits are well-known in the art. These two levels are generally called bottom stage and top stage !evels because of the DC voltages that the signals must respect.
  • FIG. 1 A conventional 2L-SE cascode circuit with NPN transistors and collector output usage is shown in Fig. 1.
  • the circuit 10 of Fig. I is made of two sets of current switches 11 and 12 mounted in cascode and of one translator stage per output, respectively referenced 13 for the true output and 14 for the complement output.
  • Circuit 10 is biased between a first supply voltage, a positive voltage VPP, and a second supply voltage, the ground GND.
  • the first set 11 of current switches is comprised of input transistors TX11 and TX12, connected in a differential amplifier configuration with reference transistor TX13. Combination of current switch 11 and transistor TX13 forms the so called "bottom stage" 16.
  • To TX13 base is connected to a fixed reference voltage VR11 delivered by a reference voltage generator.
  • A11 and A12, are applied to the bases of transistors TX11 and TX12, respectively.
  • the bottom stage is supplied by a constant current 10, determined by a conventional current source comprised of transistor TY11, the base of which is connected to a fixed reference voltage VRR delivered by a reference voltage generator, and resistor RE1.
  • Said constant current 10 ((VRR - VBE-(TY11))/RE1) has to flow either through TX11.TX12 or TX13; it flows through the transistor which receives the highest base voltage. Since in this example, collectors of TX11 and TX12 are tied together, the collector voltage may go low as soon as the current flows through TX11 or TX12, thus realizing a 2 Way OR function. Note that the extension to an N Way OR is trivial.
  • the second set 12 of current switches is comprised of input transistors TX14 and TX15 connected in a differential amplifier configuration with transistor TX16.
  • the combination of current switch 12 and transistor TX16 forms the so called "top stage" 17.
  • To TX16's base is connected a fixed reference voltage VR12 delivered by a reference voltage generator.
  • the top logic input signals N11 and N12 are applied to the bases of transistors TX14 and TX15, respectively.
  • the constant current is determined by the same current source as for the first set of current switches. It still flows through the transistor which receives the highest base voltage. Since in this example, TX14 and TX15 collectors are tied together, the collector voltage may be low as soon as the current flows through TX14 or TX15, realizing a 2 Way OR function. Note that the extension to an N Way OR is trivial.
  • Bottom stage 16 and top stage 17 the loads (RCC1, SBD11, RCT1 and SBD12), and the associated current source circuitry (TY11 and RE1), form the tree 15, biased between VPP and GND.
  • the true output T11 of the tree is available at node 18 formed by dotting collectors of transistors TX13 and TX16.
  • the complement output C11 is available at the node where collectors of TX14 and TX15 are tied together.
  • Level translator stage 13 for the true output is constituted with transistor TY12 mounted as an emitter follower and a current source comprised of TY13 and resistor RST1.
  • the top output T11 is available at collector of TX16 while the bottom output T12 is available on the emitter of TY12.
  • level translator stage 14 for complement output is comprised of devices TY14, TY15 and RSC1.
  • the top output C11 is available at the collector of TX14 while the bottom output C12 is available on the emitter of TY14.
  • Either translator stage 13 or 14 also acts as a buffer for 'bottom' connections.
  • circuit 10 may be broadly understood as being comprised of two stacking levels, the first including TX11, TX12 and TX13 forming the bottom stage and the second including TX14, TX15 and TX16 forming the top stage. Only the bottom stage is provided with a buffer stage.
  • the constant current source 10 sets the power that the logic tree 15 will consume in performing its designed logical function.
  • Logical operations are accomplished through selectively steering the tree current through various paths within the tree to one of two binary output summation points. Current steering is accomplished by applying logic input signals to each input of transistors in the tree, selecting the transistors that will allow the current to pass. Both sets of current switches in this example are connected so that, to get a low voltage at RCC1 resistance node, and thus a high voltage corresponding to a logical "1 " at RCT1 resistance node, the current has to flow through TX14 OR TX15 AND through TX11 OR TX12.
  • the logic function is therefore an AND of the two ORs.
  • the complementary function Y1 is available at output C11.
  • circuit 10 results from its excessive sensitivity to the capacitive loading at the top output.
  • line and wiring capacitance C1 a at top output T11 has a significant impact in terms of delay (time constant), which in turn, limits the switching speed of the cascode circuit. Therefore, this sensitivity is a serious detractor in terms of circuit performance.
  • Circuit 10 is also sensitive to dotting in terms of delay, as any dotting will bring additional capacitances.
  • Circuit 20 differs from circuit 10 only in the configuration of level translator stages 23 and 24. Unlike in circuit 10, the top output T21 of translator stage 23 is translated downward of a VBE, through transistor TY22 connected in an emitter follower configuration. As a result of this downshift, circuit 20 benefits from the buffering effect offered by this transistor TY22.
  • the bottom output T22 is translated even more by means of an output level shifter: either a PN junction (a transistor operating as a diode) or a Schottky junction. To avoid bottom stage transistor saturation in the tree, a minimum shift of 0,4V is needed.
  • the Schottky Barrier Diode offers a shift of 0,55V which is convenient.
  • the PN diode offers a shift of about 0,8V which is also appropriate, but does have the inconvenience of requiring a higher VPP supply for correct functional operation.
  • the circuit has a much better performance- power product over the circuit of Fig.1.
  • the tree current is lower, as the tree performs only the logic function without any load at the tree output.
  • TY22 and its associated current source TY23 take care of the load (wiring capacitance C2a and fan-out) at top output T21.
  • the cascode circuit 20 of Fig. 2 still presents various inconveniences mainly caused by the presence of said output level shifter consisting generally of a SBD.
  • circuit 20 is not usable with the 3.3 ⁇ 0.3V VPP supply as defined by the JEDEC specifications for future CMOS products and CMOS/bipolar interfaces in the worst case conditions, where the supply voltage VPP is as low as 3V.
  • top output (e.g. T21) may be only connected to corresponding top input signals (e.g. N21, N22,...) but not to the bottom input signals (e.g. A21, A22,...), of a following similar circuit, since transistors like TX21, TX22, and TX23, would saturate.
  • bottom output e.g. T22
  • bottom input signals e.g. A21, A22, etc..., but not to the top input signals e.g. N21, N22, etc..., of a following similar circuit.
  • Fig. 2 which includes two outputs per phase out, not only requires more wiring which in turn, results in lower density, but also implies two load capacitances, e.g. C2a and C2b, which are almost in parallel, because they are connected through said output level shifter which consists of a continuously conducting diode, e.g. SBD23, when the two outputs are simultaneously used.
  • said output level shifter which consists of a continuously conducting diode, e.g. SBD23, when the two outputs are simultaneously used.
  • the circuit of Fig. 2 must also use Schottky Barrier Diodes, referenced as SBD21 and SBD22, as clamping devices across collector resistors respectively referenced RCC2 and RCT2.
  • SBD21 and SBD22 Schottky Barrier Diodes
  • the intent is to provide both a good definition of the voltage swing which can not be minimized and to avoid saturation of the top output transistors such as TX24 and TX25; this may occur if the current source has wide variations due to process, temperature and power supply tolerances.
  • said clamping devices add to the collector parasitic capacitance. As a result, the presence of these clamping devices significantly impedes the speed of the cascode circuit.
  • a library of logic circuits based on the circuit shown in Fig. 2 would have two major incon- /eniences. First, it would have potentially a low power from a logical implementation point of view.
  • the circuit of Fig. 2 provides an OR-AND function; if more complex functions are needed, appropriate standard logic circuitry has to be added, at the cost of significantly lowering integration density.
  • the circuit shown in Fig. 2 exhibits a limited number of logical circuits, in that it does not allow generalization to 2N-level single ended cascode logic circuits, unless the power supply value is significantly increased, which is not the trend in designing future VLSI circuits.
  • the primary objective of the present invention is therefore to provide a family of cascode current switch logic circuits forming a library of various logic functions which do not have the above mentioned drawback inherent in the conventional cascode circuits with output level shifter.
  • an output level shifter such as a SBD
  • the present logic circuit family is derived from the conventional 2L-SE cascode circuit as detailed above, however some changes have been made.
  • the circuits are provided with the bottom output only. This means that an emitter follower (EF) configuration is systematically used, and for a given phase out, only one wire is necessary to connect to the loading circuit. This single wire means a better density and also a lower loading capacitance.
  • the output level shifter device e.g. a SBD, which down shifts the bottom level with respect of the top level, is no longer necessary.
  • the top stage level is recovered in each circuit input by means of at least one level shifter device (translator), such as a diode, connected to the input transistors.
  • a level shifter device such as a diode
  • This diode usage enables the addition of an AND logic function on the inputs when several diodes, whose anodes are connected together, are used. It is a key feature of the present invention to employ unidirectional current conducting means, such as diodes, as inputs to add an AND logic function in a cascode logic circuit.
  • circuits may be operated either from a 3.3 or from a 5.0 V nominal power supply, or any power supply insuring 3V minimum at the circuit itself, in the worst case.
  • the above concept may be generalized to the implementation of a family of 2n-level single-ended (2NL-SE) cascode logic circuits.
  • circuit 30 is broadly similar to circuit 20 of Fig. 2 to take full take benefit of the systematic usage of an emitter-follower from a performance point of view, in order to get a good power-performance product.
  • Circuit 30 is basically made of two sets of current switches 31 and 32 mounted in a cascode configuration and of one translator or output stage per output, respectively referenced 33 for the true output and 34 for the complement output.
  • Output circuits for the "true” and “complement” output are mounted in an emitter-follower configuration, in order to adjust the logical levels and to amplify the current.
  • Each output includes a current source, the value of which is selected according to the load, the dotting, and fan-out it will drive.
  • Circuit 30 is biased between the first supply voltage: a positive voltage VPP and a second supply voltage: the ground GND.
  • Current switch 31 is comprised of input transistors TX31 and TX32 connected in a differential amplifier configuration with reference transistor TX33, to form the bottom stage 36. Similar construction applies to form top stage 37. As previously explained with respect to Fig.
  • SBD's may be preferred due to the beneficial anode to cathode capacitance by which the switched input is coupled to the transistor base. If three or more diodes are used, PN diodes are preferred; otherwise, the unswitched Schottky anode to cathode capacitances would have become dominant and would have to be charged or discharged.
  • SBD's referenced SBD31 to SBD33 and resistor RD31 are combined to perform an AND function and are connected to the base of input transistor TX34.
  • SBD's 34 and 35 and resistor RD32 are also combined to perform an AND function and are connected to input transistor TX35.
  • logic functions that are basically associated with a simple cascode tree are an AND (or an OR) of an ANDOR at top stage level, combined with an OR at bottom stage level.
  • a Schottky contact is commonly fabricated by reacting a metal of the platinum group (Pt, Pd, ...) with the N- epitaxial layer of a silicon substrate when a high barrier diode which exhibits a high forward f oltage characteristic (e.g. 500-600 mv) is desired.
  • a high barrier diode which exhibits a high forward f oltage characteristic (e.g. 500-600 mv) is desired.
  • n° 65133 assigned to the assignee of the present invention.
  • SBD's with high potential barrier are used, for a better distinction in input voltage levels and to avoid bottom transistor saturation.
  • the reference voltage VR32 is obtained by shifting up the reference voltage VR31 through a similar SBD.
  • circuit 30 of Fig. 3 compared with circuit 20 of Fig. 2.
  • the figures given below are related to current state-of-the-art semiconductor technology.
  • a 2 Way Exclusive OR extended with a 3 way AND and a 3 way OR is shown on Fig. 5, which function is:
  • Another example is a 2 Way Selector extended with a 3 way AND and a 2 way AND as shown in Fig. 6.
  • Fig.7 displays the schematic for a 1 port Polarity Hold Shift Register Latch (PHSRL) implemented according to the LSSD technique.
  • TX77 and TX78 are the cross-coupled transistors of the master.
  • the data N0, N1 and N2 are ANDed in this book before being transferred to the master at the time when the C1 clock is active.
  • the slave inputs are directly tied to the collectors of TX77 and TX78. This means that the master loading at the emitter-follower does not delay the transmission to the slave. Note also that the master latching time does not depend on the master loading.
  • Another advantage of this schematic is that the master outputs (at emitter follower outputs) may be dotted, which is not a general case for latches.
  • this PHSRL may be clock driven from any book of the library, it does not require a specific clock driver book.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
EP87480023A 1987-12-15 1987-12-15 Famille étendue de circuits logiques du type commutateur de courant cascode (CSC) Expired - Lifetime EP0320555B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE3751365T DE3751365T2 (de) 1987-12-15 1987-12-15 Umfassende Familie von logischen Kaskode-Stromschaltkreisen (CSC).
EP87480023A EP0320555B1 (fr) 1987-12-15 1987-12-15 Famille étendue de circuits logiques du type commutateur de courant cascode (CSC)
JP63291120A JP2580289B2 (ja) 1987-12-15 1988-11-19 カスコード論理回路
US07/275,860 US4942316A (en) 1987-12-15 1988-11-25 Cascode logic circuit including a positive level shift at the input of the top logic stage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP87480023A EP0320555B1 (fr) 1987-12-15 1987-12-15 Famille étendue de circuits logiques du type commutateur de courant cascode (CSC)

Publications (2)

Publication Number Publication Date
EP0320555A1 true EP0320555A1 (fr) 1989-06-21
EP0320555B1 EP0320555B1 (fr) 1995-06-21

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EP87480023A Expired - Lifetime EP0320555B1 (fr) 1987-12-15 1987-12-15 Famille étendue de circuits logiques du type commutateur de courant cascode (CSC)

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US (1) US4942316A (fr)
EP (1) EP0320555B1 (fr)
JP (1) JP2580289B2 (fr)
DE (1) DE3751365T2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0410063A1 (fr) * 1989-07-26 1991-01-30 International Business Machines Corporation Famille logique de circuit commutateur de courant cascode différentiel avec diodes à l'entrée

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5299136A (en) * 1991-06-05 1994-03-29 International Business Machines Corp. Fully testable DCVS circuits with single-track global wiring
US5274285A (en) * 1992-09-01 1993-12-28 International Business Machines Corporation Enhanced differential current switch compensating upshift circuit
AU3582797A (en) * 1996-06-28 1998-01-21 Dpc Cirrus, Inc. Automated immunoassay analyzer
US8981831B1 (en) 2013-09-11 2015-03-17 International Business Machines Corporation Level shifter with built-in logic function for reduced delay

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EP0167339A2 (fr) * 1984-06-30 1986-01-08 Sony Corporation Circuit logique
EP0176909A1 (fr) * 1984-09-24 1986-04-09 Siemens Aktiengesellschaft Porte ET pour circuits ECL

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EP0176909A1 (fr) * 1984-09-24 1986-04-09 Siemens Aktiengesellschaft Porte ET pour circuits ECL

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IBM TECHNICAL DISCLOSURE BULLETIN, vol. 27, no. 1B, June 1984, pages 681-682, New York, US; G. BOUDON et al.: "Diode current switch logic" *
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0410063A1 (fr) * 1989-07-26 1991-01-30 International Business Machines Corporation Famille logique de circuit commutateur de courant cascode différentiel avec diodes à l'entrée
US5075574A (en) * 1989-07-26 1991-12-24 International Business Machines Corporation Differential cascode current switch (dccs) logic circuit family with input diodes

Also Published As

Publication number Publication date
DE3751365D1 (de) 1995-07-27
JP2580289B2 (ja) 1997-02-12
JPH01260922A (ja) 1989-10-18
US4942316A (en) 1990-07-17
DE3751365T2 (de) 1996-02-08
EP0320555B1 (fr) 1995-06-21

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