EP0319132B1 - Unterbrechungsabwicklung in einem parallelen Datenverarbeitungssystem - Google Patents

Unterbrechungsabwicklung in einem parallelen Datenverarbeitungssystem Download PDF

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Publication number
EP0319132B1
EP0319132B1 EP88309481A EP88309481A EP0319132B1 EP 0319132 B1 EP0319132 B1 EP 0319132B1 EP 88309481 A EP88309481 A EP 88309481A EP 88309481 A EP88309481 A EP 88309481A EP 0319132 B1 EP0319132 B1 EP 0319132B1
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EP
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Prior art keywords
instructions
instruction
registers
execution
address
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EP88309481A
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English (en)
French (fr)
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EP0319132A3 (de
EP0319132A2 (de
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Gregory Frederick Grohoski
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International Business Machines Corp
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International Business Machines Corp
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Publication of EP0319132A3 publication Critical patent/EP0319132A3/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

  • This invention relates to interrupt handling in a parallel data processing system.
  • a data processing system for executing a sequence of instructions, the data processing system comprising: a plurality of processors, each for executing instructions; means for dispatching each of the instructions to one of the processors; control means for directing the concurrent execution of the dispatched instructions in the plurality of processors irrespective of locations of the instructions in the sequence, the control means including interrupt handling means for receiving an instruction interrupt signal, and for resetting the plurality of processors and the dispatching means to a state that existed when the instruction that caused the interrupt signal was earlier executed, in order to re-execute the instruction sequence from the instruction that caused the interrupt signal; the system being characterised in that the control means comprises: one or more backup registers connectable to corresponding processor registers in at least one of said processors, said backup registers being arranged to store previous contents of the processor registers if the contents of the processor registers are updated during execution of the instructions; a storage means for storing entries relating to instructions issued by the dispatching means, each entry being arranged to include
  • an embodiment of the invention comprises a data processing system for executing a sequence of instructions including several processors, each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the processors. A control apparatus is included for directing the concurrent execution of the dispatched instructions in the processors irrespective of the locations of the instructions in the sequence.
  • the control apparatus includes the capability to receive an instruction interrupt signal. Upon receiving the instruction interrupt signal, the control apparatus determines which instruction execution generated the instruction interrupt.
  • the control apparatus includes the capability to reset the processors and the dispatching apparatus to the state that existed when the instruction that generated the instruction interrupt signal was first executed in order to re-execute the instruction that caused the interrupt.
  • control apparatus includes the capability to maintain a history of which instructions were dispatched to which processors.
  • the control apparatus further maintains a record of the contents of selected registers.
  • the control apparatus Upon the occurrence of an interrupt signal, the control apparatus is able to determine the state of these registers and the state of the processors that existed at the time the instruction was first executed. The control apparatus then reinitialises all of the processors with the information that has been stored to place the processors and the instruction dispatching apparatus into the state that existed when the instruction that caused the interrupt was first executed.
  • the disclosed arrangement provides a mechanism for the parallel and concurrent execution of several instructions while permitting interrupts to be processed in such a manner that the instruction execution will appear to be serial.
  • Figure 1 is a block diagram illustrating a data processing unit including a memory 10 connected to a memory controller 12 and instruction buffer 14. Connected to the instruction buffer 14 is a program counter stack and instruction dispatch logic 16. Several execution units 18a through 18d are in turn connected to the program counter stack and instruction dispatch logic 16. The execution units 18a through 18d are connected to an information bus 20 which provides for the distribution of information throughout the data processing system.
  • Figure 2 is a block diagram illustrating the instruction buffers 14 connected via bus lines 1 to instruction issue logic 17.
  • the instruction issue logic 17 is further connected via buses 2 and 3 to the program control stack 15.
  • the instruction issue logic 17 and the program counter stack 15 make up the block 16 of Figure 1.
  • Also illustrated are instructions units 18a, 18b, 18c and 18d. It should be apparent to those skilled in the art that the number of execution units included may vary in accordance with the number of instructions to be concurrently executed.
  • execution unit 18a executes branch instructions.
  • Execution unit 18b executes fixed point arithmetic instructions.
  • Execution unit 18c executes floating point arithmetic instructions.
  • execution units 18a through 18c are the only ones that are functional.
  • the instruction buffer 14 stores a large group of instructions that are received from the memory 10 ( Figure 1).
  • the instruction issue logic 17 loads instructions from the instruction buffer 14 into the available execution units 18a through 18d. In the preferred embodiment, the instruction issue logic 17 can load four instructions simultaneously to the execution units 18a - 18d. The instruction issue logic 17 further determines which instruction goes to which execution unit and if the execution unit is able to take an instruction. Furthermore, the instruction issue logic 17 provides an input over lines 2 to the program counter stack. This input includes the record of the instructions dispatched.
  • the program stack counter 15 provides a signal over line 3 to the instruction issue logic to stop the dispatching of instructions. This signal occurs when either an interrupt has been generated or when the stacks in the program counter 15 are full.
  • the instructions from the instruction issue logic 17 are provided to the appropriate execution units.
  • the branch execution unit 18a provides information to the program counter stack such as addresses and the values of certain registers over line 7.
  • the fixed point arithmetic instruction execution unit 18b provides signals over line 9 indicating the completion of instructions or the occurrence of an instruction interrupt signal.
  • the fixed point arithmetic instruction execution unit 18b further provides and receives signals from the floating point arithmetic instruction execution unit 18c over line 11. These signals over line 11 provide for synchronisation between the floating point and fixed point execution units for the execution of floating point load and store instructions.
  • the fixed point execution unit 18b completes address calculations floating point load and store instructions. The fixed point execution unit 18b then sends these addresses to memory.
  • the fixed point unit 18b For store instructions, the fixed point unit 18b must know when the floating point unit 18c has completed execution of the instruction so that the fixed point unit 18b will know when data is ready to be stored and therefore, when the address is ready to be transmitted. Furthermore, the fixed point unit 18b signals the occurrence of interrupts to the floating point unit 18c so that it will disregard the current floating point unit instruction.
  • Figure 3 illustrates, in a more detailed fashion, the intercommunication between the branch unit 18a and the program counter stack 16.
  • the branch unit 18a is shown to contain the count register 22, the link register 24, the condition register 26, and the interrupt address register 28.
  • the count register 22 maintains a count for the execution of loop instructions in the branch execution unit 18a.
  • the link register 24 maintains the address for link operations such as the return from a subroutine call.
  • the condition register 26 maintains the condition codes that result from comparison operations.
  • the interrupt address register 28 receives the address of an instruction that has generated an interrupt.
  • the count register 22 is connected by lines 40 and 42 to the count register backup stack 30 in the program counter stack 16.
  • the link register 24 is connected to the link register backup stack 32 by lines 44 and 46.
  • condition register 26 is connected via lines 48 and 50 to the condition register backup stack 34.
  • the interrupt address register 28 is connected via line 70 to an adder 75.
  • the adder 75 produces the interrupt address for the interrupt register 28 via line 71.
  • the contents of these registers 22, 24, 26 and 28 control the state of the execution of the branch execution unit 18a.
  • the program counter storage entry storage table 36 is updated.
  • the base address is provided on line 56.
  • the mask and two fields are provided from line 54 from the program counter stack control 38.
  • the program counter stack control 38 receives this information via line 63 from the instruction issue logic 17. Additionally, the program counter stack control 38 updates stack pointers 39 which contain head pointers and tail pointers for the three backup stacks 30, 32 and 34, and executes the stack removal and stack addition functions performed by the stack addition logic 64 and stack removal logic 66.
  • the program counter stack control 38 regulates the operation of the backup stacks 30, 32, and 34 by line 52. Furthermore, this control 38 provides the stop dispatch signals to the instruction issue logic 17 on line 62 and receives the instruction complete and interrupt signals from the fixed point execution unit 18b on line 60 as previously discussed.
  • the program counter stack entry storage 36 provides the address of the interrupting instruction on line 70 to the interrupt address register 28.
  • Figure 4 is an illustration of the contents of the program counter stack entry storage 36 ( Figure 3).
  • a single entry 80 is listed that includes the base instruction address field 82, the 4 bit mask field 84, the instruction 1 field 86 and the instruction 2 field 88.
  • Field 82 is the address of the base instruction for the 4 instruction sequence that has been dispatched in the cycle by the instruction issue logic 17 ( Figure 2).
  • the mask field 84 indicates the position of any interrupt causing instructions in this 4 instruction group. In the present embodiment, only two instructions can cause interrupts in a 4 instruction group. Therefore, there are only two instruction fields 86 and 88 provided to record these instructions.
  • the first instruction field 86 includes sub-fields 90, 92, and 94. Field 90 indicates whether the link register 24 has been changed.
  • Field 92 indicates whether the count register 22 has been changed.
  • Field 94 indicates whether the condition register 26 has been changed.
  • field 90 and 92 contain 1 bit each.
  • Field 94 contains 3 bits indicating the three separate portions of the condition register 26.
  • Field 88 also contains fields similar to field 86 and are illustrated as fields 96, 97 and 98 that correspond to fields 90, 92 and 94 previously discussed.
  • the operation of this arrangement is best understood by an example illustration.
  • the TABLE appended hereto lists twelve instructions that are to be dispatched for execution by the execution units. These instructions are divided up into three groups of four instructions each. For this example, the address of the first instruction is 1. Group I consisting of instructions 1 through 4 are dispatched in cycle 1.
  • Figure 5 illustrates the contents of the program counter stack entry storage 36 consisting of entry positions 100, 102 and 104; the count register backup stack 30, consisting of entries 30a, 30b and 30c; the link register backup stack 32, consisting of entries 32a, 32b and 32c; and the condition register backup stack 34, consisting of entries 34a, 34b and 34c. Additionally, the initial contents of the count register 22, the link register 24 and the condition register 26 are illustrated as 50, 60 and 70 respectively. The actual value of these contents is arbitrary and is merely included to provide the reader with an aid to facilitate tracing of the entries through this example.
  • instructions 1 through 4 are dispatched. Since a load instruction (instruction 1) was dispatched, one entry will be added to the program counter stack entry storage 36. In this embodiment, only load and store instructions may generate interrupts.
  • the base address of "1" is stored.
  • the mask value is 1000 denoting that the first instruction is the location of the instruction that might cause an interrupt. If two instructions were included in the four instruction group, 2 bits of the mask field would be set to 1.
  • the location of the bits denotes the location of the interrupt causing instructions in the 4 instruction sequence. Therefore, the mask bit positions can be used as offsets to the base address to provide the actual addresses of the interrupt causing instructions.
  • the contents of field 1 are set if the count register 22, the link register 24, and the condition register 26 contents are changed during the execution of this four instruction sequence.
  • the branch instruction sets the count register 22 and link register 24.
  • the LCR (logic on condition register) instruction sets the contents of the condition register 26. The previous contents of these registers are stored as shown.
  • Figure 7 illustrates the status after cycle 2.
  • instructions 5 through 8 (group II of TABLE) are dispatched. Since group II is the exact same set of instructions as group I, the same actions occur to update the backup stacks respectively. Also, the execution of instructions 7 and 8 update the count register 22, the link register 24 and the condition register 26 as shown.
  • the backup registers 30, 32 and 34 store the previous contents of the count register 22, the link register 24 and the condition register 26.
  • Each cycle an interrupt causing instruction is dispatched a record of the dispatch cycle is written in to the program counter stack entry storage 36. If subsequent instructions cause the link register 24, the count register 22, or the condition register 26 to be updated, the old values of these registers are stored in the appropriate backup stacks and the respective tail pointers are incremented.
  • FIG. 8 illustrates the contents of the registers at the end of cycle 3 when the group III instructions have been dispatched. For this example, during cycle 3, the fixed point unit 18b executes instruction 1. For this example, instruction 1 did not cause an interrupt. Since only one interrupt causing instruction was dispatched during this cycle (cycle 1), the entire entry 100 may be removed. Using information in field 1, the backup register entries 30a, 32a and 34a are also removed. This is accomplished by incrementing the head pointer as previously discussed.
  • the program counter stack storage entry 104 is as shown.
  • the count register 22, the link register 24 and condition register 26 are provided with values 57, 67 and 77 respectively.
  • the previous values of these registers are stored in the appropriate entries in their backup stacks 30, 32 and 34 as shown.
  • Figure 9 illustrates the contents of these registers at the end of cycle 4.
  • instruction 2 was executed by the fixed point unit 18b. Since it is not a load or store instruction, it cannot cause an interrupt. Therefore, no entries need to be removed from the program counter stack entry storage 36.
  • Figure 10 illustrates the contents of the register at the end of cycle 5.
  • the fixed point execution unit 18b has executed instruction 5.
  • this instruction has caused an interrupt.
  • the offset mask bits (1000) are combined with the base address (5) to determine the position of the instruction that caused the interrupt.
  • the address is 5.
  • the backup values for these registers are provided to these registers. These values are stored in entries 30b, 32b and 34b respectively.
  • the address of the interrupting instruction is provided to the branch execution unit 18a.
  • the backup register contents are provided to their respective registers.
  • the program counter stack entry storage 36 and backup stacks 30, 32 and 34 are then purged of all information since this stored information is no longer relevant and the system is being reinitialise to the state when the instruction at location 5 was executed.
  • Figure 11 illustrates the register contents at the end of cycle 6 when the condition register 22, the link register 24 and the condition register 26 have been updated. At the end of cycle 6, the system has been reinitialised and is ready to start again the execution of the instruction sequence starting at instruction 5.
  • the interrupts are received on a first-in, first-out basis.
  • the oldest instruction that might generate an interrupt is assumed to have generated this interrupt.
  • the oldest instruction is not necessarily the instruction that causes the interrupt. The system could then determine the instruction that caused the interrupt by a tag that would be provided by the occurrence of the interrupt.
  • Figure 12 illustrates a state diagram depicting the concurrent execution of the stack addition function in logic 64 (state 122) and the execution of the stack removal function 124 in the stack removal logic 66. These functions 122 and 124 are executed during each cycle as depicted by states 120 and 126.
  • FIG. 13 is a flow chart illustrating the stack addition function.
  • the stack addition logic 64 begins at step 200 and proceeds to step 202 to determine if a load or store instruction was dispatched. If so, the logic proceeds to step 204 to store the base address and set the tag offset bits of the program counter stack entry storage 36. If a load and store instruction was not dispatched or, after the base address and offset bits have been stored, the logic proceeds to step 206 to determine if any branch or LCR instructions were dispatched before a load or store instruction. If so, the tag bits of the previous program counter stack entry is updated and the old values of the count, link and condition registers are stored on the backup stacks. The program then proceeds to step 216.
  • step 210 determines if any branch or LCR instructions were dispatched after a load or store instruction. If so, the logic proceeds to step 212 to set the tag bits of the present program counter storage entry and to store the old values on the backup stacks. Then in step 216, the backup stack pointers 39 are incremented.
  • step 214 if no branch or LCR instructions were dispatched after a load or store instruction, the logic proceeds to step 214 to set the tag bits of the present program counter stack entry to zero. Then, in step 218, the pointer to the program counter stack entry is incremented if a load or store instruction was dispatched.
  • step 220 the logic determines if the program counter stack entry storage is full. If so, a latch is set in step 222 to send the stop dispatch signal to the instruction issue logic 17. In step 224, the logic 64 waits until the next cycle has occurred when it returns to step 200.
  • Figure 14 is a flow chart illustrating the stack removal procedure performed by logic 66.
  • the logic 66 moves from step 300 to step 302 to determine if a load or store instruction has been executed by the fixed point execution unit. If not, the logic proceeds to step 310. If so, the logic proceeds to step 304 to determine if all load and store instructions in the program counter stack entry storage were executed. If not, the program proceeds to step 306 to wait until the next cycle. If all of the load and store instructions for the entry were executed, the logic proceeds to step 308 to remove the entry and use the status bits to remove the backup stack entries and to decrement all of the pointers. Upon the completion of step 308, the logic proceeds to step 306 to wait for the next cycle.
  • step 310 the logic determines if a load or store instruction caused an interrupt. If not, the logic proceeds to step 306. If an interrupt has occurred, the logic proceeds to step 312 to reconstruct the address of the load and store instruction from the base address and tag bits in the program counter stack entry. Then, in step 314, the old values of the link 24, count 22 and condition registers 26 are stored if appropriate. In step 316, the contents of the program counter stack entry storage 36 and the respective backup registers are purged since these values would no longer be relevant. The logic 66 then proceeds to step 306 to wait for the next cycle.

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Claims (8)

  1. Ein Datenverarbeitungssystem zur Ausführung einer Befehlssequenz, wobei das Datenverarbeitungssystem folgendes umfaßt:
    eine Vielzahl von Prozessoren (18A-18D), jeweils zum Ausführen von Befehlen;
    Mittel (17), um jeden der Befehle an einen der Prozessoren zu verteilen;
    Steuermittel (16), um die gleichzeitige Ausführung der verteilten Befehle in der Vielzahl von Prozessoren (18A-18D) zu steuern, unabhängig von den Positionen der Befehle in der Befehlssequenz, wobei das Steuermittel Unterbrechungsabwicklungsmittel umfaßt, um ein Befehlsunterbrechungssignal zu empfangen, und um die Vielzahl von Prozessoren (18A-18D) und die Verteilmittel (17) in einen Zustand zurückzusetzen, der bestand, als der Befehl, der das Unterbrechungssignal verursachte, zuerst ausgeführt wurde, um die Befehlssequenz ab dem Befehl, der das Unterbrechungssignal verursachte, erneut auszuführen;
    wobei das System dadurch gekennzeichnet ist, daß das Steuermittel (16) folgendes umfaßt:
    ein oder mehrere Sicherungsregister (30, 32, 34), die mit entsprechenden Prozessor-Registern (22, 24, 26) in mindestens einem der genannten Prozessoren (18A-18D) verbunden werden können, wobei die genannten Sicherungsregister so angeordnet sind, daß die vorherigen Inhalte der Prozessor-Register gespeichert werden, wenn die Inhalte der Prozessor-Register während der Ausführung der Befehle aktualisiert werden;
    ein Speichermittel (36) zum Speichern von Einträgen (80), die sich auf Befehle beziehen, die von dem Verteilmittel (17) ausgegeben werden, wobei jeder Eintrag so angeordnet ist, daß er Adresseninformationen für eine Vielzahl von Befehlen enthält, die von dem Verteilmittel (17) gleichzeitig ausgegeben werden, und eine Angabe darüber, ob an den Inhalten der Prozessor-Register (22, 24, 26) während der Ausführung der genannten Vielzahl von Befehlen Veränderungen stattfanden, wobei die Adresseninformation eine Basisadresse (82) umfaßt, die die Adresse eines ersten einer Vielzahl von Befehlen anzeigt, und ein Offset-Feld (84), das die Position eines jeden der Vielzahl von Befehlen, der ein Unterbrechungssignal erzeugen könnte, bezogen auf den ersten Befehl, anzeigt;
    wobei das Unterbrechungsabwicklungs-Mittel (38) auf den Empfang eines Unterbrechungssignals reagiert und auf das Speichermittel (36) zugreift, um die Adresse des Befehls, der das Unterbrechungssignal verursachte, zu erhalten, indem es die Daten des Offset-Felds (84) als Offsets zu der Basisadresse (82) einsetzt und anschließend diese Adresse einem der Prozessoren (18A-18D) zur Verfügung stellt;
    das Unterbrechungsabwicklungs-Mittel außerdem bewirkt, daß die Inhalte der Sicherungsregister (30, 32, 34) ihren jeweiligen Prozessor-Registern (22, 74, 26) bereitgestellt werden, wenn der Eintrag in dem Speichermittel (36) anzeigt, daß die Inhalte dieser Prozessor-Register im Verlauf der Ausführung der Vielzahl von Befehlen verändert wurden.
  2. Ein System nach Anspruch 1, bei dem das Steuermittel (16) weiter Löschmittel umfaßt, um alle Informationen in den Sicherungsregistern (30, 32, 34) und dem Speichermittel (36) vor der erneuten Ausführung der Befehlssequenz ab dem Befehl, der das Unterbrechungssignal verursachte, zu löschen.
  3. Ein System nach Anspruch 1 oder Anspruch 2, bei dem ein Befehlsfeld (86, 88) für einen jeden der genannten Vielzahl von Befehlen, die ein Unterbrechungssignal erzeugen könnten, in dem Eintrag des Speichermittels (36) enthalten ist, um anzuzeigen, ob die Inhalte der Prozessor-Register im Verlauf der Ausführung der genannten Vielzahl von Befehlen geändert wurden.
  4. Ein System nach einem der Ansprüche 1 bis 3, bei dem ein Eintrag in das Speichermittel (36) nur dann erfolgt, wenn einer oder mehrere der Vielzahl von Befehlen, die gleichzeitig von dem Verteilmittel (17) ausgegeben werden, ein Befehlstyp ist, der ein Unterbrechungssignal verursachen könnte.
  5. Ein System nach einem der vorangehenden Ansprüche, weiter umfassend Eintragsentfernungsmittel um, in Antwort darauf, daß die Vielzahl von Befehlen ausgeführt wird, ohne daß ein Unterbrechungssignal erzeugt wird, den betreffenden Eintrag in dem Speichermittel (36) und die betreffenden Einträge in den Sicherungsregistern (30, 32, 34) zu entfernen.
  6. Ein System nach Anspruch 5, bei dem die zugehörigen Einträge in den Sicherungsregistern (30, 32, 34) entfernt werden, indem Kopfzeiger zu den Sicherungsregistern inkrementiert werde.
  7. Ein System nach einem der vorangehenden Ansprüche, bei dem das Unterbrechungsabwicklungs-Mittel Addierer-Mittel enthält, um die Basisadresse (82) mit den Daten des off-set-Felds (84) zu verbinden, um die Adresse des Befehls, der das Unterbrechungssignal bewirkte, bereitzustellen.
  8. Ein System nach einem der vorangehenden Ansprüche, bei dem das Steuermittel Mittel enthält, um einen Befehlsdatensatz einem Datensatz in einem Prozessor-Register zuzuordnen.
EP88309481A 1987-11-30 1988-10-11 Unterbrechungsabwicklung in einem parallelen Datenverarbeitungssystem Expired - Lifetime EP0319132B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12681887A 1987-11-30 1987-11-30
US126818 2002-04-19

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EP0319132A2 EP0319132A2 (de) 1989-06-07
EP0319132A3 EP0319132A3 (de) 1991-12-04
EP0319132B1 true EP0319132B1 (de) 1996-01-03

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EP (1) EP0319132B1 (de)
JP (1) JPH01166248A (de)
BR (1) BR8806279A (de)
CA (1) CA1313275C (de)
DE (1) DE3854859T2 (de)

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Publication number Priority date Publication date Assignee Title
US5075844A (en) * 1989-05-24 1991-12-24 Tandem Computers Incorporated Paired instruction processor precise exception handling mechanism
US5440703A (en) * 1993-09-20 1995-08-08 International Business Machines Corporation System and method for saving state information in a multi-execution unit processor when interruptable instructions are identified
CN1099073C (zh) * 1995-01-24 2003-01-15 联华电子股份有限公司 并行处理器的定址装置
EP0819840A1 (de) * 1996-07-17 1998-01-21 Isuzu Ceramics Research Institute Co., Ltd. Isoliervorrichtung für Schall und Vibrationen eines Cogenerationssystems mit einer Maschine
EP0935058A3 (de) 1998-02-06 2000-09-06 Isuzu Ceramics Research Institute Co., Ltd. Kühler und Maschinenlärmschutzumhüllung
US7502725B2 (en) 2004-04-29 2009-03-10 International Business Machines Corporation Method, system and computer program product for register management in a simulation environment

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JPH01166248A (ja) 1989-06-30
BR8806279A (pt) 1989-08-15
DE3854859T2 (de) 1996-07-11
EP0319132A3 (de) 1991-12-04
CA1313275C (en) 1993-01-26
EP0319132A2 (de) 1989-06-07
DE3854859D1 (de) 1996-02-15

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