EP0315365A2 - Display device - Google Patents

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Publication number
EP0315365A2
EP0315365A2 EP88310086A EP88310086A EP0315365A2 EP 0315365 A2 EP0315365 A2 EP 0315365A2 EP 88310086 A EP88310086 A EP 88310086A EP 88310086 A EP88310086 A EP 88310086A EP 0315365 A2 EP0315365 A2 EP 0315365A2
Authority
EP
European Patent Office
Prior art keywords
column
matrix
column portion
sub
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88310086A
Other languages
German (de)
French (fr)
Other versions
EP0315365A3 (en
EP0315365B1 (en
Inventor
Graham Leslie Wright
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI PLC
Original Assignee
Thorn EMI PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Thorn EMI PLC filed Critical Thorn EMI PLC
Priority to AT88310086T priority Critical patent/ATE103092T1/en
Publication of EP0315365A2 publication Critical patent/EP0315365A2/en
Publication of EP0315365A3 publication Critical patent/EP0315365A3/en
Application granted granted Critical
Publication of EP0315365B1 publication Critical patent/EP0315365B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3644—Control of matrices with row and column drivers using a passive matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to a liquid crystal display.
  • the column electrodes are driven by the data pulses and the row electrodes are driven in turn, the contrast depending on the r.m.s. voltage across the liquid crystal cell.
  • the row drive must be of comparatively long duration, thereby limiting the number of rows which can be driven sequentially in a picture period and hence the number of lines per picture. It is known to double the number of rows which can be addressed in a given time by using two matrices, each with half the rows of the display and each with its own set of column data drives, thereby enabling two rows, one from each matrix to be driven simultaneously.
  • GB 2146478A discloses an arrangement in which two or more rows of a liquid crystal display are addressed with pulses which overlap in time.
  • the display has a switching transistor per pixel, and the duration of each row selection pulse, to switch the transistors on, is twice the line period, beginning one line period early.
  • the data pulses applied to the columns are those of row (N-1) so the LCD capacitancies of row N (i.e. the capacitancies of the electrodes of row N) are charged to V N-1 .
  • the data for row N is applied to change the charge to the correct V N .
  • the capacitancies in row N+1 are charged to V N since the row drive N+1 overlaps row N drive.
  • the charges are corrected to V N+1 .
  • a display device comprising: a matrix of selectively settable liquid crystal display cells defined by areas of overlap between members of a set of row electrodes and members of a set of column electrodes, a first column electrode comprising a plurality of first column portions, each defining a sub-matrix; means for driving said first column electrode; selectively operable means for switching for permitting selective electrical connection from each first column portion to the driving means; and means for addressing simultaneously rows in more than one sub-matrix.
  • the display device includes means for charging column capacitancies of each sub-matrix in turn, starting with the sub-matrix furthest from the respective drive(s) with all the switching means in a mode providing electrical connection between corresponding column portions.
  • the display device includes means for operating, to the open-circuit mode, the switching means for the corresponding column portions between the sub-matrix furthest from the respective drive(s) and the sub-matrix second furthest from the respective drive(s); this action may be taken at the end of the application of the data pulses to the column electrodes.
  • the display device includes means for applying the data pulse of the second furthest sub-matrix while still applying the row selection pulse to the furthest sub-matrix. This is so, because the furthest sub-matrix is now isolated from the column drives.
  • data pulses can be applied to the columns in each sub-matrix in turn while maintaining the row selection drive in all sub-matrices simultaneously. It is necessary to load all column capacitances in each sub-matrix in a time short compared with the row address period.
  • a liquid crystal display 1 is formed of a matrix of twisted nematic liquid crystal cells which are separately settable by appropriate multiplexed addressing of the information to be displayed. Each cell is defined by the overlap (as shown in Figure 1) of a column electrode strip (e.g. 2, 3 or 4) and a row electrode strip 5 to 13.
  • Each column electrode 2, 3, 4 is formed as a plurality of column portions 2a, 2b, 2c; 3a, 3b, 3c; 4a, 4b, 4c. These define a number of distinct sub-matrices 14, 15, 16 located one below another in the row addressing sequence, the sub-matrices sharing respective column electrodes 2 to 4, while having different row strips, namely 5 to 7, 8 to 10 and 11 to 13 respectively.
  • Switches 17 to 22 e.g. transistors or other electronic components
  • switches 17 to 22 actuable by the application of signals along switch lines 23 and 24.
  • the driving circuitry (not shown but located at the upper end of lines 2 to 4) drives all column portions to the voltage required on the sub-matrix 16.
  • Switches 20, 21 and 22 are then opened by application of a suitable gate voltage and the drive voltage for sub-matrix 15 applied, and so on.
  • the display can therefore be divided into a number of sub-matrices without increasing the number of external drivers, and yield should remain high since relatively few transistors are used (compared with a full active matrix). Rapid switching of the transistors is required (all of the column portions must be loaded in a short time compared with the row address time), and the time constant for the decay of charge stored on the column portions must be long compared with the row address times.
  • the RC time constants associated with the "on" resistance of the transistors and the capacitance of the column portions are kept small in order that all column portions can be loaded with charge in a time small compared with the row address time (equal to the frame period divided by the number of lines, i.e. row electrodes, in each sub-matrix).
  • FIG. 2 illustrates the detailed construction of the switching transistors 17 to 19 and their interface with, and connection, of the portions 2a, 2b; 3a, 3b; 4a, 4b of the column conductors 2, 3 and 4.
  • Each transistor has a silicon island 30 and a source/drain contact hole 31.
  • the display can therefore be divided into a number of sub-matrices without increasing the number of external drivers, and yield should remain high since relatively few transistors are used (compared with a full active matrix). Rapid switching of the transistors is required (all of the column portions must be loaded in a short time compared with the row address time), and the time constant for the decay of charge stored on the column portions must be long compared with the row address times.
  • the RC time constants associated with the "on" resistance of the transistors and the capacitance of the column portions are dept small in order that all column portions can be loaded with charge in a time small compared with the row address time (equal to the frame period divided by the number of lines, i.e. row electrodes, in each sub-matrix).
  • FIG. 2 illustrates the detailed construction of the switching transistors 17 to 19 and their interface with, and connection, of the poritons 2a, 2b; 3a, 3b; 4a, 4b of the column conductors 2, 3 and 4.
  • Each transistor has a silicon island 30 and a source/drain contact hole 31
  • the above arrangement can be modified such as to provide a different number of rows in each sub-matrix, the minimum limit being a single row per sub-matrix.
  • the number of lines which could be addressed is somewhat limited by the high RC time constants arising from placing a large number of transistor "on" resistances in series.
  • About 30 lines of 1mm square pixels can be achieved in a twisted nematic display if the transistor "on" resistance can be limited to 5 kohms (which is typical for a poly silicon transistor having a gate width of the maximum possible, 1mm).
  • a display can be driven in two sub sectors to achieve 60 lines in total, and the total number of lines achieved if multiplexed banks are used can be much higher.
  • Figure 3 shows a variant on the matrix of Figure 1, the major distinction being that now the switching transistors 40 to 48 do not connect between adjacent strips of a given column, but instead connect column portions (e.g. A, B and C) of each full column strip to separate column address lines 49 to 51 and hence to the column drive.
  • Each column capacitance can now be charged by the closure of a single transistor switch, thereby eliminating problems resulting from the "on" resistance of several resistors in series, and consequently removing the restriction on the number of submatrices into which the display is divided.
  • the number of transistors and cross-over points is reduced as compared to that in full-active matrixing, and a reduction in the number of display defects may be achieved.
  • a display embodying the present invention may have a higher yield since the 'cross over' source of defects is eliminated.
  • a display embodying the present invention can also be used to connect adjacent multiplexed tiles through externally mounted transistors.

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  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Vehicle Body Suspensions (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)

Abstract

A display device (1) comprises a matrix of selectively settable liquid crystal display cells defined by areas of overlap between members (5-13) of a set of row electrodes and members (2-4) of a set of column electrodes. A first column electrode (2, 3, 4) comprises a plurality of first column portions (a, b, c; A, B, C), each defining a sub-matrix (14, 15, 16). The display device (1) further comprises means (not shown) for driving said first column electrode; selectively operable means (17-22; 40-48) for switching for permitting selective electrical connection from each first column portion to the driving means and means (not shown) for addressing simultaneously rows in more than one sub-matrix.

Description

  • The present invention relates to a liquid crystal display.
  • In a conventional multiplexed twisted nematic liquid crystal display, the column electrodes are driven by the data pulses and the row electrodes are driven in turn, the contrast depending on the r.m.s. voltage across the liquid crystal cell. To obtain adequate contrast the row drive must be of comparatively long duration, thereby limiting the number of rows which can be driven sequentially in a picture period and hence the number of lines per picture. It is known to double the number of rows which can be addressed in a given time by using two matrices, each with half the rows of the display and each with its own set of column data drives, thereby enabling two rows, one from each matrix to be driven simultaneously.
  • GB 2146478A (Sharp) discloses an arrangement in which two or more rows of a liquid crystal display are addressed with pulses which overlap in time. However the display has a switching transistor per pixel, and the duration of each row selection pulse, to switch the transistors on, is twice the line period, beginning one line period early. During the first half of row pulse N, the data pulses applied to the columns are those of row (N-1) so the LCD capacitancies of row N (i.e. the capacitancies of the electrodes of row N) are charged to VN-1. During the second half of the row pulse the data for row N is applied to change the charge to the correct VN. At the same time the capacitancies in row N+1 are charged to VN since the row drive N+1 overlaps row N drive. Similarly in the second half of the row N+1 drive pulse, the charges are corrected to VN+1.
  • According to the present invention there is provided a display device comprising: a matrix of selectively settable liquid crystal display cells defined by areas of overlap between members of a set of row electrodes and members of a set of column electrodes, a first column electrode comprising a plurality of first column portions, each defining a sub-matrix;
    means for driving said first column electrode;
    selectively operable means for switching for permitting selective electrical connection from each first column portion to the driving means;
    and means for addressing simultaneously rows in more than one sub-matrix.
  • It will be appreciated that though the present invention is defined with reference to a first column electrode of the display device, in practice, the present invention is likely to be applied to each column electrode of the display device.
  • In this way, a number of sub-matrices can be driven by the same set of column driving means, with simultaneous addressing of rows in different sub-matrices. Because of the selectively operable switching means, it is not necessary for each sub-matrix to have its own independent set of column lines, and hence the need of separate conductors to connect the column electrodes of the sub-matrices to the edge of the matrix display is obviated. Thus the amount of conductor paths is minimised; also, the complexity of drive-circuitry is minimised.
  • Preferably the display device includes means for charging column capacitancies of each sub-matrix in turn, starting with the sub-matrix furthest from the respective drive(s) with all the switching means in a mode providing electrical connection between corresponding column portions.
  • Preferably the display device includes means for operating, to the open-circuit mode, the switching means for the corresponding column portions between the sub-matrix furthest from the respective drive(s) and the sub-matrix second furthest from the respective drive(s); this action may be taken at the end of the application of the data pulses to the column electrodes.
  • Preferably, the display device includes means for applying the data pulse of the second furthest sub-matrix while still applying the row selection pulse to the furthest sub-matrix. This is so, because the furthest sub-matrix is now isolated from the column drives.
  • In this way, data pulses can be applied to the columns in each sub-matrix in turn while maintaining the row selection drive in all sub-matrices simultaneously. It is necessary to load all column capacitances in each sub-matrix in a time short compared with the row address period.
  • In order that the invention may more readily be understood, a description is now given, by way of example only, reference being made to the accompanying drawings, in which:
    • Figure 1 shows part of a liquid crystal display embodying the present invention;
    • Figure 2 is a detail of Figure 1; and
    • Figure 3 shows part of another liquid crystal display embodying the present invention.
  • A liquid crystal display 1 is formed of a matrix of twisted nematic liquid crystal cells which are separately settable by appropriate multiplexed addressing of the information to be displayed. Each cell is defined by the overlap (as shown in Figure 1) of a column electrode strip (e.g. 2, 3 or 4) and a row electrode strip 5 to 13. Each column electrode 2, 3, 4 is formed as a plurality of column portions 2a, 2b, 2c; 3a, 3b, 3c; 4a, 4b, 4c. These define a number of distinct sub-matrices 14, 15, 16 located one below another in the row addressing sequence, the sub-matrices sharing respective column electrodes 2 to 4, while having different row strips, namely 5 to 7, 8 to 10 and 11 to 13 respectively. Corresponding column portions between adjacent sub-matrices are electrically connectable by means of switches 17 to 22 (e.g. transistors or other electronic components) actuable by the application of signals along switch lines 23 and 24. With all switches 17 to 22 closed the driving circuitry (not shown but located at the upper end of lines 2 to 4) drives all column portions to the voltage required on the sub-matrix 16. Switches 20, 21 and 22 are then opened by application of a suitable gate voltage and the drive voltage for sub-matrix 15 applied, and so on.
  • The display can therefore be divided into a number of sub-matrices without increasing the number of external drivers, and yield should remain high since relatively few transistors are used (compared with a full active matrix). Rapid switching of the transistors is required (all of the column portions must be loaded in a short time compared with the row address time), and the time constant for the decay of charge stored on the column portions must be long compared with the row address times. The RC time constants associated with the "on" resistance of the transistors and the capacitance of the column portions are kept small in order that all column portions can be loaded with charge in a time small compared with the row address time (equal to the frame period divided by the number of lines, i.e. row electrodes, in each sub-matrix).
  • Figure 2 illustrates the detailed construction of the switching transistors 17 to 19 and their interface with, and connection, of the portions 2a, 2b; 3a, 3b; 4a, 4b of the column conductors 2, 3 and 4. Each transistor has a silicon island 30 and a source/drain contact hole 31.
  • The display can therefore be divided into a number of sub-matrices without increasing the number of external drivers, and yield should remain high since relatively few transistors are used (compared with a full active matrix). Rapid switching of the transistors is required (all of the column portions must be loaded in a short time compared with the row address time), and the time constant for the decay of charge stored on the column portions must be long compared with the row address times. The RC time constants associated with the "on" resistance of the transistors and the capacitance of the column portions are dept small in order that all column portions can be loaded with charge in a time small compared with the row address time (equal to the frame period divided by the number of lines, i.e. row electrodes, in each sub-matrix).
  • Figure 2 illustrates the detailed construction of the switching transistors 17 to 19 and their interface with, and connection, of the poritons 2a, 2b; 3a, 3b; 4a, 4b of the column conductors 2, 3 and 4. Each transistor has a silicon island 30 and a source/drain contact hole 31
  • The above arrangement can be modified such as to provide a different number of rows in each sub-matrix, the minimum limit being a single row per sub-matrix. In the latter case, the number of lines which could be addressed is somewhat limited by the high RC time constants arising from placing a large number of transistor "on" resistances in series. About 30 lines of 1mm square pixels can be achieved in a twisted nematic display if the transistor "on" resistance can be limited to 5 kohms (which is typical for a poly silicon transistor having a gate width of the maximum possible, 1mm). A display can be driven in two sub sectors to achieve 60 lines in total, and the total number of lines achieved if multiplexed banks are used can be much higher.
  • Figure 3 shows a variant on the matrix of Figure 1, the major distinction being that now the switching transistors 40 to 48 do not connect between adjacent strips of a given column, but instead connect column portions (e.g. A, B and C) of each full column strip to separate column address lines 49 to 51 and hence to the column drive. Each column capacitance can now be charged by the closure of a single transistor switch, thereby eliminating problems resulting from the "on" resistance of several resistors in series, and consequently removing the restriction on the number of submatrices into which the display is divided. In this embodiment, the number of transistors and cross-over points is reduced as compared to that in full-active matrixing, and a reduction in the number of display defects may be achieved.
  • A display embodying the present invention may have a higher yield since the 'cross over' source of defects is eliminated. A display embodying the present invention can also be used to connect adjacent multiplexed tiles through externally mounted transistors.

Claims (5)

1. A display device comprising: a matrix of selectively settable liquid crystal display cells defined by areas of overlap between members of a set of row electrodes and members of a set of column electrodes, a first column electrode comprising a plurality of first colum portions, each defining a sub-matrix;
means for driving said first column electrode;
selectively operable means for switching for permitting selective electrical connection from each first column portion to the driving means;
and means for addressing simultaneously rows in more than one sub-matrix.
2. A display device according to Claim 1 comprising means for charging the capacitance of each first column portion in turn, the arrangement being such that a first column portion is charged when an electrical connection is provided from said a first column portion to the driving means.
3. A display device according to Claims 1 or 2 wherein switching means are provided between a first column portion and another first column portion, permitting connection in series of said plurality of first column portions.
4. A display device according to Claim 3 dependent on Claim 2, the arrangement being such that the first column portion furthest from the driving means is charged when all the switching means are in a mode providing electrical connection between a first column portion and another first column portion.
5. A display device according to Claims 1 or 2 wherein switching means permit selective electrical connection from each first column portion to an address line electrically connected to the driving means.
EP88310086A 1987-11-04 1988-10-27 Display device Expired - Lifetime EP0315365B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT88310086T ATE103092T1 (en) 1987-11-04 1988-10-27 DISPLAY DEVICE.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8725824 1987-11-04
GB878725824A GB8725824D0 (en) 1987-11-04 1987-11-04 Display device

Publications (3)

Publication Number Publication Date
EP0315365A2 true EP0315365A2 (en) 1989-05-10
EP0315365A3 EP0315365A3 (en) 1991-03-20
EP0315365B1 EP0315365B1 (en) 1994-03-16

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EP88310086A Expired - Lifetime EP0315365B1 (en) 1987-11-04 1988-10-27 Display device

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EP (1) EP0315365B1 (en)
AT (1) ATE103092T1 (en)
DE (1) DE3888451T2 (en)
GB (1) GB8725824D0 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0730256A1 (en) * 1995-03-03 1996-09-04 Motorola, Inc. Method of operating a display with parallel driving of pixel groups and structure of the same
WO2002039178A2 (en) * 2000-11-08 2002-05-16 Koninklijke Philips Electronics N.V. Display device
WO2002048780A2 (en) 2000-12-15 2002-06-20 Koninklijke Philips Electronics N.V. Active matrix device with reduced power consumption
WO2004066251A1 (en) * 2002-05-24 2004-08-05 Koninklijke Philips Electronics N.V. Electrophoretic display device and driving method therefor
US7023419B2 (en) * 2000-12-30 2006-04-04 Lg.Philips Lcd Co., Ltd. Liquid crystal display device
US7215311B2 (en) * 2001-02-26 2007-05-08 Samsung Electronics Co., Ltd. LCD and driving method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0105767A1 (en) * 1982-08-26 1984-04-18 Commissariat A L'energie Atomique Method of controlling a matrix display
GB2139795A (en) * 1982-12-28 1984-11-14 Citizen Watch Co Ltd Method of driving liquid crystal matrix display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0105767A1 (en) * 1982-08-26 1984-04-18 Commissariat A L'energie Atomique Method of controlling a matrix display
GB2139795A (en) * 1982-12-28 1984-11-14 Citizen Watch Co Ltd Method of driving liquid crystal matrix display

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOLECULAR CRYSTALS & LIQUID CRYSTALS, vol. 139, nos. 1-2, 1986, pages 81-101, Montreux, CH; E. KANEKO: "Directly addressed matrix liquid crystal display panel with high information content" *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0730256A1 (en) * 1995-03-03 1996-09-04 Motorola, Inc. Method of operating a display with parallel driving of pixel groups and structure of the same
WO2002039178A2 (en) * 2000-11-08 2002-05-16 Koninklijke Philips Electronics N.V. Display device
WO2002039178A3 (en) * 2000-11-08 2003-12-24 Koninkl Philips Electronics Nv Display device
WO2002048780A2 (en) 2000-12-15 2002-06-20 Koninklijke Philips Electronics N.V. Active matrix device with reduced power consumption
WO2002048780A3 (en) * 2000-12-15 2002-09-12 Koninkl Philips Electronics Nv Active matrix device with reduced power consumption
US6624865B2 (en) 2000-12-15 2003-09-23 Koninklijke Philips Electronics N.V. Active matrix device with reduced power consumption
US7023419B2 (en) * 2000-12-30 2006-04-04 Lg.Philips Lcd Co., Ltd. Liquid crystal display device
US7215311B2 (en) * 2001-02-26 2007-05-08 Samsung Electronics Co., Ltd. LCD and driving method thereof
WO2004066251A1 (en) * 2002-05-24 2004-08-05 Koninklijke Philips Electronics N.V. Electrophoretic display device and driving method therefor

Also Published As

Publication number Publication date
ATE103092T1 (en) 1994-04-15
DE3888451T2 (en) 1994-09-29
DE3888451D1 (en) 1994-04-21
EP0315365A3 (en) 1991-03-20
EP0315365B1 (en) 1994-03-16
GB8725824D0 (en) 1987-12-09

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