EP0304363A1 - Leistungsregler, insbesondere für Flugplatzbeleuchtung - Google Patents

Leistungsregler, insbesondere für Flugplatzbeleuchtung Download PDF

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Publication number
EP0304363A1
EP0304363A1 EP88401967A EP88401967A EP0304363A1 EP 0304363 A1 EP0304363 A1 EP 0304363A1 EP 88401967 A EP88401967 A EP 88401967A EP 88401967 A EP88401967 A EP 88401967A EP 0304363 A1 EP0304363 A1 EP 0304363A1
Authority
EP
European Patent Office
Prior art keywords
circuit
transformer
voltage
current
thyristor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88401967A
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English (en)
French (fr)
Inventor
Jean-Pierre Nicolas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ets AUGIER SA
Augier SAS
Original Assignee
Ets AUGIER SA
Augier SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ets AUGIER SA, Augier SAS filed Critical Ets AUGIER SA
Publication of EP0304363A1 publication Critical patent/EP0304363A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/12—Regulating voltage or current wherein the variable actually regulated by the final control device is ac
    • G05F1/14—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using tap transformers or tap changing inductors as final control devices
    • G05F1/16—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using tap transformers or tap changing inductors as final control devices combined with discharge tubes or semiconductor devices
    • G05F1/20—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using tap transformers or tap changing inductors as final control devices combined with discharge tubes or semiconductor devices semiconductor devices only
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/155—Coordinated control of two or more light sources

Definitions

  • the invention relates to an electronic power regulating device, capable of operating at constant current, or at constant voltage.
  • ferroresonance regulators are known. They allow the load current to be kept constant when the load's current demand varies, provided that the supply voltage remains constant. This advantage is paid for by different counterparts: an overvoltage appears at the output terminals when the loop is accidentally opened while the load impedance becomes infinite; the cosine phi degrades strongly at low values of the charge and at low glosses; finally the yield is acceptable only for the full load intensity.
  • Magnetic amplifier regulators are also known. They have a high reliability even in difficult climatic conditions. However, their cosine phi is strongly degrades at low gloss. There is also an open circuit overvoltage, less significant than for ferro-resonance regulators. Finally, the efficiency is only acceptable for the nominal current at full load.
  • sine wave regulators cut by controlled switches such as thyristors. They have the advantage of great simplicity of construction and good performance. It is however necessary to adapt the output of the regulator to the value of the load, which can take amplitudes of four quarters, three quarters, half, a quarter and an eighth, in the particular case of an airport beacon.
  • the drawback of these regulators lies in the creation of electromagnetic parasites which pollute the supply network, and also in the presence of rapid intensity variations which make the design of the protection circuits difficult.
  • the present invention aims to improve these latter types of regulators, in order to reduce the drawbacks.
  • One of the aims of the invention is thus to ensure that the efficiency and the power factor (cosine phi) practically do not degrade when passing from maximum brightness to lower gloss, in the case of airport signs, or when the load is reduced to its lowest value.
  • Another object of the invention is to obtain an absence of overvoltage at the opening of the charging circuit, on the one hand, as well as an absence of overcurrent harmful to lighting lamps, on the other hand.
  • the invention also aims to provide a regulator which is independent of the precise value of the mains supply voltage.
  • the invention also seeks to avoid any unnecessary fatigue lamps, thanks to a gradual rise in current.
  • the invention finally makes it possible to avoid the creation of parasites due to the steep current front, thanks to a sinusoidal shape as full as possible of the latter.
  • the subject of the present invention is a power current regulating device, of the type comprising: - an AC power supply input, - a first transformer whose primary is connected to this input and the secondary has staggered sockets, - at least one intermediate transformer similar to the first transformer, - a last transformer, the secondary of which is to be connected to the load to be regulated, through a device for measuring the load current or voltage, - a series of controlled switches suitable for connecting one of the taps of each transformer to the next, and means for controlling the conduction of these switches, one at a time per series, characterized in that these control means include: a comparator stage of the value measured by said member to a set value, - a generator of a clock signal controlled at start-up by the zero crossing of the mains voltage, and then by the zero crossing of the current in the load, - an up-down counting circuit capable of defining a count likely to evolve step by step according to the result of comparison, at the rate of the clock signal, and comprising as many up-down counters
  • the taps of the different transformers are chosen to obtain a given precision, substantially constant throughout the extent of the variation of the current value in measured voltage, and the digital base of the up-down counting and decoding circuit are chosen from preferably according to the distribution of the sockets of the different transformers.
  • the updating of the corresponding lock memory takes place during the actuation phase of said series of corresponding switches by the corresponding decoder means.
  • Each controlled switch preferably comprises two thyristors mounted head to tail and controlled one relative to its secondary socket, the other relative to the thyristor output common; these two thyristors are advantageously each associated with a control transistor, with an individual supply for those on the socket side and a common supply for those on the common side; the two transistors are preferably isolated by respective opto-couplers from the decoder means, these optocouplers being validated by respective square-wave signals of opposite polarity, synchronous with the supply current passing through zero.
  • the predetermined delay can normally have a low or zero value, and a higher value in the case where the control of a new thyristor is deferred, and this predetermined delay can have increasing values when going from the memory-lock of the high weights to those of lower weights.
  • the device according to the invention advantageously includes monitoring means to prohibit, in particular at the level of the decoder means, the taking into account of a modified command for the state of the thyristors in the event of a thyristor short-circuited, or of load in short circuit.
  • the monitoring means can be sensitive to the existence of a reverse voltage across the terminals of each thyristor.
  • a short-circuit state of two thyristors can lead to the use of a circuit breaker capable of protecting at least this series.
  • the device according to the invention comprises an auxiliary contactor, disposed between a determined socket of a transformer and the corresponding pair of thyristors, said contact being closed when the circuit breaker is open so as to ensure degraded operation of the device.
  • a state of under intensity can lead to the use of a main contactor, preferably after a time delay.
  • An overcurrent state can cause the up-downcounting circuit to be reset to zero, and, in the event of a persistent overcurrent, the main contactor can be activated.
  • the pulses of the clock signal are preferably eliminated when they lie outside a window of selected duration, of a few milliseconds, relative to the zero crossings of the voltage.
  • an AC mains supply at 220 Volts is available between the phase PH and neutral N terminals. It supplies all of the ETCP power transformers and switches via a contactor main CP under the control of a CCP circuit.
  • a first transformer T2 Downstream of the contactor is a first transformer T2, which can be an autotransformer, the secondary winding of which has five sockets, for example. These five sockets are respectively connected, from the lowest voltages to the highest voltages, to controlled switches IC0-2 to IC4-2, via a respective circuit breaker (DS0-2 to DS4-2).
  • the outputs of the controlled switches are connected to a common, to be applied to a resistance-capacitance filtering network noted RCP2, as well as to the primary of an autotransformer T1.
  • This one is mounted like the previous one with five controlled switches IC0-1 to IC4-1, a circuit breaker (DS0-1 to DS4-1) and a capacity resistance circuit RCP1, and a third autotransformer T0. It is mounted like the previous ones with controlled switches IC0-0 to IC4-0, a circuit breaker (DS0-0 to DS4-0) and a resistance-capacity network RCP0.
  • the staggering of the taps on the different transformers are defined to allow digital control, for example as follows: let e be the relative precision desired for regulation; we denote by K the difference between 1 and this precision (doubled if it is counted more and less).
  • U0 denotes the full nominal secondary voltage of transformer T0.
  • the intermediate sockets will then be chosen to supply the voltage U0xK, U0xK2, U0xK3 and U0xK4 in addition.
  • the sockets U2, U2xK25, U2xK50, U2xK75 and U2xK100 will be established.
  • Figure 1 also shows the TAC load matching transformer, the primary of which is supplied by the previous assembly, and the secondary of which supplies the load through an ICT current transformer, the secondary of which supplies, in series with a current ammeter.
  • table MA a second TIM measurement intensity transformer with two secondary.
  • Figure 1 shows the ELCG trigger control logic assembly consisting of: a CCD up-down circuit capable of defining a count capable of evolving step by step at the rate of the clock signal SH and according to the change CH and up / down U / D signals, - a CMV memory-lock circuit connected to the parallel outputs of the up-down counters and whose updating is effected by the action of an updating control signal ("strobe") ST.
  • a CCD up-down circuit capable of defining a count capable of evolving step by step at the rate of the clock signal SH and according to the change CH and up / down U / D signals
  • strobe updating control signal
  • This ST signal to take place: - either immediately after the clock signal if there is no change in counting or if the change corresponds to a reduction in voltage on the tap transformer, - either with a predetermined delay R if there is a change in metering and if this change corresponds to an increase in voltage on the tap transformer, a circuit of DMX demultiplexers (decoding means) connected to the outputs of the lock memories and whose own outputs are conditioned by inhibition signals INH whose delay time t starts immediately after the clock signal SH, - a CCG trigger control circuit connected to the outputs of the demultiplexers by means of opto-couplers and whose function is to actuate said series of switches.
  • the sampled measurement circuit CME, the brightness control circuit CCB, the sequential control circuit CCS, the thyristor monitoring circuit CST and the logic trigger control assembly ELCG constitute control means MC of the switches.
  • the predetermined delay R has a value of the order of 1 to 2 milliseconds and the duration of the time delay t of the trigger control signal, a value of the order of 5 milliseconds.
  • Figure 2 specifies this logic trigger control assembly by highlighting the three up-down counters CD-2, CD-1 and CD-0, as well as their upstream link with the comparison circuits and their downstream link with the lock memories MV-2, MV-1 and MV-0 respectively updated by the update control signals ST2, ST1 and ST0.
  • the count values are decoded by the DMX2, DMX1 and DMX0 demultiplexers under the respective control of the inhibition signals INH-2, INH-1, INH-0.
  • the decoded values X0 to X4 of each of the three counting groups are applied to the trigger control circuits of each series of controlled switches.
  • the composition of the logic control circuit shows: - a thyristor control logic under the control of signals 0K2, 0K1 and 0K0 coming from the thyristor monitoring circuits, - an update command MD of the lock memories under the control of the direction of counting change, - comparison circuits which generate the CH change, U / D rise / fall, RST reset signals, as well as other signals not mentioned in FIG. 2, such as overcurrent, undercurrent, immediate stop , especially.
  • FIGS. 3 a and 3 b give details of the CCS sequential control circuits.
  • the voltage zero detection circuit DZT From the voltage signal SU, emitted by the secondary of the voltage transformer TU, the voltage zero detection circuit DZT supplies the two signals A and B in slots of opposite phase respectively which will also be used in the control assembly triggers (defined during the explanation of Figure 6).
  • the sum of signals A and B controls a time window of 1 to 2 milliseconds starting at zero voltage.
  • the clock signal SH is the logic output of a monostable circuit with forcing at zero MT1.
  • the triggering of this monostable is ensured by the zero crossing of the voltage (start of the window). It drops out after 1 to 2 milliseconds (system initialization), or before, as soon as a zero crossing of the current is indicated by the signal Io (steady state).
  • the filtering of the clock pulses by a window of selected duration has the advantage of eliminating the parasitic pulses likely to cause the unwanted control of another pair of thyristors by risking creating a short circuit between taps of the same transformer .
  • the signal SH supplies the down-counters on the one hand and, on the other hand, a series of staggered timers intended to produce the signals SAMV-2, SAMV-1 and SAMV-0, as well as the signals SCG-2, SCG -1 and SCG-0, as shown in Figure 3a.
  • This series of staggered timers is produced by a timer circuit D2.
  • FIG. 3b represents the simplification introduced in the production of the preceding signals when the thyristor monitoring is removed.
  • FIG. 4 gives the details of the CME sampled measurement circuits.
  • the current measurement circuit CMC From the current signal IM1, the current measurement circuit CMC provides a proportional DC voltage signal which will be divided into a brightness selection circuit CSB under the control of the brightness control circuit CCB; the effective value of this resulting signal will be worked out in the effective value circuit CVE. At each clock signal, the new value of the sampled measurement signal SME will be available for the comparison circuits.
  • CMC, CSB, CCB, CVE circuits constitute a compa rator (CN0).
  • FIG. 5 gives details of the CST thyristor monitoring circuits.
  • the secondary P4 socket of the transformer concerned is assumed to be the one providing the highest voltage.
  • the taps are then considered in descending order until the tap P0 which provides the lowest voltage, the other terminal of the secondary being noted C.
  • thyristor T4 + mounted conductor between P4 and C
  • thyristor T4- mounted conductor between C and P4.
  • the triggers of these two thyristors are moreover connected to the emitters of the transistors Q4 + and Q4-, and these transistors, of the NPN type, are respectively controlled between bases and emitters by optocouplers 0C4 + and 0C4-. The whole of this command constitutes the controlled switch IC4.
  • the transistors Q4-, Q3-, Q2-, Q1 and Q0- have respective supplies AL4, AL3, AL2, AL1 and AL0, these supplies being referred to the voltages of the sockets P4 to P0.
  • the other transistors can have a common supply ALC compared to common C.
  • the 0C optocouplers are validated by a voltage A if they have the suffix + or by a voltage B if they have the suffix -. These voltages A and B, generated as described above, are sector synchronous and of opposite polarity.
  • each pair of opto-couplers like 0C4 is supplied by a respective output from the DMX demultiplexer.
  • a reset of the up-down counters is carried out with execution of this order by the thyristors; and if the overcurrent state persists, the main contactor CP opens.
  • 0n protects the thyristors of the same series against internal short circuits by using local circuit breakers placed between the taps of each transformer and the thyristors.
  • a direct connection is reserved between a determined tap of the transformer T2 and the corresponding thyristor pair (for example IC2-2), whose trigger control is automatically performed by an auxiliary contact linked to the circuit breaker group. This auxiliary contact is closed when the circuit breaker group is open.
  • This arrangement allows degraded operation at three levels (because there are three transformers T2, T1, T0), the last level corresponding to the supply of the output transformer by a fraction of the supply voltage of the network.
  • the device includes monitoring means to prohibit, in particular at the level of the decoder means, the taking into account of a modified thyristor control, if the thyristor which has just operated is in short -circuit.
  • the monitoring means used for this purpose may be of a different nature to characterize the absence of a short-circuit of the last thyristor having led: either the existence of a reverse voltage at the terminals of the thyristor, or the cancellation of the current at the end of time Tq, i.e. the presence of an overvoltage across the load when the current is canceled.
  • Tq a reverse voltage at the terminals of the thyristor
  • the clock signal SH is obtained from the zero crossing of the line voltage signal and triggers all the sequential commands which authorize the updating of the lock memories by the update command signal and the trigger control via the demultiplexers. for the entire duration of the reverse inhibition signal.
  • the thyristors connected to the lowest taps of the transformers are conducting and the smallest voltage is applied to the transformer adaptation of TAC loads: this results in a generally very low current in the load but nevertheless sufficient to supply current measurement signals IM1 and IM2.
  • IM2 will make it possible to control the clock signal SH at the zero crossing of the current and from there the incrementation of the up-counters will occur at each alternation of the current until the moment when the value of the current has reached the setpoint value.
  • the regulator stabilizes unless the value of the mains voltage changes enough to vary the load current outside its margin of precision, or if the load changes enough to produce the same effects, or finally if the selected brightness selection is changed.
  • FIGS. 7 and 8 A more detailed operation of the device will be described on the basis of the time diagrams represented in FIGS. 7 and 8, these figures being respectively characteristic of the operation "with” or “without” monitoring of the thyristors.
  • the left-hand side illustrates a configuration in which the up-down counter 0 has increased by one unit while the other two are not modified.
  • the middle part of the figures illustrates a configuration in which the up-down counter 0 decreases by one unit, while the up-down counter 1 increases by one and the up-down counter 2 is not modified.
  • the right-hand part illustrates a configuration in which the up-down counter 0 has decreased by one unit, the up-down counter 1 decreases by a unit and the up-down counter 2 increases by a unit.
  • the direction of variation of each up-down counter is determined from the overall value of the up-down counting circuit after the change, knowing that the overall direction of variation (increase or decrease) is known and no change is made. than one unit at a time.
  • the top diagram illustrates (very schematically) the current through the load.
  • the three lines below illustrate the three change signals CH-2, CH-1, CH-0 respectively.
  • the next line illustrates the SH clock signal.
  • the following three groups of three lines respectively illustrate, for the three up-downcounters i the signal 0Ki, the muting signal INH-i and the update control signal ST-i.
  • the clock signal SH appeared at the zero crossing of the current.
  • the 0K2 signal is sent to signal that there are no thyristors short-circuited (DV off-hook on the first line in Figure 7) and that one could control.
  • the INH-2 trigger control order takes place 50 microseconds after the end of the 0K2 signal.
  • the update control signal ST-2 takes place immediately after the rise of the signal SH because there is no change in counting.
  • the update control signal ST-0 will be emitted, during the actuation phase series of switches by demultiplexers (DMX), that is to say during the low state phase of the signal INH-0.
  • DMX demultiplexers
  • the ST-0 signal is shifted by half a millisecond relative to the fall of the INH-0 signal, which ensures better voltage continuity in the regulator.
  • the low state phase of the INH-i signal lasts 5 ms.
  • the rise in signal ST-0 corresponds to a small current fault across the load.
  • the update control signal is not shifted when the value of the corresponding up-down counter is stationary or decreases.
  • FIG. 8 illustrates the unattended operation of the thyristors, and is simplified compared with FIG. 7. The interpretation of the signals represented is identical to that of FIG. 7.
  • This invention can be the subject of various variants.
  • the extinction state of the thyristors can also be detected by the cancellation of the voltage between the common output C and the neutral, or by the cancellation of the current in each thyristor concerned.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
EP88401967A 1987-07-31 1988-07-28 Leistungsregler, insbesondere für Flugplatzbeleuchtung Withdrawn EP0304363A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8710923 1987-07-31
FR8710923A FR2618921B1 (fr) 1987-07-31 1987-07-31 Regulateur de puissance, notamment pour le balisage d'aeroports

Publications (1)

Publication Number Publication Date
EP0304363A1 true EP0304363A1 (de) 1989-02-22

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EP88401967A Withdrawn EP0304363A1 (de) 1987-07-31 1988-07-28 Leistungsregler, insbesondere für Flugplatzbeleuchtung

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US (1) US4816738A (de)
EP (1) EP0304363A1 (de)
CA (1) CA1289183C (de)
FR (1) FR2618921B1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2070735A2 (es) * 1993-04-15 1995-06-01 Ingequr S A Variador de tension estatico para regulacion de consumo de redes de alumbrado, con variacion y regulacion de la tension de salida y limitacion de intensidad.
ES2109846A1 (es) * 1994-04-27 1998-01-16 Salicru Roses Jacinto Perfeccionamientos en los estabilizadores de tension aplicables a instalaciones de iluminacion.

Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
US5581229A (en) * 1990-12-19 1996-12-03 Hunt Technologies, Inc. Communication system for a power distribution line
US5136233A (en) * 1991-04-09 1992-08-04 Iowa-Illinois Gas And Electric Company Means and method for controlling elecrical transformer voltage regulating tapchangers
US5642290A (en) * 1993-09-13 1997-06-24 Siemens Energy & Automation, Inc. Expansion chassis for a voltage regulator controller
US5596263A (en) * 1993-12-01 1997-01-21 Siemens Energy & Automation, Inc. Electrical power distribution system apparatus-resident personality memory module
US6078148A (en) * 1998-10-09 2000-06-20 Relume Corporation Transformer tap switching power supply for LED traffic signal
US11557430B2 (en) * 2020-02-19 2023-01-17 Eaton Intelligent Power Limited Current transformer powered controller

Citations (5)

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Publication number Priority date Publication date Assignee Title
US3818321A (en) * 1973-04-09 1974-06-18 Wilorco Inc Voltage regulator
US3921059A (en) * 1974-03-22 1975-11-18 Forbro Design Corp Power supply incorporating, in series, a stepped source and a finely regulated source of direct current
US3970918A (en) * 1975-01-13 1976-07-20 Edward Cooper High speed, step-switching AC line voltage regulator with half-cycle step response
EP0157689A1 (de) * 1984-03-19 1985-10-09 Ets. AUGIER S.A. Verstellbarer Wechselspannungsgenerator
US4623834A (en) * 1984-07-06 1986-11-18 Oneac Corporation Dual programmable response time constants for electronic tap switching line regulators

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Publication number Priority date Publication date Assignee Title
US3603971A (en) * 1968-08-06 1971-09-07 Perkin Elmer Corp Apparatus for converting between digital and analog information
CA939001A (en) * 1971-07-02 1973-12-25 Westinghouse Canada Limited Lighting control system
GB2125194A (en) * 1982-08-05 1984-02-29 Plessey Co Plc Regulated DC power supply

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818321A (en) * 1973-04-09 1974-06-18 Wilorco Inc Voltage regulator
US3921059A (en) * 1974-03-22 1975-11-18 Forbro Design Corp Power supply incorporating, in series, a stepped source and a finely regulated source of direct current
US3970918A (en) * 1975-01-13 1976-07-20 Edward Cooper High speed, step-switching AC line voltage regulator with half-cycle step response
EP0157689A1 (de) * 1984-03-19 1985-10-09 Ets. AUGIER S.A. Verstellbarer Wechselspannungsgenerator
US4623834A (en) * 1984-07-06 1986-11-18 Oneac Corporation Dual programmable response time constants for electronic tap switching line regulators

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2070735A2 (es) * 1993-04-15 1995-06-01 Ingequr S A Variador de tension estatico para regulacion de consumo de redes de alumbrado, con variacion y regulacion de la tension de salida y limitacion de intensidad.
ES2109846A1 (es) * 1994-04-27 1998-01-16 Salicru Roses Jacinto Perfeccionamientos en los estabilizadores de tension aplicables a instalaciones de iluminacion.

Also Published As

Publication number Publication date
US4816738A (en) 1989-03-28
FR2618921B1 (fr) 1989-12-08
CA1289183C (en) 1991-09-17
FR2618921A1 (fr) 1989-02-03

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