EP0258285A1 - Methods for fabricating transistors and mos transistors fabricated by such methods - Google Patents
Methods for fabricating transistors and mos transistors fabricated by such methodsInfo
- Publication number
- EP0258285A1 EP0258285A1 EP19870900849 EP87900849A EP0258285A1 EP 0258285 A1 EP0258285 A1 EP 0258285A1 EP 19870900849 EP19870900849 EP 19870900849 EP 87900849 A EP87900849 A EP 87900849A EP 0258285 A1 EP0258285 A1 EP 0258285A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- insulating layer
- polycrystalline
- amorphous
- seed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000009331 sowing Methods 0.000 abstract 2
- 238000010899 nucleation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 238000001953 recrystallisation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- MUJOIMFVNIBMKC-UHFFFAOYSA-N fludioxonil Chemical compound C=12OC(F)(F)OC2=CC=CC=1C1=CNC=C1C#N MUJOIMFVNIBMKC-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Definitions
- This invention relates to methods for fabricating transistors, and to metal oxide silicon (MOS) transistors fabricated by such methods.
- MOS metal oxide silicon
- a conventional type of transistor structure comprises a positively doped bulk silicon structure which includes source and drain regions in the form of diffused N conductivity type regions spaced apart in a silicon substrate.
- a gate electrode is formed over the silicon substrate between the source and drain regions. This structure has the disadvantage that undesirable capacitances exist between the source and drain regions and the substrate.
- a silicon on saphire (SOS) transistor comprises a silicon layer having spaced apart source and drain regions on an insulating layer of saphire.
- SOS silicon on saphire
- Such a transistor attempts to reduce undesirable capacitances by putting the insulating layer under the device but this isolates the active channel region resulting in the device taking up an undefined potential which can modify the transistor action. Although this can be avoided by including a substrate contact on the top surface of the device, such a contact concerns that the device takes up more space.
- a further conventional type of transistor which is subject to the same disadvantages as the SOS transistor is a silicon on insulator (SOI) transistor.
- SOI silicon on insulator
- Such a device comprises an insulating layer formed on a silicon 5 substrate.
- a further silicon layer which includes source and drain regions is formed on the insulating layer.
- a conventional method of fabricating the silicon on insulator (SOI) transistor structures comprises forming an insulating layer on a silicon substrate and etching seed
- a layer of polysilicon is then formed over the insulating layer and over the seed window.
- the polysilicon is then recrystallised (solid phase epitaxy) by way of a recrystallisation process, such as the one described in H. . Lam IEDM Technical Digest
- Source and drain regions are then formed in the recrystallised polysilicon layer by, for example, an implant doping process and a gate is formed between the source and the drain. In this structure, the gate overlies the insulating layer.
- the present invention is directed to a method for fabricating transistors which alleviates the afore mentioned disadvantages, and MOS transistors fabricated by such methods, which transistors have relatively low capacitances associated therewith.
- a metal oxide silicon (MOS) transistor comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the other side of the seed window, and a gate between the source and the drain, the gate overlying the seed window.
- MOS metal oxide silicon
- the source and the drain may be diffused N type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insulator.
- a method for fabricating a metal oxide silicon (MOS) transistor comprising: forming an insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the seed window(s); recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed window(s); isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining
- amorphous or polycrystalline semiconductor layer forming a source on one side of the seed window over the insulating layer, a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed
- the step of forming the insulating layer having one or more seed windows ? ay comprise forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed window(s), through the
- recesses may be formed in the semiconductor substrate and the insulating layer may be formed in the recesses, the seed window(s) and the insulating layer thereby having a substantially flat
- the isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window region(s) may be effected by etching away the non- recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or
- the drain and the source may be formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
- the step of recrystallising the amorphous or polycrystalline layer may be by solid phase epitaxy or by direct epitaxy.
- direct epitaxy the amorphous polycrystalline layer recrystallises in the region of the seed window as the layer is deposited over the insulating layer and the seed window.
- Embodiments of the present invention are advantageous in that they enable the fabrication of a novel MOS transistor structure having relatively low capacitances associated therewith. In addition, they provide for the elimination of the need to waste space due to adandonment of seed window regions by incorporating the seed window regions into the MOS transistor structures. This saving of space can lead to increased packing density.
- Figures la to le show fabrication stages for a MOS transistor structure embodying the present invention.
- FIGS 2a to 2e show fabrication stages of an alternative MOS transistor structure embodying the present invention.
- silicon dioxide is formed on a single crystal semiconductor substrate 2 such as silicon.
- a hole is etched through the insulating layer 1 to form a seed window 3; although only one seed window 3 is shown, a plurality of seed windows may be formed.
- amorphous or polycrystalline semiconductor such as polysilicon 4
- polysilicon 4 is- hen deposited over the insulating layer 1 and in the seed window 3 ⁇ as illustrated in Figure lb.
- the polysilicon 4 may be subjected to, for example, furnace treatment to cause solid phase epitaxy which grows single crystal silicon regions in the polysilicon around the seed window
- the substrate as a seed.
- the single crystal silicon region so formed is illustrated in Figure lc by reference numeral 5.
- the recrystallisation may be induced by laser treatments, electron beam treatments or quartz halogen lamps.
- the seed window 3 is to correspond to an active region of a gate of a metal oxide silicon (MOS) transistor to be formed in the seed window 3 region.
- MOS metal oxide silicon
- the next stage in the method of fabrication of the MOS transistor is to etch away field regions 6 of the MOS transistor, the resulting structure being illustrated in Figure Id.
- the field region 6 may be formed by converting the polysilicon layer in these regions into an insulator by oxidation.
- Source and drain regions 7 and 8 are formed in the regions of the polysilicon layer which overlie the insulating layer 1, for example, by furnace doping or implant.
- the source region 7 and the drain region 8 are formed on opposite sides of the seed window 3 and may be of N or P conductivity type.
- a gate electrode, comprising a dielectric layer 9 and a conducting or semiconducting layer 10 is formed over, the seed window 3 as shown in Figure le. The gate electrode may be formed before the source and drain regions 7 and 8 are formed.
- An MOS transistor formed in the above described way, such as the one illustrated in Figure le, is advantageous in that the benefits of silicon on insulator (SOI) technology (i.e. low capacitances) may be achieved for MOS transistors while using a simple fabrication process.
- SOI silicon on insulator
- the relatively low capacitance achievable in MOS transistors using the above described fabrication method exist since the fabrication method enables the MOS transistor to be formed in islands of good quality silicon which are connected to the substrate in the gate region, but have their source and drain regions over the initially formed oxide layer. Additionally, the transistors
- the field oxide 5 fabricated in this way may have low field capacitance because the field oxide may be made up of the oxidised polysilicon plus the original oxide.
- the insulating layer 1 is formed in recesses which have been etched in the single crystal semiconductor substrate 2,-vhich results in the seed window 3 and the insulating layer 1 having a substantially flat surface ( Figure 2a).
- the polysilicon 4 is then formed on the
- Source and drain regions 7 and 8 are then formed in a similar manner to that described earlier and the structure is then isolated, in this case, by converting the field regions to oxide 11 ( Figure 2d).
- Source and drain electrodes S, D are connected to the respective source and
- the steps for fabricating transistors, and the MOS transistors described above are intended to be examples and it is envisaged that variations may be adopted without departing from the scope of the present invention.
- the step of recrystallisation by solid phase epitaxy may be combined with the isolation step which involves oxidation of the field regions.
Abstract
Un transistor métal-oxyde-silicium (MOS) comprend un substrat semi-conducteur (2), une couche isolante (1) sur le substrat, et une fenêtre d'ensemencement (3) dans la couche isolante (1), ladite fenêtre d'ensemencement (3) étant en communication avec le substrat semi-conducteur. Le transistor MOS comprend également une couche (4) de semi-conducteur recristallisé amorphe ou polycristallin qui recouvre la couche isolante (1) au moins dans la région de la fenêtre d'ensemencement et qui est en contact avec le substrat semi-conducteur (2). Une source est formée dans la couche (4) de semi-conducteur recristallisé amorphe ou polycristallin sur la couche isolante (1) d'un côté de la fenêtre d'ensemencement (3), et un drain est formé dans la couche (4) de semi-conducteur recristallisé amorphe ou polycristallin sur l'autre côté de la fenêtre d'ensemencement (3), et une électrode de porte comprenant une couche électrique (9) et une couche conductrice ou semi-conductrice (10) est formée entre la source et le drain.A metal-oxide-silicon transistor (MOS) comprises a semiconductor substrate (2), an insulating layer (1) on the substrate, and a sowing window (3) in the insulating layer (1), said window d seed (3) being in communication with the semiconductor substrate. The MOS transistor also comprises a layer (4) of amorphous or polycrystalline recrystallized semiconductor which covers the insulating layer (1) at least in the region of the seed window and which is in contact with the semiconductor substrate (2 ). A source is formed in the layer (4) of amorphous or polycrystalline recrystallized semiconductor on the insulating layer (1) on one side of the sowing window (3), and a drain is formed in the layer (4) of amorphous or polycrystalline recrystallized semiconductor on the other side of the seeding window (3), and a door electrode comprising an electrical layer (9) and a conductive or semiconductor layer (10) is formed between the source and drain.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08601830A GB2185851A (en) | 1986-01-25 | 1986-01-25 | Method of fabricating an mos transistor |
GB8601830 | 1986-01-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0258285A1 true EP0258285A1 (en) | 1988-03-09 |
Family
ID=10591944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19870900849 Withdrawn EP0258285A1 (en) | 1986-01-25 | 1987-01-19 | Methods for fabricating transistors and mos transistors fabricated by such methods |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0258285A1 (en) |
JP (1) | JPS63502544A (en) |
GB (1) | GB2185851A (en) |
WO (1) | WO1987004563A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
US5021119A (en) * | 1987-11-13 | 1991-06-04 | Kopin Corporation | Zone-melting recrystallization process |
US5453153A (en) * | 1987-11-13 | 1995-09-26 | Kopin Corporation | Zone-melting recrystallization process |
CN1395316A (en) * | 2001-07-04 | 2003-02-05 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
US20230420546A1 (en) * | 2022-06-24 | 2023-12-28 | Nxp Usa, Inc. | Transistor with current terminal regions and channel region in layer over dielectric |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3764413A (en) * | 1970-11-25 | 1973-10-09 | Nippon Electric Co | Method of producing insulated gate field effect transistors |
JPS49112574A (en) * | 1973-02-24 | 1974-10-26 | ||
JPS54881A (en) * | 1977-06-03 | 1979-01-06 | Fujitsu Ltd | Semiconductor device |
US4269631A (en) * | 1980-01-14 | 1981-05-26 | International Business Machines Corporation | Selective epitaxy method using laser annealing for making filamentary transistors |
JPS5861622A (en) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | Manufacture of single crystal thin film |
EP0077737A3 (en) * | 1981-10-19 | 1984-11-07 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Low capacitance field effect transistor |
US4476475A (en) * | 1982-11-19 | 1984-10-09 | Northern Telecom Limited | Stacked MOS transistor |
JPS59195871A (en) * | 1983-04-20 | 1984-11-07 | Mitsubishi Electric Corp | Manufacture of metal oxide semiconductor field-effect transistor |
-
1986
- 1986-01-25 GB GB08601830A patent/GB2185851A/en not_active Withdrawn
-
1987
- 1987-01-19 WO PCT/GB1987/000030 patent/WO1987004563A1/en not_active Application Discontinuation
- 1987-01-19 EP EP19870900849 patent/EP0258285A1/en not_active Withdrawn
- 1987-01-19 JP JP50089087A patent/JPS63502544A/en active Pending
Non-Patent Citations (1)
Title |
---|
See references of WO8704563A1 * |
Also Published As
Publication number | Publication date |
---|---|
GB2185851A (en) | 1987-07-29 |
JPS63502544A (en) | 1988-09-22 |
WO1987004563A1 (en) | 1987-07-30 |
GB8601830D0 (en) | 1986-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19870911 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR GB IT LI LU NL SE |
|
17Q | First examination report despatched |
Effective date: 19891027 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19900307 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: OAKLEY, RAYMOND, EDWARD |