EP0244280B1 - Video attributes decoder for a colour or monochrome display in a teletext mode or in a high-definition alphanumerical mode - Google Patents

Description

The present invention relates to a video attribute decoder for color or monochrome display in videotex or alphanumeric mode, in high definition.

There are video attribute decoders for color or monochrome display in high definition alphanumeric mode which are generally used in so-called professional terminals. The video monitors of these alphanumeric terminals allow the display of 25 lines of 80 characters.

There are also so-called consultation terminals used in videotex with a low definition alphamotic operating mode allowing 25 rows of 40 columns to be displayed.

The object of the present invention according to claim is to propose a video attribute decoder for display in high definition alphanumeric mode (so-called professional quality) and semigraphic display (videotex type).

This first aim is achieved by the fact that the video attribute decoder for color or monochrome display in videotex mode or in high definition alphanumeric mode comprises a clock circuit, a configuration register, a character attribute register, a line attribute register, an attribute decoding circuit connected to these different registers, a character masking circuit, a serializer connected to this masking circuit and to the clock circuit, a background inversion circuit, a character color control circuit and a background color control circuit connected at the input to the attribute decoder circuit and at the output to the monitor cannon multiplexing and control circuit, is characterized in that the output of the serializer is sent to a point widening circuit and in that it further comprises a double height logic circuit connected on the one hand to the line attribute register and to another e goes to the selection lines of a character slice in the character generator read-only memory.

In the case of a professional alphanumeric type terminal, a series of pulses called "pixels" is sent to the monitor so as to form the characters (see for example document EP-A 0 084 122 which describes a terminal with a decoder video attributes for color display). For a professional terminal a pixel lasts 40 ns. In this case the phosphor of the monitor screen does not respond instantly but with a time lag and more, it is more difficult to turn on than turn off. The consequence of this disadvantage of operation of the monitor screen is that, in the characters having vertical portions and horizontal portions, the brightness is not the same. Indeed in the horizontal part where the pixels are joined we arrive at the maximum brightness of the tube, while in the vertical parts the brightness appears weaker. When we know that a pixel represents on a professional terminal a dimension of a quarter of a millimeter on the screen, we understand that this drawback becomes major for a professional terminal. However, this drawback does not exist in low-end devices such as consultation terminals because the number of dots on the screen is much lower (480 pts instead of 800) and therefore the dots are wide enough to that the fault does not appear.

A second object of the invention is therefore to propose a video attribute decoder which overcomes this drawback.

The second goal is achieved by the fact that the point enlargement circuit makes it possible to widen the point by a determined value whatever the display mode adopted direct or reverse.

According to another characteristic, the point widening circuit consists of an inverter of a clock signal, flip-flops for delaying the serialization signals of the data and the inverted data, and of a combinational logic according to the mode d display adopted data signals, reverse data and the same delayed signals.

A third object of the invention is to propose a video attribute decoder which in operation in videotex mode allows the display of alphanumeric characters in double height and this regardless of the type of monitor used and the number of slices that comprises. a character.

The third object of the invention is achieved by the fact that the double height circuit makes it possible to double the height of the characters regardless of the number of character slots contained in a character of normal height.

According to another characteristic, the double height logic circuit comprises means for memorizing the address of the last section of the character, means for generating a constant value and adding this constant value to the signal representative of the address of the section of character and halve the result to form the address of the slice of the double height character being processed.

• - la figure 1 représente la configuration typique d'une interface d'affichage vidéo entre le bus (10) d'un microprocesseur et le moniteur d'affichage ;
• - la figure 2 représente le circuit décodeur d'attributs pour affichage vidéo utilisé dans la configuration de la figure 1 ;
• - la figure 3 représente le schéma électronique du circuit de génération des signaux permettant l'affichage des caractères double hauteur ;
• - la figure 4 et la figure 5 représentent le schéma du circuit électronique permettant l'élargissement du point de génération des caractères ;
• - la figure 6 représente l'octet de configuration ;
• - les figures 7 et 8 représentent deux octets de codage des caractères en mode alphanumérique respectivement monochrome et couleur ;
• - les figures 9 et 10 représentent les deux octets de codage du caractère en mode vidéotex respectivement alphanumérique et semigraphique ;
• - la figure 11 représente les deux octets de codage d'un caractère délimiteur ;
• - la figure 12 représente un caractère simple hauteur et un caractère double hauteur ;
• - la figure 13 représente les diagrammes temporels des signaux utilisés dans le circuit d'élargissement du point.

Other characteristics and advantages of the present invention will appear more clearly on reading the description below made with reference to the appended drawings in which:

• - Figure 1 shows the typical configuration of a video display interface between the bus (10) of a microprocessor and the display monitor;
• - Figure 2 shows the attribute decoder circuit for video display used in the configuration of Figure 1;
• - Figure 3 shows the electronic diagram of the signal generation circuit for displaying double height characters;
• - Figure 4 and Figure 5 show the diagram of the electronic circuit allowing the widening of the character generation point;
• - Figure 6 shows the configuration byte;
• - Figures 7 and 8 show two bytes of character encoding in alphanumeric mode respectively monochrome and color;
• - Figures 9 and 10 show the two character coding bytes in videotex mode, alphanumeric and semigraphic respectively;
• - Figure 11 shows the two coding bytes of a delimiter character;
• - Figure 12 shows a single height character and a double height character;
• - Figure 13 shows the time diagrams of the signals used in the point widening circuit.

A conventional interface between a video monitor (not shown) and a buz (10) of a microprocessor (not shown) is constituted by a video display controller circuit (11) which can be constituted in a known manner by a circuit marketed by the company SIGNETICS under the reference SCN 2674 or by the circuit marketed by the MOTOROLA company under the reference MC2674. This box (11) communicates with the data, address and control bus (10) of the microprocessor and receives on the other hand by the line (250) the character clock signal coming from the video attribute decoder circuit ( 20). This video attribute decoder circuit (20) receives synchronization signals from the box 11 via the 5 lines (110): HSYNC, horizontal synchronization signal, VSYNC, vertical synchronization signal, BLANK, erasure signal, CURSOR, signal cursor, RESET, system reset signal. This circuit (20) also receives by the 8 lines (320, 330), the line control signals coming from the display address outputs of the video display controller (11). The other display address lines are sent, on the one hand, to a first 2k-byte RAM (12) constituting the character memory and on the other hand to a second 2k- RAM (13) byte constituting the attribute memory. The character random access memory (12) communicates by its eight data lines (160) with on the one hand a door assembly (16) giving access to the bus (10), and on the other hand with a door assembly (14 ) giving access to the seven lines (140) for selecting the address of the 256 characters contained in a read-only memory (15) constituting the character generator. This read only memory (15) has a capacity of 8k-byte. The highest weight data line (120) from the memory (12) is connected to the input (220) of the video attribute decoder circuit (20). the eight data lines of the attribute random access memory (13) are connected by the eight attribute lines (130) to the decoder circuit (20). These eight lines are also connected to a door (17) for communication with the bus (10) of the microprocessor. The decoder circuit (20) transmits by the four outputs (LCO to LC3) of the circuit (313) the signals for selecting the range of characters stored in the character generator (15). The character generator (15) stores for each character a representation according to a matrix of points which can be constituted by a set of nine lines each comprising for example ten points. The logical value 0 or 1 of each of these points enables a bright spot or a dark spot to be reproduced on the video screen. We call character range the set of points of a line of the character matrix. As will be seen below, the character slices can have a width varying between 8 and 10 points, this so as to be able, depending on the monitor used, to improve the definition of the characters and a character can consist of 9 to 16 slices. Finally the circuit (20) receives on its input (253) the output of a clock (18) operating at the frequency of 25 MHz and delivering pulses corresponding to the width of a point. This point clock signal is called (DCLK).

FIG. 2 represents a diagram of the various functions performed by the video attribute decoding circuit. This circuit includes a circuit (25) dividing the clock signal supplied on the input (253) by the output of the housing (18) delivering the signal (DCLK) of the 25 MHz clock. This circuit (25) makes it possible to predivide this signal (DCLK) by two, according to the signal (DL) supplied on the input (252) by the output (210) of the attribute decoding circuit (21). This signal (DL) supplied to the input (252) indicates that the character must be double width. Then the pre-divided clock signal is itself divided by 8, 9 or 10 depending on the signal supplied on the input (251) of the circuit (25), signal delivered by the output (230) of the circuit (23) constituting the configuration register. This clock circuit delivers on the line (250) the signal (CCLK), character clock signal, which is sent to the corresponding input of the video display controller (11). The output (254) of the clock divider circuit (25) delivers the signal (SHCLK) which is the serialization clock signal, which signal is sent to the input (400) of the serializer circuit (40). The output (255) of the circuit (25) is sent on the one hand to the input (211) of the attribute decoding circuit (21) and on the other hand to the input (311) of the circuit (31) of double height logic. The signal (VCCLK) delivered by the output (255), is the clock signal of the video characters. Finally the signal (CCLK) delivered by the output (250) is also sent to the input (312) of the circuit (31) of the double height logic.

The eight output lines (150) of the read-only memory (15) representing the character codes (CO to C7) are sent to the circuit (41) constituting the mask logic. The output (411) of this circuit (41) is connected to the input (401) of the serializer circuit (40). An input (412) of the mask circuit (41) receives the output (212) of the attribute decoding circuit (21). The output (402) of the serializer circuit (40) is connected to the input (540) of the point widening circuit (54). The output (542) of this circuit (54) is connected to the input (501) of a multiplexing circuit (50). A screen inversion circuit (53) sends the background inversion signal, via its outputs (534) and (530) to the input (500) of a multiplexing circuit (50) . An input (533) of this circuit (53) receives the serialization clock signal (SHCLK). The input (532) of this circuit (53) receives the output (213) of the attribute decoding circuit (21). An output (531) of the circuit (53), which is the inverse of the output (534) is also sent to the input (501). A character color control circuit (51) receives on its input (510) the output (254) transmitting the serialization clock signal (SHCLK). The output (511) of this circuit (51) is connected to the input (502) of the multiplexing circuit. The input (512) of this circuit (51) receives the output (214) of the attribute decoding circuit (21). A background color control circuit (52) receives on its input (520) the output (254) which transmits the serialization clock signal (SHCLK). The output (521) of this circuit (52) is connected to the input (503) of the multiplexing circuit (50). The input (522) of this circuit (52) is connected to the output (215) of the attribute decoding circuit (21). This attribute decoding circuit receives on its input (216) the output (231) of the circuit (23) constituted by the configuration register. The input (232) of this circuit (23) receives the reset signal (RESET) supplied by the video display controller (11). The input (234) receives the signal (WDB) supplied by the output (CTRL1) of the video display controller (11), a signal for writing data to the memory buffers (12, 13). The input (233) of the circuit (23) receives the nine lines respectively (130, 120) representing respectively the character attribute signals (CAD to CA7) and the signal of the most significant bit of the character address. (CB7). These signals are also sent to the input (220) of the circuit (22) constituted by the character attribute register whose output (221) is connected to the input (217) of the decoding circuit (21). attributes. The output of the circuit (11) delivering the signal (CURSOR) is connected to the input (218) of the attribute decoding circuit (21). The eight control lines (320, 330) delivered by the circuit (11) are connected to the inputs of the circuits (32) and (33) constituting the line attribute registers. The inputs (321, 331) of these circuits receive the blanking signal (BLANK) delivered by the corresponding output of the circuit (11) video display controller. The output lines (332) of the line attribute register are connected on the one hand to the inputs of the circuit (31) of the double height logic, and on the other hand to the input (219) of the circuit (21) attribute decoding. Finally, the vertical synchronization circuit (34) receives the output lines (322) from the line attribute register (32). The output (340) of this circuit (34) delivers the vertical synchronization signal of the video. Finally, a horizontal synchronization circuit (24) receives as input the HSYNC and BLANK signals delivered by the corresponding outputs of the cathode ray tube controller circuit (11). The output (240) delivers the signal HRTC for controlling the tube and the output (241) delivers the signal BKFIELD to the input (535) of the circuit (53) for inverting the bottom.

For its operation, the circuit of FIG. 2 first receives a configuration byte loaded by a write command to the address of a pointer whose address is greater than 2 ^13. This configuration byte is represented in the figure 6 on which it can be seen that the two least significant bits (DIVO, DIV1) make it possible to determine the width of the character. The next bit called BFM is used to modify the extension mode of the serializer, when this BFM bit is at zero the serializer performs an extension of the character range while, when this BFM bit is at one the serializer sends 8 bits. The bit (COL), according to its value "0" or "1" selects the color mode, the DSEN bit selects according to its value the validation of enlargement of the point, VTX selects the videotex mode, the 7th bit is unused and the 8th bit REVS selects the video inversion of the screen. The first two bits DIVO and DIV1 select the width of the character according to their value. These bits select the character widths according to Table 1 below

FIG. 7 represents the byte (AO to A7) of character attributes and the byte (BO, B7) of the character's address in the case of a display in alphanumeric mode selected by setting the bit to zero ( VTX) and in monochrome mode selected by the value of the bit (COL) at zero. Character attribute bits (AO) to (A7) indicate low weights towards increasing weights the following operations: bit (DL) selects double line width and this bit is active on the first character of a row only. The bit (CS) controls the column separator, the bit (UL) controls the underlining of characters, the bit (RV) controls the video inversion, the bit (BL) controls the flashing, the bit (BK) controls the secret , the bit (LI) controls the under-brightness so as to reduce the brightness of the display of a character.

• - une commande de propagation des attributs qui est obtenues en positionnant le bit (A7) de l'octet d'attributs à "1" et tous les autres bits de cet octet à "0". Dans ce cas, tant que la configuration de l'octet attributs reste égale au code (80) en hexadécimal, les derniers attributs restent mémorisés et s'appliquent à tous les caractères visualisés. Toutefois le premier caractère de chaque rangée doit porter la configuration explicite des attributs choisis.
• - la deuxième commande spéciale est l'effacement ligne qui est constitué par tous les bits de l'octet attribut à zéro, ce qui permet de masquer le signal vidéo (RGB) jusqu'à la fin de la rangeée courante. Ce signal (RGB) est forcé à la valeur "000" si l'écran est en mode normal et à la valeur "111" " si l'écran est en mode inverse.

FIG. 8 represents the attribute byte (AO to A7) and the character address byte (BO, B7) in the case of an alphanumeric display in color mode, with the bit (in the configuration register) ( COL) to "1". In the attribute byte the bit (B) controls the blue color, the bit (V) controls the green color, the bits (UL, RV, BL and BK) have the same functions as in the case of monochrome and the bit (R) controls the color red. Note in Figures 7 and 8 that the bit (A7) is at zero which allows to have the following two special commands:

• - a command to propagate the attributes which is obtained by setting the bit (A7) of the attribute byte to "1" and all the other bits of this byte to "0". In this case, as long as the configuration of the attributes byte remains equal to the code (80) in hexadecimal, the last attributes remain memorized and apply to all the characters displayed. However, the first character in each row must bear the explicit configuration of the attributes chosen.
• - the second special command is the line erasure which consists of all the bits of the attribute byte at zero, which makes it possible to mask the video signal (RGB) until the end of the current row. This signal (RGB) is forced to the value "000" if the screen is in normal mode and to the value "111""if the screen is in reverse mode.

FIG. 9 represents the coding of the attributes and alphanumeric characters in videotex mode, that is to say with the bit (VTX) equal to "1" in the configuration byte. Switching to videotext mode results in a halving of the base clock for (CLK). The width of the character in this mode will be programmed on 8 points by setting the bits (DIV1) and (DIVO) to 0. In this mode the color bit (COL) has no more action, the bit (DSEN) although 'usable is not necessary and will be programmed at zero, the inverse function although valid must be programmed at zero to satisfy videotex standards. In the attribute byte of Figure 9 the bits (CO) to (C2) are used to define the color of the character. With a color monitor the bit (CO), at the value "1" controls the color blue, the bit (C1) at the logic value 1, the color red, the bit (C2) at 1, the color green. In the case where a monochrome monitor is used, the three bits (C2, C1, CO) make it possible to establish the gray level (C2) being the most significant and (CO) the least significant. The bit (BL) allows to control the flashing of the character, the bit (DH) controls the double height display, the bit (DL) controls the double width display and the bit (RV) controls the display with inversion the bottom.

It will be noted that the byte of the character code has its most significant bit (B7) has the logical value "0" which makes it possible to select 128 alphanumeric characters in videotex mode.

FIG. 10 shows the character attribute byte and the character code byte in the videotex display mode for semigraphic characters. In this byte, the bits (C2, C1, CO) make it possible to determine the color of the character as before or to define 8 levels of gray, the bit (BL) controls the flashing display of the character and the bits (BO, B1, B2 ) allow the background color to be determined with the same conventions as for the definition of the character color in the case of a color display and in the case of a monochrome display allow to define eight gray levels. Bit (A7) is always "0". The most significant bit of the character code (bit B7) is at level "1" to indicate that we are dealing with semigraphic characters and the bits (BO) to (B6) allow to select 128 semigraphic forms including 64 are said to be separate or lined. These 64 separate or lined semigraphic forms are selected when the bit (L) is equal to "1 Note that this bit (L) is not processed in the circuit of FIG. 2 but is simply used to address in the ROM (15 ) the lined semigraphic characters.

Finally, Figure 11 shows the attribute byte and the character code byte of a character called a delimiter. The bits (CO) to (C2) of the attribute byte of this delimiter character make it possible to determine the color of the delimiter character. The bit (BK) at "1" hides the characters following the delimiter character until the end of the row or until the next delimiter in which the bit (BK) is equal to "0". A delimiting character is displayed as a space, not underlined, not flashing, the color of which is defined by the bits (C0, C1, C2). The bits (BO, B1, B2) define the background color for the alphanumeric characters following the delimiter character. And this until the end of the row or until the next delimiter. The bit (A7) of the attribute byte of the delimiter character is at level "1" which makes it possible to distinguish this character from the preceding ones by the presence of this bit (A7). The eighth bit of the character code (B7) enables the underlined display function to be implemented. This bit (UL) when it is at level "1" allows to underline the zone which follows the delimiter character. The other bits of the character code (BO) to (B6) are all at level "1". The use of the functions of the diagram of FIG. 2 combined with the attribute and character codes of FIGS. 7 to 10 makes it possible to carry out the different display combinations which we have just seen when describing the attribute and character codes above.

The functions of the various circuits of the video attribute decoder having been described, the circuits making it possible to carry out each of these functions are conventional for those skilled in the art except for the point widening function and the function of the double height logic circuit. For conventional circuits for those skilled in the art, what is original in the attribute decoder circuit is the combination of the different functions between them and in particular the combination of these conventional functions with the function of widening the point and the double height logic whose embodiments will be described.

FIG. 3 represents the double height logic circuit (31) associated with the line attribute registers (32, 33) and with the vertical synchronization circuit (34). A first line attribute register (32) receives on its four inputs the signals (UL), (BLINK), (LL) and (LR). These signals supplied by the circuit (11) respectively indicate the underline, the flashing, the last row, the last line. These registers are synchronized by the erasure signal (BLANK) delivered by the circuit (11). The second re gistre (33) receives on its four input lines the line attributes (LAO) to (LA3) which, in fact, define in the character matrix the line or the range of characters that will be processed. The registers (32) and (33) are reset by a signal (MRST). The outputs (33-1 Q) to (33-4Q) of the register (33) constitute the lines (332) of the double height logic. This double height logic comprises a register (3100) for memorizing the signals delivered at the output of the line attribute register, this memorization being effected when the last line signal (LL) is active on the output of the flip-flop (32-4Q ^* ). Consequently, the storage of line attribute signals takes place in circuit 3100 when the last line of a character is being processed. The inverted outputs (1Q ^* ) to (4Q ^* ) of the register (3100) for memorizing the last line of the character are sent to the set of 4 NOR gates with two inputs constituting a circuit (3110) for selecting between the value represented by the last character line and a null value. The outputs of this NOR gate assembly (3110) are connected to the four inputs (B1) to (B4) of an adder circuit (3120) whose other inputs (A1) to (A4) receive the output signals from the outputs (1Q) to (4Q) of the register (33). The input (CI) of the adder (3120), of addition of the carry is connected to the output (Q) of a rocker (314) whose output (Q) at level "1" means, in the case where we are processing a double height character that we are processing the lower part of a character. By lower part of a character means in the case for example of a capital T, the lower part of the vertical bar of the T. The output (Q ^* ) of the rocker (314) delivers the signal (TOP) which indicates that we are processing the top of a character when this signal is at level "1". This output (Q ^* ) of this flip-flop (314) is connected to each of the second inputs of the four NOR gates constituting the circuit (3110) and on the other hand to the input of a NAND gate (3140) whose second input receives the output (Q ^* ) of a flip-flop (3141) which delivers on this output (Q ^* ) the signal (DBLH) indicating when it is at level "1" that one is in the process of process a double height character. When the signal (TOP) delivered by the output (Q ^* ) of the flip-flop (314) is at level "1", the outputs of the circuit (3110) are at level "0". On the other hand when the output (Q ^* ) of the rocker (314) is on level "0" which indicates that one is processing the lower part of a double height character, the outputs of the circuit (3110) reproduce the signals (LLLAO) (LLLA3). These signals are sent to the respective inputs (B1) to (B4). The signals (LLLAO) to (LLLA3) correspond to the line attributes of the last line of the character in its upper part and are delivered by the circuit (3100). The clock input of the flip-flop (314) receives the output signal (4Q ^* ) from the register (32), this signal (LL ^* ) corresponds to the inverse signal of the last line. The input (D) of the flip-flop (314) is connected to the output (Q) of a flip-flop (3143) whose input (S) for setting to "1" is connected to the output of the gate NON- AND (3140). The clock input of this flip-flop (3143) is also connected to the output (4Q ^* ) of the register (32). The flip-flop reset inputs (R) (3143) and (314) are both linked to the signal (VRRST ^* ), video reset signal. The flip-flop (3141) receives on its input (D) the output of a NAND gate (3142) with four inputs. The inputs of this NAND gate are respectively the signals (VTX) indicating the videotex mode, the signal (A7 ^* ) indicating that the character is not delimiting or that one is not making a propagation of attributes, the signal (RC7 ^* ) indicating that a semi-graphic character is being processed, the signal (A4) which when it is at level "1" corresponds to the bit (DH) of FIG. 9 and indicates that the we want to display a double height character. Consequently when one is in videotex mode without delimiter or propagation of attributes and that one selected the double height, the exit of the door NAND (3142) is on level "0" what causes the passage at "1" of the output (Q ^* ) of the scale (3141). The flip-flop (3141) receives on its clock input the signal (VCCLK) coming from the circuit (25) and constituting the video character clock signal. The input (S) of this flip-flop (3141) receives the signal (ROWRST) which commands a reset of a row. The outputs (S2, S3, S4) of the adder (3120) are respectively connected to the inputs (4A, 3A, 2A) of a multiplexing circuit (3130). The input (1A) of the multiplexing circuit (3130) receives the output (CO) of the adder (3120), output which delivers the signal to retain the addition. The inputs (1 B) to (4B) of the multiplexer. (3130) respectively receive the outputs (1Q) to (4Q) of the line attribute register (33). These outputs respectively represent the signals (LA3) to (LAO). The control input (3131) of the multiplexing circuit controlling the switch between the input channels (A) and the input channels (B) on the output of the multiplexer is connected to the output of the NAND gate (3142). This output delivers the signal (DBLH ^* ) which is at level "1" when you are not trying to display a double height character. In this case the input (3131) controls the switch on the channels (B) and consequently the line attributes (LAO) to LA3 are directly transmitted to the outputs (4Y) to (1Y) of the multiplexer (3130), these outputs constituting the lines (313) delivering respectively (LCO) to (LC3) to the character coding read-only memory. Lines (LCO) to (LC3) are used to code the character slices which will be serialized for display.

Les figures 4, 5 représentent le circuit d'élargissement du point et son association avec les autres blocs fonctionnels du décodeur d'attributs vidéo. Les signaux (CCO) à (CC7) sortant de la mémoire morte (15) sont envoyés sur les entrées correspondantes du circuit (41) représenté à la figure 4. Dans le cas de l'exemple choisi à la figure 12 pour la tranche des caractères 0, les signaux (CCO) à (CC4) sont successivement et dans l'ordre 0 1 1 0. Les 10 lignes de sortie (411) du circuit (41) permettent d'étendre le code caractère sur 10 bits suivant les valeurs des signaux de commande (COLSEP-CMD) et (BF-MODE) qui représentent respectivement la commande d'attribut de séparation verticale et le mode d'extension du sérialisateur (40). Les signaux (BLANK-CMD) et (SET-CMD) sont les signaux de commande d'effacement et le signal de commande de mise à "1" du circuit. Ces signaux de commande permettent par l'intermédiaire des portes NON-ET (4100) à (4119) de masquer ou de mettre à "1" l'ensemble des codes caractères. Les 10 lignes parallèles de sortie (411) du circuit de masque (41) sont sérialisées dans le sérialisateur (40) constitué par 3 registres à décalage (4001) à (4003) dont les sorties série sont chainées et les entrées parallèles reçoivent les 10 lignes de sortie (411 ). La commande du décalage et de la sérialisation est effectuée par le signal (SHCLK), signal d'horloge de sérialisation envoyé sur l'entrée (400) du boitier (4001). Le signal sérialisé permettant l'affichage vidéo est représenté par la ligne (SRD), données sérialisées, qui est liée à la sortie (4Q) du boitier (4003). La sortie de données sérialisées inverse (SRD^*) est constituée par la sortie (4Q^*) du même boitier. Les entrées de chargement des registres à décalage de sérialisation sont commandées par le signal (SLOAD^*) signal de chargement pour la sérialisation. Le signal (DSEN^*) d'invalidation de l'élargissement du point et le signal (SLOAD) de chargement de la sérialisation sont envoyés sur une porte (NON-OU) (5404) dont la sortie est envoyée sur l'entrée de remise à "1" d'une bascule (540). Donc lorsque le chargement série et l'invalidation de l'élargissement du point sont à zéro la sortie de la porte (5404) via commander la remise à "1" de la bascule (540). La bascule (540) reçoit sur son entrée d'horloge la sortie d'un inverseur (5405) dont l'entrée reçoit le signal (SHCLK) qui est le signal d'horloge de sérialisation. Ce signal d'horloge de sérialisation est inversé par l'inverseur (5405) qui délivre le signal (SHCLK^*). Cette bascule (540) de type D reçoit son son entrée (D) le signal (SRD) et délivre sur sa sortie (Q) le signal (SRDX), signal de sérialisation des données retardées et sur sa sortie (Q^*) le signal (SRDX^*), signal de sérialisation des données inversées et retardées. Ainsi si l'on se réfère à la figure 13, la ligne (SHCLK) représente la périodicité du signal d'horloge de signalisation, la ligne (SHCKL^*) représente le signal d'horloge de sérialisation décalé d'une demi période, le signal (SRD) représente le signal de sérialisation des données dans le cas où l'on a à afficher un point appartenant à un barre verticale telle que le premier point de la tranche 1 du caractère A de la figure 12. Ce signal (SRD) délivré par la sortie (4Q) du registre à décalage a une durée égale à une période entière du signal d'horloge de sérialisation qui commande les registres de sérialisation du circuit (40). Le signal (SRDX) délivré par la sortie (Q) de la bascule (540) est comme on peut le voir sur la figure 13 décalé d'une demi période par rapport au signal (SRD). Une logique constituée par les circuits (5400, 5401, 5402, 5403) permet, en fonction des signaux délivrés par un circuit (541) d'inversion du point, de délivrer un signal (E) tel que celui représenté à la figure 13. Ce signal (E) comme on peut le voir a été prolongé d'une demi période par rapport au signal (SRD). Par conséquent, on a élargi le premier point de la tranche 1 du A d'une valeur sur l'écran correspondant à une demi période de l'horloge. Ce circuit permet donc d'uagmenter la luminosité des barres verticales dans les caratères contenant ces barres verticales. Par contre sur les barres horizontales ce circuit ne présente aucun inconvénient puisque le résultat final sur une barre horizontale est de prolonger cette barre d'une demi période. La porte NON-ET (5401 ) à 3 entrées reçoit sur sa première entrée le signal (SRDX^*), signal de sérialisation retardé et inversé, sur sa deuxième entrée le signal (SRD^*), signal de sérialisation inversé et sur sa troisième entrée le signal délivré par la sortie (Q) d'une bascule (5401). La sortie de cette porte NON-ET (5401) est envoyée sur une première entrée d'une porte NON-ET (5400) délivre au circuit de multiplexage (50) le signal (E) représenté à la figure 13. Un inverseur (5406) branché à la sortie (542) permet de délivrer sur sa sortie un signal (E^*), signal inverse, qui est envoyé également au multiplexeur (50). La deuxième entrée de la porte NON-ET (5400) reçoit la sortie d'une porte NON-ET (5402) à 2 entrées dont la première entrée reçoit le signal (SRDX) signal de sérialisation des données retardées et la deuxième entrée reçoit la sortie (Q^*) d'une bascule (5410). La troisième entrée de la porte NON-ET (5400) reçoit la sortie d'une porte NON-ET (5403) à 2 entrées dont la première entrée reçoit le signal (SRD), signal de sérialisation des données, et la deuxième entrée reçoit la sortie (Q^*) d'une bascule (5410). La sortie (Q) de la bascule (5410) indique lorsqu'elle est au niveau "1" que le point correspondant du caractère doit être inversé. Dans ce cas cette sortie (Q) qui est envoyée sur la porte NON-ET (5401) valide les entrées de cette porte NON-ET et c'est le signal de sortie de cette porte NON-ET (5401) qui est transmis au travers de la porte NON-ET (5400) pour constituer le signal (E). En effet (Q) étant au niveau "1", (Q^*) est au niveau "0" et par conséquent le portes NON-ET (5402, 5403) délivrent en sortie les niveaux "1" qui servent uniquement à valider la transmission du signal de sortie de la porte. (5401). Dans le cas inverse, (Q) vaut "0" et la sortie de la porte (5401) est au niveau "1" et valide sur la porte (5400) la transmission des signaux de sortie des portes (5402, 5403). Dans ce cas (Q^*) est au niveau "1" et par conséquent le signal (SRDX) reçu en entrée de la porte (5402) est recopié après inversion sur la sortie et le signal (SRD) subit le même sort dans la porte (5403). En entrée de la porte (5400) on dispose donc du signal (SRDX) inversé et (SRD) inversé ce qui, dans la porte NON-ET (5400) qui est équivalente à deux inverseurs en entrée et une porte OU à la suite, assure sur la sortie (542) l'addition des deux signaux (SRD) et (SRDX) et par conséquent la fourniture du signal d'élargissement du point. Le circuit de commande d'inversion du point (541) est constitué d'une bascule (D) (5410) dont l'entrée (D) de commande reçoit la sortie d'une porte NON ET (5411) à deux entrées. La première entrée de cette porte NON-ET (5411) reçoit la sortie d'une porte NON-ET (5412) à deux entrées, dont la première entrée reçoit le signal (REV-CMD) signal de commande de l'inversion qui est fourni par le bit (RVS) de l'octet de configuration représenté à la figure 6. La deuxième entrée de cette porte NON-ET (5412) reçoit le signal (SLOAD) signal de commande du chargement du sérialisateur. Ce signal est également envoyé sur la première entrée d'une autre porte NON-ET (5413) à 2 entrées. Cette porte NON-ET (5413) reçoit sur sa deuxième entrée la sortie (Q^*) de la bascule (5410). La sortie de cette porte NON-ET (5413) est envoyée sur la deuxième entrée de la porte (5411). La bascule (5410) est synchronisée avec le reste du circuit par le signal (SHCLK), cette bascule est réini- tialisée par le signal (VRST^*), signal de réinitialisation de la vidéo.To make it easier to understand the explanations for the operation of the double height circuit, we have shown in Figure 12 on the left a character (A) represented in single height by a matrix of 8 sections of 5 columns each and on the right of Figure 12 the same character represented in double height. The numbers 0 to 7 for the single height character designate the slice numbers, numbers which are binary coded by the lines (LAO) to (LA3). To simplify the explanations we limited the coding of the lines on 3 attribute lines (LAO) to (LA2). In the column appearing between the single character and the double height character are indicated the decimal values corresponding to the binary coding of the lines (LAO) to (LA2) giving a display cycle of double height character. To the right of the double height character, the value of the signal (TOP) has been indicated, indicating whether the upper part or the lower part of the double height character is being processed and in the display points of the double height character, the decimal values corresponding to the binary coding of the signals (LCO) to (LC3) have been indicated. The table below makes it possible to understand the operation of the circuit in the case of the coding of the slices of a character on 3 lines (LAO) to (LA2) and the transformation of this coding to allow display. Transformed coding is output on lines (LCO) to (LC2). In column N, the decimal values corresponding to the section numbers of a single-height character appear, while in column NC corresponds the decimal values of the section number which must be selected in the read-only memory (15) to allow display. double height character. Thus for the upper part of the double height character represented by the portion of the table in which the signal (TOP ^* ) is equal to "0", the circuit behaves for the values (LCO) to (LC2) as a multiplier by 2 of values (LAO) to (LA2). In this way, on the first two lines of the upper part of the double height character, we will select twice the slice 0 of the character. Similarly for sections 6, 7 of the upper part of the double height character, we will select twice section 3 of the single height character. When we pass in the lower part of the double height character, lower part which is signaled by the signal (TOP ^* ) to the logical value "1", we add the signal corresponding to the line of attributes being processed for the single height character with the retained signal consisting of the signal value (TOP ^* ) and the signal (LLA) corresponding to the value of the attribute line for the last line of the single height character before switching to processing lower part. This signal (LLA) consists of the bit values represented in the dotted frame of line 7. The result of the respective additions gives the respective values of the signals (S1) to (CO) for the lower part of the table corresponding to the display of the lower part of the character. Thus after having eliminated by wiring the values taken by (S1) we find the values of (S2, S3, S4) respectively on the outputs (LCO, LC1, LC2) of the multiplexer circuit. Indeed, we recall that we are in the case where the switch input (3131) selects the channels (A) and consequently the outputs of the adder circuit since the signal from the gate output NAND (3142) is at level "0". In this way the first two lines of the lower part of the double height character are constituted by the sections 4,4 of the single height character and the last two lines of the double height character are constituted by the sections 7,7 of the single height character. The signals (LCO) to (LC3) associated with the signals passing on the line (140) will allow the selection of the character range concerned and the ROM (15) will therefore transmit on the 8 lines (CC) represented by the link (150 ) the bit values corresponding to the required display. These 8 lines (CCO) to (CC7) are found in Figure 4 which represents the mask circuit associated with the serializer (40) and the point widening circuit. It is quite obvious that for reasons of simplification of explanations we represented the character with 5 columns and 8 lines but that the same circuit applies as well to characters constituted by matrices of 10 to 16 lines and of 8 to 10 columns. The advantage of this double height display circuit is precisely that it is independent of the number of lines or slices of characters.

Figures 4, 5 show the point widening circuit and its association with the others functional blocks of the video attribute decoder. The signals (CCO) to (CC7) leaving the read-only memory (15) are sent to the corresponding inputs of the circuit (41) represented in FIG. 4. In the case of the example chosen in FIG. 12 for the range of characters 0, the signals (CCO) to (CC4) are successively and in the order 0 1 1 0. The 10 output lines (411) of the circuit (41) allow the character code to be extended over 10 bits according to the values control signals (COLSEP-CMD) and (BF-MODE) which respectively represent the vertical separation attribute control and the extension mode of the serializer (40). The signals (BLANK-CMD) and (SET-CMD) are the erase control signals and the circuit control signal to "1". These control signals make it possible, via the NAND gates (4100) to (4119), to hide or set all the character codes to "1". The 10 parallel output lines (411) of the mask circuit (41) are serialized in the serializer (40) constituted by 3 shift registers (4001) to (4003) whose serial outputs are chained and the parallel inputs receive the 10 output lines (411). The shift and serialization are controlled by the signal (SHCLK), serialization clock signal sent to the input (400) of the box (4001). The serialized signal allowing the video display is represented by the line (SRD), serialized data, which is linked to the output (4Q) of the box (4003). The reverse serialized data output (SRD ^* ) consists of the output (4Q ^* ) of the same unit. The loading inputs of the serialization shift registers are controlled by the signal (SLOAD ^* ) loading signal for serialization. The signal (DSEN ^* ) for invalidating the enlargement of the point and the signal (SLOAD) for loading the serialization are sent to a door (NOR) (5404) whose output is sent to the reset input to "1" of a rocker (540). So when the serial loading and the invalidation of the widening of the point are at zero the output of the door (5404) via command the reset to "1" of the rocker (540). The flip-flop (540) receives on its clock input the output of an inverter (5405) whose input receives the signal (SHCLK) which is the serialization clock signal. This serialization clock signal is inverted by the inverter (5405) which delivers the signal (SHCLK ^* ). This flip-flop (540) of type D receives its input (D) the signal (SRD) and delivers on its output (Q) the signal (SRDX), serialization signal of the delayed data and on its output (Q ^* ) the signal (SRDX ^* ), serialization signal for inverted and delayed data. Thus if we refer to FIG. 13, the line (SHCLK) represents the periodicity of the signaling clock signal, the line (SHCKL ^* ) represents the serialization clock signal shifted by half a period, the signal (SRD) represents the data serialization signal in the case where we have to display a point belonging to a vertical bar such as the first point of section 1 of character A of figure 12. This signal (SRD) delivered by the output (4Q) of the shift register has a duration equal to an entire period of the serialization clock signal which controls the serialization registers of the circuit (40). The signal (SRDX) delivered by the output (Q) of the flip-flop (540) is as can be seen in FIG. 13 shifted by half a period compared to the signal (SRD). Logic constituted by the circuits (5400, 5401, 5402, 5403) makes it possible, as a function of the signals delivered by a circuit (541) for reversing the point, to deliver a signal (E) such as that represented in FIG. 13. This signal (E) as can be seen has been extended by half a period with respect to the signal (SRD). Consequently, the first point of section 1 of A has been widened by a value on the screen corresponding to half a period of the clock. This circuit therefore makes it possible to increase the brightness of the vertical bars in the characters containing these vertical bars. By cons on the horizontal bars this circuit has no drawbacks since the end result on a horizontal bar is to extend this bar by half a period. The NAND gate (5401) with 3 inputs receives on its first input the signal (SRDX ^* ), delayed and inverted serialization signal, on its second input the signal (SRD ^* ), inverted serialization signal and on its third input the signal delivered by the output (Q) of a rocker (5401). The output of this NAND gate (5401) is sent to a first input of a NAND gate (5400) delivers to the multiplexing circuit (50) the signal (E) shown in Figure 13. An inverter (5406 ) connected to the output (542) makes it possible to deliver on its output a signal (E ^* ), reverse signal, which is also sent to the multiplexer (50). The second input of the NAND gate (5400) receives the output of a NAND gate (5402) with 2 inputs, the first input of which receives the signal (SRDX) serialization signal of the delayed data and the second input receives the output (Q ^* ) of a scale (5410). The third input of the NAND gate (5400) receives the output of a NAND gate (5403) with 2 inputs, the first input of which receives the signal (SRD), data serialization signal, and the second input receives the output (Q ^* ) of a flip-flop (5410). The output (Q) of the flip-flop (5410) indicates when it is at level "1" that the corresponding point of the character must be inverted. In this case this output (Q) which is sent to the NAND gate (5401) validates the inputs of this NAND gate and it is the output signal from this NAND gate (5401) which is transmitted to the through the NAND gate (5400) to form the signal (E). Indeed (Q) being at level "1", (Q ^* ) is at level "0" and consequently the NAND gates (5402, 5403) deliver at output levels "1" which are used only to validate the transmission of the door output signal. (5401). In the opposite case, (Q) is equal to "0" and the output of the door (5401) is at level "1" and validates on the door (5400) the transmission of the output signals of the doors (5402, 5403). In this case (Q ^* ) is at level "1" and consequently the signal (SRDX) received at the input of the door (5402) is copied after inversion on the output and the signal (SRD) undergoes the same fate in the door (5403). At the input of the gate (5400) there is therefore the signal (SRDX) inverted and (SRD) inverted, which in the NAND gate (5400) which is equivalent to two inverters at the input and an OR gate in succession, ensures on the output (542) the addition of the two signals (SRD) and (SRDX) and therefore the supply of the point widening signal. The reverse control circuit of the point (541) consists of a flip-flop (D) (5410) whose control input (D) receives the output of a NAND gate (5411) with two inputs. The first input of this NAND gate (5411) receives the output of a NAND gate (5412) with two inputs, the first input of which receives the signal (REV-CMD) inversion control signal which is supplied by the bit (RVS) of the configuration byte shown in Figure 6. The second input of this NAND gate (5412) receives the signal (SLOAD) signal for command to load the serializer. This signal is also sent to the first input of another NAND gate (5413) with 2 inputs. This NAND gate (5413) receives on its second input the output (Q ^* ) of the flip-flop (5410). The output of this NAND gate (5413) is sent to the second input of the gate (5411). The flip-flop (5410) is synchronized with the rest of the circuit by the signal (SHCLK), this flip-flop is reset by the signal (VRST ^* ), video reset signal.

The operation of the point reversal circuit is as follows. When the signal (REV-CMD) is at level "1" so as to indicate a command to invert the character point due to the cursor, the output (Q) of the flip-flop (5410) is at level "0" and the output (Q ^* ) is at level "1". As we are carrying out a character output the signal (SLOAD) is also at level "1". Consequently the doors (5412) and (5413) receiving on their inputs of the levels "1" deliver at the output of the levels "0". The door (5411) receiving levels "0" at the input delivers at the output a level "1" which attacks the input (D) of the scale (5410) and causes the output (Q) to pass from the level "0" to the level "1" at the next clock stroke (SHCLK). At this time (Q ^* ) goes to level "0" and consequently the output of the door (5413) goes to level "1" and the output of the door (5411) maintains the value of the signal (REV-CMD) . As soon as this reversing control signal returns to level "0" the output of the door (5411) also passes to level "0" which causes the output (Q) of the rocker (5410) to drop back to level "0" . In this case we no longer reverse the point. The multiplexing circuit (50) consists of 3 NAND gates (5001, 5002, 5003) whose respective outputs represent the signals (R, G, B), signals for controlling the display of the respective red color, green, blue. The output door (5001) receives on the first of its 3 inputs the output of a NAND gate (5010) with 3 inputs whose first input receives the signal (E) the second input receives one of the output lines ( 511) of the character color control circuit (51). This line (511) being constituted by the line controlling the color red. The third input of the door (5010) receives an output line (531) from the circuit (53) for controlling the inversion of the bottom. The output line (531) delivers the signal RBLANK ^* which controls the erasure of the screen when it is at logic level "0". The second input of the door (5001) receives the output of a door (5020), the first input of which receives the output of the inverter (5406) delivering the signal (E ^* ). The second input receives one of the output lines (521) of the circuit (52) for controlling the background color of the screen. This line being that which corresponds to the command of the red color of the background. The third entry of this door (5020) receives the line (531). The third input of the door (5001) receives the output of a door (5004) with 2 inputs, the first input of which receives a signal (REVSCREEN), signal for inverting the screen when it is at logic level "1 ". This signal (REVSCREEN) is provided by line (530). The second input of this door (5004) receives the output (534) of the bottom inversion circuit (53). This output (534) supplies the signal RBLANK of blanking of the screen, controlling the blanking of the screen when it is at logic level "1". The NAND gate (5200) corresponding to the green color will also be connected to a gate (5011) whose output will determine the color of the shape of the character, to a gate (5021) whose output will determine the background color and to a door (5005), the output of which will determine whether the screen should be inverted. In the same way the door (5003) whose output delivers the control signal of the blue color on a color monitor will be connected to the output of a door (5012) whose output determines the color of the shape of the character, at the exit of the door (5022) whose exit will determine the background color and at the exit of a door (5006) which will control the inversion of the screen. The circuits (51, 52) each consist of a register (5110, respectively 5210) with 3 flip-flops, synchronized by the signal SHCLK and reinitialized respectively by the signals VRRST ^* and ROWRST ^* . The three outputs Q of each of these registers are connected to the inputs 1A to 3A of the respective multiplexers 5100, 5200. The inputs 1 B to 3B of the multiplexer 5100 receive the REDFORG signals for controlling a red character GREFORG for controlling the character green, BLUFORG command of a blue character. Similarly, the inputs 1 B to 3 B of the multiplexer 5200 receive the signals A6 to A4 for controlling a background of red, green and blue respectively. The multiplexers (5100, 5200) are controlled respectively by the FORGEN and BAKGEN character validation and background signals respectively. The FORGEN and BAKGEN signals make it possible to take into account the respective color commands (REDFORG to BLUFORG and A6 to A4) by registers 5110 at 5210 during the first pixel of a character. Then the looping back of the outputs Q on the inputs A of the multiplexers ensures that the commands are maintained throughout the character, while the signals REDFORG to BLUFORG and A6 to A4 already correspond to the next character.

The other circuits carrying out the functions described in FIG. 2 being conventional circuits for those skilled in the art will not be described in more detail.

Claims (5)

1. Video attributes decoder for colour or monochrome display in a high definition alphanumeric mode or a videotext mode with the option, in the videotext mode, between the alphanumric mode and the semigraph- ic mode, comprising a clock circuit (25), a configuration register (23), a character attributes register (22), a line attributes register (32, 33), an attributes decoding circuit (21) connected to these different registers, a characters masking circuit (41), a serialiser (40) connected to this masking circuit (41) and to the clock circuit (25), a background inversion circuit (53), a circuit (51) for controlling the character colour and a circuit (52) for controlling the background colour, these last 3 circuits being connected at the input to the attributes decoding circuit and at the output to a circuit (50) for multiplexing and for controlling the monitor guns, characterized in that the output (402) of the serialiser circuit (40) is sent to a dot broadening circuit (54) of which the output (542) is connected to an input of the circuit (50) for multiplexing and controlling the monitor guns, and in that it also comprises a double-height logic circuit (31) connected on the one hand to the line attributes register (33) and on the other hand to selection lines (LCO, LC3) of a group of characters in a character generator read-only memory (15).

2. Controller according to claim 1, characterized in that the double-height circuit (31) allows the height of the characters to be doubled regardless of the number of character groups contained in a character of standard height.

3. Controller according to claim 1, characterized in that the dot broadening circuit (54) allows the dot to be broadened by a predetermined value corrresponding to half a clock cycle, regardless of the display mode adopted, whether direct or inverted.

4. Controller according to claim 3, characterized in that the dot broadening circuit comprises a clock signal inverter (5405), a delay flipflop (540) for the data and inverted data serialisation signal and a combinational logic (5400) to (5403) between the data signals, the inverted data signals and the same signals delayed as a function of the direct or inverted display mode determined by a circuit (541).

5. Controller according to one of the claims 1 or 2, characterized in that the double-height logic circuit (31) comprises means (3100) for memorising the address of the last character line, means (3110) for generating a constant value and means (3120) for adding this constant value to the signal representing the character group in the course of processing supplied by means (3130) of storing the character group in the course of processing and means (3120) for dividing the result by two to constitute the address of the character group fed to the group address inputs of the character generator read-only memory (15) and means (3130) for selecting either the outputs of the summator/divider or the outputs of the line attributes register (33).

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